JPH11164377A - Time division multiplexed memory switching device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce scale of a signal processing and a device by simplifying structure at front and rear stages of a TSW (time division multiplexed memory switch) in an optical transmission network, etc. SOLUTION: All of (n) pieces of input signals are inputted in each of (n) pieces of selection circuits 21 to 2n and an input signal with (i)th bit is selected based on switched data from a control system 10. Bits to be replaced by each of the TSWs 31 to 3n are replaced in a time axis direction for an output signal. Output of the TSW3j is selected and transmitted for the (i)th bit in (n) bit of (n) pieces of the input signals for all the output signals afterwards by selection circuits 41 to 4n. In this case, (j)=1 when (i)=1 and J=2-(i)+(n) when (i)>1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bit-slice type time-division multiplexing memory switching device, and more particularly, to a time-division multiplexing method for mutually exchanging at least one set of a plurality of n-bit input signals. The present invention relates to a memory switching device.

[0002]

2. Description of the Related Art FIG. 6 is a block diagram showing a configuration of a conventional time-division multiplexing memory switching device. The time-division multiplexing memory switching device has n input terminals 11, 12,.
N input signals of bits are provided correspondingly. These n signals are signals for which phase synchronization between bits has not been established.

[0003] For the n input signals, n serial / parallel (S / P) separation circuits 61, 62 ... 6n are provided, and the i-th S / P separation circuit 61 ... 6n includes: The input signals of the i-th input terminals 11... 1n are supplied. Further, n parallel / serial (P / S) multiplexing circuits 71, 72,.
n of the P / S multiplexing circuits 71... 7n
6n receives all of the n output signals of the S / P separation circuits 61... 6n.

FIG. 7 is a diagram showing the timing of input signals to n input terminals 11... 1n, and FIG. 8 is a diagram showing the timing of output signals of P / S multiplexing circuits 71. As shown in FIGS. 7 and 8, by combining the S / P separation circuits 61... 6n and the P / S multiplexing circuits 71.
T2 · 1, T3 · 1, T4 · · · · · Tn · 1 / bit T1
· 2, T2 · 2, T3 · 2, T4 · 2 ··· Tn · 2 / bit T1 · n, T2 · n, T3 · n, T4 · n ·· Tn ·
n) are rearranged into n bits in the time axis direction (t).

[0005] These n P / S multiplexing circuits 71 ... 7
time multiplexing memory switch (TSW) 3 for n
1, 32... 3n are provided.
n is a P / S multiplexing circuit 71 to which each is connected.
7n (bits T1, 1, T1.
2, T1,3, T1,4 ... T1, n / bit T2,1,
T2 • 2, T2 • 3, T2 • 4 ... T2 • n / bit Tn
.1, Tn.2, Tn.3, Tn.4... Tn.n) are input.

FIG. 9 is a diagram for explaining time division multiplexing timing in the TSWs 31... 3n. This TSW31
.. 3n, the output signals of the P / S multiplexing circuits 71... 7n are replaced in the time axis direction by output bits (bits T1.2, T1.11, T1.3, T1.4).
... T1 · n / bit T2 · 2, T2 · 1, T2 · 3, T
2.4 ··· T2 · n / bit Tn · 2, Tn · 1, Tn ·
3, Tn.4... Tn.n). This TSW31
.., 3n, for example, using a memory such as a RAM, writing one frame of n bits into this memory, and then reading out the frames in an order according to the exchange condition as shown in FIG. I do.

Further, serial / parallel (S / P) separation circuits 81, 82... 8n are provided corresponding to the TSWs 31... 3n, respectively.
n is input as a time-division multiplexed output signal. Further, parallel / serial (P / S) multiplexing circuits 91, 92... 9n to which n output signals of S / P separation circuits 81. 9n and the S / P separation circuits 81... 8n perform bit replacement processing.

FIG. 10 is a diagram showing timings of output signals of P / S multiplexing circuits 91... 9n. The P / S multiplexing circuits 91... 9n combine the S / P separation circuits 81... 8n to rearrange the n multiplexed signals from the TSWs 31.
2, T2 • 2, T3 • 2, T4 • 2 ... Tn • 2 / bit T1.1 • T2 • 1, T3 • 1, T4.1 • ... Tn • 1 /
Bits T1 · n, T2 · n, T3 · n, T4 · n... Tn
N) are output through output terminals 51, 52... 5n.

The S / P separation circuits 61... 6n, P / S
The switching and setting of the multiplexing circuits 71... 7n, TSW31... 3n, S / P separation circuits 81... 8n and P / S multiplexing circuits 91. .

[0010]

However, in the above-mentioned conventional time-division multiplexing memory switching device, the TSW31.
S / P separation circuits 61... 6n and P / S multiplexing circuits 71... 7n are arranged before 3n, and S / P separation circuits 81... 8n and P / S multiplexing circuits 91. Therefore, the configuration is complicated, and the signal processing scale and the device scale are disadvantageously increased.

The present invention solves the above-mentioned problems in the prior art, and in an optical transmission network or the like, it is possible to simplify the configuration of the preceding and succeeding stages of a time division multiplexing memory switch (TSW). It is an object of the present invention to provide a time-division multiplexing memory switching device capable of reducing the signal processing scale and device scale.

[0012]

According to a first aspect of the present invention, there is provided a time-division multiplexing memory switching device, comprising:
And i-th (i = 1 to n)
And n selection means for sequentially selecting and outputting bits of (integer), and provided for each of the n selection means.
N time-division multiplexing memory switches for exchanging bits in the output signals from the n selecting means in the time axis direction and transmitting the same, and switching data for instructing selection by the n selecting means, and , And a control system for transmitting setting data for performing time division multiplexing by the n time division multiplexing memory switches.

A time-division multiplexing memory switching device according to a second aspect of the present invention provides an n-time-division multiplexing memory switch for exchanging bits in an input signal of n serial data in the time axis direction and transmitting the same, Selecting means for receiving all of the n output signals from the coded memory switches, sequentially selecting and transmitting only the j-th bit of the i-th input signal in the n output signals, sending switching data instructing selection by the n selecting means, and n
And a control system for transmitting setting data for performing time division multiplexing by the time division multiplexing memory switches.

According to a third aspect of the present invention, there is provided a time-division multiplexing memory switching device for mutually exchanging at least one set of n input signals of n bits and outputting the same. A first n selection means for sequentially selecting and outputting the i-th (i = 1 to n) bits, and a first n selection means, respectively. N time-division multiplexing memory switches for switching bits in the output signals from the first n selecting means in the time axis direction and transmitting the same, and all n output signals from the time-division multiplexing memory switches Are input to each other, and j of the i-th input signal in the n output signals is
The second n selecting means for sequentially selecting and transmitting only the n-th bit, and the switching data for instructing the selection by the first and second n selecting means are transmitted. And a control system for transmitting setting data for performing time division multiplexing by the division multiplexing memory switch.

According to a fourth aspect of the present invention, in the time division multiplexing memory switching device, the selection means is a combination of switching data input in parallel to an input side and inputting to a plurality of data selector terminals. By changing
The configuration uses a multiplexer that outputs an n-bit signal on the input side from the output side as serial data.

In the time-division multiplexing memory switching device according to a fifth aspect of the present invention, as the division-multiplexing memory switch, one frame of n bits is written, and then read out in an order according to a condition for replacement to perform multiplexing. The configuration uses a memory.

According to a sixth aspect of the present invention, in the time division multiplexing memory switching device, when j is i = 1, j =
1, and when i> 1, j = 2-i + n.

According to a seventh aspect of the present invention, there is provided a time-division multiplexing memory switching device, wherein the device is used for an optical transmission network.

The time-division multiplexing memory switching device having such a configuration is provided in an optical transmission network or the like, and at least one set of n-bit input signals is exchanged and output. The i-th bit of the n input signals is sequentially selected, and the bits in the selected signal are replaced in the time axis direction. Further, only the j-th bit of the i-th signal in all the replaced n signals is sequentially selected and transmitted.

That is, a simple configuration selecting means such as a multiplexer which outputs an n-bit parallel input signal as serial data is used, and the configuration of the preceding and subsequent stages of the time division multiplexing memory switch (TSW) is simplified. You. For example, there is no need to dispose an S / P separation circuit and a P / S multiplexing circuit at the front and rear stages of the time-division multiplexing memory switch as in the conventional example, and the signal processing scale and the device scale are reduced.

[0021]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, an embodiment of a time division multiplexing memory switching device according to the present invention will be described in detail with reference to the drawings. In the following text and drawings, the same components as those in FIGS. 6 to 10 are denoted by the same reference numerals. FIG. 1 is a block diagram showing a configuration of a time division multiplexing memory switching device according to an embodiment of the present invention.

This time-division multiplexing memory switching device is arranged in an optical transmission network or the like, and has input terminals 11, 12... 1n to which n input signals are supplied, and an input signal based on switching data. .. 2n for selecting the input signal of the input terminal 1i and the bits to be replaced in the output signals from the selection circuits 21. -Division multiplexing memory switch (TSW) 3 which switches and transmits in the time axis direction based on the switching data of
1, 32... 3n.

The time-division multiplexing memory switching device includes a selection circuit 41, 42... 4n for selecting and transmitting the output signal of the TSW 3j for the i-th bit of the n input signals of the n input signals. The output terminals 51, 52... 5n for deriving output signals from the circuits 41.
.. 2n, TSW31... 3n, and a control system 10 for transmitting switching data for performing switching setting of the selection circuits 41.

The selection circuits 21... 2n and the selection circuits 41.
A multiplexer is specifically used as n. This multiplexer (data selector) selects a parallel input signal of several bits and outputs it as a serial data signal.
That is, a bit signal is input to the input side in parallel, and switching data or setting data from the switching control system 10 is supplied to a plurality of data selector terminals. By changing the combination of the switching data input to the plurality of data selector terminals, the bit signal on the input side is output from the output side as serial data.

Next, the operation of this embodiment will be described. All of the n input signals input to the n input terminals 11... 1n are input to the n selection circuits 21. In the selection circuits 21... 2n, based on the switching data from the control system 10, i in n bits of the input signal is selected.
With respect to the bit, the input signal of the input terminal 1i is selected and transmitted to the corresponding TSW31... 3n connected to the output side.

In the TSW31 ... 3n, the selection circuits 21 ... 2
The bits to be exchanged of the output signals from n are exchanged in the time axis direction based on the switching data from the control system 10. All of the output signals from the TSWs 31... 3n are input to the respective selection circuits 41. Selection circuit 4
1 ... 4n, the output of the TSW 3j is selected for the i-th bit in the n bits of the n input signals, and the output terminal 5
1 ... 5n. Here, j is j = when i = 1.
1, and when i> 1, j = 2-i + n.

Next, the main part of this operation will be described in detail.
FIG. 2 is a diagram showing the timing of an input signal to the input terminals 11... 1n. As shown in FIG. 2, n input signals (bits T1 .multidot.
1, T2 · 1, T3 · 1, T4 · 1 ··· Tn · 1 / bit T1,2, T2 · 2, T3 · 2, T4 · 2 ·· Tn · 2 /
Bits T1 · n, T2 · n, T3 · n, T4 · n... Tn
・ N) is input. The phase synchronization is established between the n input signals of n bits. All of the n input signals of n bits input to the input terminals 11... 1n are input to the selection circuits 21.

FIG. 3 is a diagram showing the timing of the output signals of the selection circuits 21... 2n. In the selection circuits 21... 2n, all of the n-bit input signals of n bits from the input terminals 11... 1n are input in parallel, and as shown in FIG. (Bits T1, 1, T2, 2, T3, 3, T4,... T
nn / bit T1,2, T2,3, T3,4, T4
5 ... Tn · 1 / bit T1 · n, T2 · 1, T3 · 2,
T4 · 3... Tn · (n−1)).

The selection circuits 21... 2n use a multiplexer in which an n-bit parallel input signal is input and switching data is input from the control system 10 to a plurality of data selector terminals. By changing the combination of the switching data input to the plurality of data selector terminals, the bit signal on the input side is output from the output side as serial data. The output signals of the selection circuits 21... 2n are input corresponding to the TSWs 31.

FIG. 4 is a diagram for explaining the multiplexing timing in the TSWs 31... 3n. 3n output signals (bits T2.2, T1.1, T3.3, T4.4...) Shown in FIG. T
nn / bit Tn · 1, T2 · 3, T3 · 4, T4 ·
5... Tn · 1 / bit T1 · n, T3 · 2, T2 · 1,
T4 · 3... Tn · (n−1)).

In the TSW 31... 3n, for example, RA
One frame of n bits is written in a memory such as M, and thereafter, for example, as shown in FIG. 4, the data is read out in the order according to the exchange condition by the setting data from the control system 10 to perform time division multiplexing. All the output signals of the TSWs 31... 3n are input to the respective selection circuits 41.

FIG. 5 is a diagram showing the timing of the output signals of the selection circuits 41... 4n. The selection circuits 41... 4n
3n for all the output signals of the TSWs 31... 3n, select the j-th data at the position of the i-th bit Ti and send it to the output terminals 51, 52. As described above, j is j = 1 when i = 1, and j = 2-i + n when i> 1.

As described above, the selection circuits 41... 4n also use a multiplexer in which an n-bit parallel input signal is input and switching data is input from the control system 10 to a plurality of data selector terminals. By changing the combination of the switching data to be input to the plurality of data selector terminals, the bit signal on the input side is output from the output side as serial data.

In this embodiment, TSW31 ... 3
2n are provided as a preceding stage to n.
The selection circuits 41... 4n are provided at the subsequent stage of the SWs 31.
When only the configuration is different from the network configuration, the configuration can be used. The configuration of only the TSWs 31... 3n and the selection circuits 41... 4n can be used when the network configuration is different.

[0035]

As is apparent from the above description, according to the time division multiplexing memory switching device of the present invention, in an optical transmission network or the like, the i-th bit of n input signals is sequentially selected. The bits in the selected signal are exchanged in the time axis direction, and only the j-th bit of the i-th signal in all the n exchanged signals is sequentially selected and transmitted.

In this case, a simple configuration selecting means such as a multiplexer for outputting an n-bit parallel input signal as serial data is used, and the configuration of the preceding and subsequent stages of the time division multiplexing memory switch (TSW) is simplified. Thus, the signal processing scale and the device scale can be reduced.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a time division multiplexing memory switching device according to an embodiment of the present invention.

FIG. 2 is a diagram showing a timing of an input signal in the embodiment.

FIG. 3 is a diagram showing a timing of an output signal of a selection circuit in the embodiment.

FIG. 4 is a diagram for describing multiplexing timing in a time-division multiplexing memory switch in the embodiment.

FIG. 5 is a diagram showing a timing of an output signal of another selection circuit in the embodiment.

FIG. 6 is a block diagram showing a configuration of a conventional time-division multiplexing memory switching device.

FIG. 7 is a diagram showing a timing of an input signal to an input terminal in a conventional example.

FIG. 8 is a diagram showing a timing of an output signal of a P / S multiplexing circuit in a conventional example.

FIG. 9 is a diagram for explaining time division multiplexing timing in a time division multiplexing memory switch in a conventional example.

FIG. 10 is a diagram showing a timing of an output signal at an output terminal in a conventional example.

[Explanation of symbols]

 11 ... 1n input terminal 21 ... 2n selection circuit 31 ... 3n time division multiplexing memory switch (TSW) 41 ... 4n selection circuit 51 ... 5n output terminal 10 control system

Claims (7)

[Claims] 1. An apparatus according to claim 1, wherein said plurality of input signals are provided corresponding to n input signals.
N selecting means for sequentially selecting and outputting the i-th bit (i = 1 to n), and output means for each of the n selecting means. N number of time-division multiplexing memory switches for exchanging bits in a signal in the time axis direction and transmitting, and switching data for instructing selection by the n selecting means, and n time-division multiplexing A time-division multiplexing memory switching device, comprising: a control system for transmitting setting data for performing time-division multiplexing by a memory switch. 2. An n number of time-division multiplexing memory switches for exchanging bits in an input signal of n serial data in a time axis direction and transmitting the same, and an n number of output signals from the time-division multiplexing memory switch. And n selection means for sequentially selecting and transmitting only the j-th bit of the i-th input signal in the n output signals, and instructing the selection by the n selection means. And a control system for transmitting setting data for performing time-division multiplexing with n time-division multiplexing memory switches. apparatus. 3. A time-division multiplexing memory switching device for replacing at least one set of a plurality of n input signals of n bits with each other and outputting the plurality of input signals, the i-th switching device being provided corresponding to the n input signals. (I =
(N of 1 to n) bits are sequentially selected and output, and the first n selection means are provided corresponding to the first n selection means, respectively. N time-division multiplexing memory switches that exchange bits in the output signal from the selecting means in the time axis direction and transmit the same; and all of the n output signals from the time-division multiplexing memory switch are input to each of them. Second n selecting means for sequentially selecting and transmitting only the j-th bit of the i-th input signal in the n output signals, and selecting by the first and second n selecting means And a control system for transmitting switching data indicating the setting and transmitting setting data for performing time division multiplexing with the n time division multiplexing memory switches. Memory switching device. 4. An n-bit signal on the input side by changing a combination of switching data input to a plurality of data selector terminals, wherein an n-bit input signal is input to the input side in parallel, and 4. The time-division multiplexing memory switching device according to claim 1, wherein a multiplexer which outputs the data as serial data from an output side is used. 5. The memory according to claim 1, wherein the time-division multiplexing memory switch uses a memory that writes one frame of n bits, and then reads out and multiplexes in an order according to an exchange condition. 4. The time-division multiplexing memory switching device according to any one of claims 1, 2, and 3. 6. The time division method according to claim 2, wherein in the selection means, j = 1 when j = 1, and j = 2-i + n when i> 1. Multiplexed memory switching device. 7. A time-division multiplexing memory switching device using the device according to claim 1 for an optical transmission network.