JPH01185039A - Condition transferring circuit - Google Patents

Abstract

PURPOSE:To simplify a circuit by stopping the generation of a reading address for updating generated by means of a reading address generating means for updating at the time of transiting the bit condition of synchronizing condition information into the same condition for all registers in a data storing means. CONSTITUTION:Data to be stored into N-number of registers in a data storing means 10a in an independent condition when a control signal 10 from a switching means 100 are reading-sent to a reading address 3 for sending, respectively. On the other hand, when a control signal 110 from the switching means 100 is turned on, the action of a reading address generating means 30a for updating is stopped, a fixation is executed in the condition of, for example, the final stage of N-number of registers, and the data to transit it through a condition transition processing means 20a into the next condition are successively written to respective registers by a writing address 2 for updating. Contents to be transited into the same condition are sent to the reading address 3 for sending when the writing to the register of the final stage is completed. Thus, the independent contents and common contents of N-number of registers can be sent by a more simplified circuit.

Description

[Detailed Description of the Invention] [Summary] A state transition circuit that transitions the bit state of synchronization state information at the time of new reception processing of synchronization detection pattern bits in a plurality of received data can be easily integrated into an integrated circuit. data storage means for storing synchronization detection pattern bits included in received data in N registers together with synchronization state information indicating a synchronization state; state transition processing means for transitioning the state of synchronization state information according to the synchronization detection pattern bit stored in the data storage means and the synchronization detection bit at the time of new reception processing, and transmitting the state to the corresponding register; and storing it in the data storage means. Update read address generation means that generates an address to be read to update the state of the synchronization state information in accordance with the newly received and processed synchronization detection bit, and the bit state of the synchronization state information is the same for all registers in the data storage means. Stops generation of the update read address generated by the update read address generation means when transitioning to the state,
The control device is configured to include switching means for sending both the control signal and the signal for fixation.

[Industrial Application Field] The present invention relates to a state transition circuit that transitions the bit state of synchronization state information at the time when synchronization detection pattern bits in a plurality of received data are newly received and processed.

For example, in time division multiplexing, the signals of each channel to be multiplexed (for example, data from multiple subscribers, etc.) are sequentially and synchronously arranged, and a synchronization detection pulse having a specific pattern is sent every period. Additional insertion may be required to synchronize.

On the receiving side of such data, the pulse train for each frame is checked, a synchronization detection pulse is detected, the time slot position of each channel is identified, and synchronization processing is performed.

In particular, in the integrated service digital network (hereinafter referred to as 15DN) that has recently been developed and is being put into practical use, in the case of subscriber data mode in which subscriber data is directly processed, synchronization is determined by the synchronization detection pulse pattern state of each channel within each frame. For example, when processing data with a subscriber in a remote location via a remote device (subscriber control mode), and when transmitting synchronization detection pulses of all channels for each frame in the same state. There is.

In order to integrate a circuit that simultaneously performs such processing, it is required to simplify the circuit and reduce the number of gates used.

[Conventional technology]

FIG. 4 is a block diagram illustrating a conventional example, FIG. 5 is a diagram illustrating a data structure, and FIG. 6 is a diagram illustrating a synchronous transition state.

The block diagram shown in FIG. 4 is a block diagram of a state transition circuit that performs frame synchronization detection bit reception processing every multiple frames (for example, every three frames) for frame synchronization processing of data to be transmitted. The configuration is as follows: A register section 1 consisting of N registers Reg, 1 to Reg, n that store m bits consisting of synchronization detection bits for multiple frames and synchronization status bits for each multiple frames.
0, the synchronous state bit is changed according to the data bit read from each register Reg, 1 to Reg, n, and the data bit to be newly received and processed, and the corresponding register Reg, 1
A state transition driver circuit 20 that sends data to "Reg, n," an update read counter circuit 30 that generates an address "■" for reading data bits stored in each register Reg, 1 to Reg, n, and a state transition An update write counter circuit 40 that generates an address (■) for writing the data bit whose state has changed in the driver circuit 20 to each register Reg, 1 "Reg, n," and A sending read counter circuit 50 that generates an address (2) for reading out the stored data bits to, for example, a data reception processing circuit (not shown), an update read address (2), and an update write address (2).

A selector circuit 60 that selects one of the sending read addresses ■ and sends it to each register Reg, 1 to Reg, n.
, a common counter circuit 70 generated by cyclically transitioning the synchronization state bit, and data bits sent from each register Reg, 1 to Reg, n based on a switching control signal ■ accompanying a switching instruction from the switching control unit 90. a selector circuit 80 that switches to select the synchronization state bit generated from the common counter circuit 70; and a switching control unit that generates control signals (1) and (2) to select which of the plurality of input terminals of the selector circuit 60 and the selector circuit 80. 90.

The switching modes of the switching control section 90 described above are, for example, a subscriber data mode and a subscriber control service mode in 15DN.

The data handled in this example is the case where the voice and data of 60 subscribers are processed per frame as shown in Figure 5.
The data structure for each subscriber (hereinafter referred to as CH) is as follows.
As shown in Figure (3).

In other words, 8-pin information (data) and 8-bit status/
Consists of control information. Note that a synchronization detection bit (F bit) for synchronizing data is assigned to one bit (usually the last bit) in the status S/control information.

The data stored in each register Reg, 1 to Reg, n includes synchronization detection bits for a plurality of frames and status bits that indicate the synchronization state of data using the synchronization detection bits.

Therefore, each register Reg, 1 to Reg, n in this example is N
It is possible to store each synchronization state independently (having a capacity of m bits). Note that the example shown in FIG. 5 is a case of 3-frame multiplayer with N-60 and m=4.

As mentioned above, the contents of the data stored in each register Reg, 1 to Reg, n indicate an independent state, and the state of the data stored in each of these registers Reg, 1 to Reg, n is updated. If so, each register R
Read the data stored in eg, 1 to Reg, n,
Transition to the synchronous state when newly received new data is added and write to the corresponding register Reg,l''Reg,n.

That is, the synchronization state is indicated by the status bits shown in FIG. 6, for example. The example shown in Figure 6 is the front two stages.

This is an example in which the rear two stages are protected, and at the start, all registers Reg, 1 to Reg, n are reset to "O".

The state when reset to “0” is indicated by “00”. In this state, set the synchronization detection bit to, for example, 110'' (this is
When detecting a pattern indicating the same x, 1161 standing state in the case of 3 frame multi, the state s3 transfer driver circuit 20 changes the state to "01" and the corresponding register Reg, 1 =
Store in Reg, n.

Next, when the registers Reg, 1 to Reg, n are successively read by the update read counter circuit 30, the synchronization detection bit for two frames is "11" and the synchronization detection bit for the third frame is "50". If so, the state transition driver circuit 20 transitions the state from "01" to "11" and stores it in the corresponding registers Reg,1 to Reg,n.

Then, if the pattern of the synchronization detection bits at the next time is “110”, the state transition driver circuit 2
0 repeats "11".

The direction indicated by the thick line is the same pJ11i! The direction shown by the thin line indicates the out-of-synchronization direction state. In other words, when the state of "11" collapses, it transitions to the state of "10", and then the state changes to "1" again.
If the state is "1", the state transitions from "10" to "ll".

Also, the output of the update read counter circuit 30 for reading the contents of registers Reg, 1 to Reg, n for update;
Output (1) of the update write counter circuit 40 for writing state transitions, and a readout counter circuit for sending out the contents of registers Reg, 1 to Reg, n to a data reception processing circuit (not shown) The output ■ of 50 is
The selector circuit 60 selects the register Re according to the processing at that time in response to the switching control signal (■) from the switching control section 90.
It is sent as an address for g, 1 to Reg, n.

The above mode corresponds to the subscriber data mode in 15DN, and when the mode is next switched to the subscriber control service mode, the control method requires that all the CHs in each frame be transmitted in the same state.

To do this, the selector circuit 80 is switched by the switching control signal (2) from the switching control section 90, and the common counter circuit 70 is switched.
Select and output the synchronization status information ■ output from .

That is, the common counter circuit 70 changes from 00" to "00" shown in FIG.
01"→"11"→"10"→"00" are repeatedly output for each frame. In addition, "00" as shown in FIG.
Synchronous state information ■ of “01” indicates an asynchronous state, and “11”
", "10" synchronization state information ■ indicates a synchronization state.

[Problem that the invention seeks to solve]

In the state transition circuit described above, each register ReH, 1 to fleg
.

In order for n to transition to a common state, a common counter circuit 70 and each register Reg, 1 to
Status read from Reg, n and common counter circuit 7
It is necessary to provide an extra selector circuit 80 for selecting the output (2) from 0, and if these are integrated into an integrated circuit, the number of IC cells will increase accordingly.

SUMMARY OF THE INVENTION An object of the present invention is to provide a simplified state transition circuit that can be easily integrated into an integrated circuit.

[Means for solving problems]

FIG. 1 shows a block diagram illustrating the invention in detail.

In the block diagram of the principle of the present invention shown in FIG. 1, 10a is data storage means for storing synchronization detection pattern bits included in received data in N registers, respectively, together with synchronization state information indicating the synchronization state; 30a is a state transition processing means that changes the state of the synchronization state information according to the synchronization detection pattern bit stored in the data storage means 10a and the synchronization detection bit when a new reception process is performed and sends it to the register; 30a is a data storage means; Update read address generating means generates an address to be read in order to update the state of the synchronization state information stored in the means 10a according to the newly received and processed synchronization detection bit, and 100 indicates the bit state of the synchronization state information. This problem is solved by providing means for generating the update read address generation means 30a when all the registers in the data storage means 10a are brought into the same state.

[For production]

When the control signal [phase] from the burial mound switching means 100 is off, the data stored in the N registers in the data storage means 10a in an independent state is read out and sent out using the sending read address (2).

On the other hand, when the control signal 0 from the switching means 100 is turned on, the operation of the update read address generation means 30a is stopped and the state of the N registers is fixed at, for example, the final stage.
The data that has been transitioned to the next state via the state transition processing means 20a is sequentially written into each register using the update write address ■.

Then, at the end of writing to the register at the final stage, it is configured to send the contents that have been changed to the same state to the sending read address ■, and the independent contents of the N registers and the contents common to the N registers are transmitted. It becomes possible to send out data using a more simplified circuit.

〔Example〕

The gist of the present invention will be specifically explained below with reference to embodiments shown in FIGS. 2 and 3.

FIG. 2 is a block diagram illustrating the present invention in detail, and FIG. 3 is a diagram illustrating the structure of a register in an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The block diagram of this embodiment shown in FIG. 2 has the same configuration as that explained in FIG. 4 as the data storage means 10a explained in FIG. 1, and each register Reg, 1 to Rc.
4. When transitioning from the n state to the common state, the final stage Re
A register unit IO1 configured to apply only the states g and n to the state transition driver circuit 20. As the state transition processing means 20a, a state transition driver circuit 20 similar to that explained in FIG. 4, and an update read address generation As the means 30a, the update read counter circuit 3 is configured to stop and fix the output when the input control signal 0 turns on, as explained in FIG.
This is an example configured with a switching control signal generating section 100a that generates a control signal [phase] for 0b and a switching control signal ■ for the selector circuit 60.

In addition to the above functional blocks, this embodiment also includes the update write counter times FI! explained in FIG. Ir40. Sending read counter circuit 50. A selector circuit 60 is provided.

Next, in the case of this embodiment as well, there are N synchronization detection bit patterns in independent states (for example, F bits for synchronization detection included in each data transmitted from N subscribers), and these The F bit is stored in each register Reg, 1 to Reg, n constituting the register section 10, as shown in FIG.

That is, the example shown in Figure 3 is a case where synchronization is detected using 3 frame multi, the first two bits store status bits as shown in Figure 6, and the latter two bits store the synchronization for two frames. Store detection bits.

In the case of this embodiment as well, the number of subscribers is N=60. This is a case where the capacity of each register FJm=4 bits. Further, it is assumed that the case where the synchronization detection bit pattern is "110" means a synchronous state, and the other cases mean an asynchronous state.

Next, in the same way as the process explained in FIG.
, 1 =Reg, When writing update data (synchronization detection bit and status bit) to n, the process is as follows.

That is, the synchronization detection bits for two frames (for example, "1 bit") already stored in the corresponding register Reg, i in each register Reg, 1 to Reg, n, are set to the previous synchronization state. It is read out using the address (2) generated from the update read counter circuit 30b together with the status bit indicating information.

The state transition driver circuit 2
For example, if the synchronization detection bit of the third channel input to 0 is a “0” bit, the status bit is set to “11”.
Address output from update write counter circuit 40 ■
Based on the register Reg.

Write to i.

The above processing is performed sequentially for each register Reg, 1 to Reg, n corresponding to each CHI to CH60, and the status bit and synchronization detection bit at this time are transferred to, for example, a data reception processing circuit (not shown). When sending, each register R is set at the address ■ of the sending read counter circuit 50.
The contents of eg, 1 to Reg, n are read and sent.

Incidentally, the selection of each of the above-mentioned addresses (2) to (2) is performed by controlling the selector circuit 60 by the switching control signal (2) generated from the switching control signal generating section 100a, as explained in FIG.

Next, when the states of each register Reg, 1 to Reg, n are changed to a common state, the final stage (for example, 60
The operation of the update read counter circuit 30b is fixed at the position of the address {circle around (2)} generated from the update read counter circuit 30b.

Then, the data stored in the register Reg,n is transitioned by the state transition driver circuit 20, and the state bit is changed to each register Reg,1 =Reg, (n −1 )
Write in the same state sequentially to

Note that the control signal [phase] that fixes the operation of the update read counter circuit 30b is periodically sent out from the switching control signal generating section 100a in synchronization with the timing of Reg, n.

As described above, the same status bits written to each register Reg, 1 to Reg, n are sent to, for example, a data reception processing circuit (not shown) at address (2) of the sending read counter circuit 50.

By processing in this manner, the common counter circuit 70 and selector circuit 80 explained in FIG. 4 can be deleted.

〔Effect of the invention〕

According to the present invention as described above, a more simplified state transition circuit can be realized.

[Brief explanation of the drawing]

FIG. 1 is a block diagram explaining the present invention in detail, FIG. 2 is a block diagram explaining the present invention in detail, FIG. 3 is a diagram explaining the configuration of a register in an embodiment of the present invention, and FIG. FIG. 5 is a block diagram illustrating a conventional example, FIG. 5 is a diagram illustrating a data configuration, and FIG. 6 is a diagram illustrating a synchronous transition state. In the figure, 10 is a register section, loa is a data storage means, 20
20a is a state transition driver circuit, 20a is a state transition processing means, 30.30b is an update read counter circuit, 30a is an update read address generation means, 40 is an update write counter circuit, 50 is a sending read counter circuit, 60. 80 is a selector circuit, 70 is a common counter circuit,
90 is a switching control unit, 100 is a switching means, 100a
are the switching control signal generation section, and are respectively shown. FIG. 1 is a diagram explaining the structure of a register in an embodiment of the present invention FIG. 3 is a block diagram explaining in detail the present invention FIG. 2 FIG. 5

Claims (1)

[Scope of Claims] Data storage means (10a) for storing synchronization detection pattern bits included in received data in N registers, respectively, together with synchronization state information indicating a synchronization state; and storing in the data storage means (10a). a state transition processing means (20a) that changes the state of the synchronization state information according to the synchronization detection pattern bit to be processed and the synchronization detection bit at the time of new reception processing and sends it to the register; and the data storage means (10a). ); update read address generation means (30a) for generating an address ([1]) to be read to update the state of the synchronization state information stored in the synchronization state information stored in the synchronization state information according to a newly received and processed synchronization detection bit; The bit state of the state information is stored in the data storage means (
10a) A control signal ([10]) for stopping and fixing the generation of the update read address ([1]) generated by the update read address generating means (30a) when all the registers in ) for sending out the switching means (
100), when the update read address ([1]) is generated from the update read address generation means (30a), the synchronization detection bit state stored in the data storage means (10a) is respectively set. The update read address ([[
1]) is stopped and fixed, the bit state of the synchronization state information stored in the data storage means (10a) will be the update read address (
[1]) A state transition circuit that transitions to a bit state read out and written to.