JPH11163337A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide the forming method of a MOS transistor by which high reliability can be ensured in a simple method but which has LDD structure. SOLUTION: When the source-drain diffusion layers of an insulated gate field-effect transistor are formed into an LDD structure, sidewalls 8 constituted of non-doped polysilicon are formed onto the sidewall sections of a gate electrode 5 via a protective insulating film 6, and impurities are introduced at the same time to the forming regions of the source-drain diffused layers and the sidewalls. Lightly doped regions (P-diffused layers 12) and heavily doped regions (P<+> -diffused layer 13) having LDD structure are formed through the same heat treatment at the same time.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a shallow LDD (Lightly Dopant).
The present invention relates to a method for manufacturing an insulated gate field effect transistor (hereinafter, referred to as a MOS transistor) having an ed Drain structure.

[0002]

2. Description of the Related Art Fine structure and high density of semiconductor devices such as MOS transistors are still being vigorously promoted. For miniaturization, 0.15 μm
A semiconductor element formed with a dimension is used, and a semiconductor device such as a memory device or a logic device based on this dimension has been put to practical use.

[0003] Such miniaturization is the most effective method for achieving high performance or multifunctionality due to high integration, high speed, etc. of a semiconductor device, and is indispensable for the manufacture of semiconductor devices in the future. With the miniaturization of such a semiconductor element, it has become necessary to form the impurity diffusion layers in the source and drain regions extremely shallow and with high reliability.

Various methods have been studied for forming the source / drain regions having the LDD structure. Among them, a method has been proposed as disclosed in, for example, Japanese Patent Application Laid-Open No. 2-1941. Hereinafter, this method will be described as a conventional example with reference to FIG.

FIG. 5 is a sectional view of a MOS transistor having an LDD structure in the order of manufacturing steps. As shown in FIG. 5A, a field oxide film 102 is selectively formed on a silicon substrate 101 having a P-type conductivity. Next, a gate oxide film 103 is formed on the active region. Then, a gate electrode 104 made of polycrystalline silicon to which a phosphorus impurity is added is formed. Next, the gate electrode 10 made of polycrystalline silicon is used.
4 is thermally oxidized to form a thermal oxide film 105.

Next, as shown in FIG. 5B, a polycrystalline silicon film containing a phosphorus impurity is deposited on the entire surface by chemical vapor deposition (CVD), and anisotropic dry etching is performed. By this anisotropic dry etching of the entire surface, that is, etch back, a sidewall 106 made of polycrystalline silicon containing a phosphorus impurity is formed on the side wall of the gate electrode 104 via a thermal oxide film 105.

Next, arsenic ions 107 are implanted over the entire surface to form a high concentration N-type diffusion layer. Then, heat treatment is performed to activate the implanted arsenic impurities. By this heat treatment, as shown in FIG. 5C, the low concentration region 109 is formed at the same time as the high concentration region 108 is formed. Here, the low concentration region 109 is a side wall 1 made of polycrystalline silicon containing a phosphorus impurity.
06 is formed by thermally diffusing phosphorus impurities in the silicon substrate.

Thus, the P-type silicon substrate 101
A MOS having a field oxide film 102 selectively formed thereon, a gate oxide film 103, a gate electrode 104, and a diffusion layer having an LDD structure having a high concentration region 108 and a low concentration region 109 as a source / drain region. A transistor will be formed.

[0009]

In the method of manufacturing a MOS transistor having the above LDD structure, two types of channel type MOS transistors, ie, N-channel MOS transistors, are used.
Transistor (hereinafter referred to as NMOS) and P-channel M
M of both OS transistors (hereinafter referred to as PMOS)
When a semiconductor device including an OS transistor (hereinafter, referred to as CMOS) is manufactured, there is a problem that the manufacturing process is complicated and the manufacturing cost is significantly increased.

For example, when the above-mentioned conventional technique is applied only to an NMOS, a polycrystalline silicon film containing a phosphorus impurity is deposited on the entire surface in order to prevent the formation of the sidewall 106 on the side wall of the gate electrode of the PMOS. Thereafter, in a photolithography process, only the NMOS must be covered with a photoresist, and the above-mentioned phosphorus-containing polycrystalline silicon film on the PMOS must be removed by etching. Thus, a photolithography step and an etching step are added. In this case, the phosphorus impurities in the sidewalls 106 are hardly dissolved in the thermal oxide film 105 and are hardly thermally diffused into the surface of the silicon substrate 101. For this reason, the above heat treatment requires a high temperature.

In addition, the above-mentioned conventional technology is applied to NMOS and PM.
When applied to both OSs, it is necessary to further deposit a polycrystalline silicon film containing boron impurities.
A photolithography step and an etching step are further added in order to etch away the polycrystalline silicon film containing the boron impurity. Thus, the manufacturing cost of the semiconductor device increases.

An object of the present invention is to provide a method of manufacturing a semiconductor device which solves all of the above-mentioned problems, is simple, and can ensure high reliability.

[0013]

For this purpose, a method of manufacturing a semiconductor device according to the present invention comprises forming a gate electrode of an insulated gate field effect transistor on a semiconductor substrate of one conductivity type via a gate insulating film; Forming a protective insulating film on the upper and side wall portions of the electrode and the semiconductor substrate; forming non-doped polysilicon on the side wall portion of the gate electrode via the protective insulating film; A step of implanting impurity ions of the opposite conductivity type into the source / drain diffusion layer forming region of the effect transistor and the polycrystalline silicon, and the step of implanting the impurity implanted into the polycrystalline silicon by heat treatment to the surface of the semiconductor substrate through the protective insulating film. Diffusing and activating the impurities in the source / drain diffusion layer formation region.

Alternatively, the method of manufacturing a semiconductor device according to the present invention comprises the steps of: forming a well layer of the opposite conductivity type on a semiconductor substrate of one conductivity type; and interposing a gate insulating film formed on the surface of the semiconductor substrate and the well layer. Forming a first gate electrode and a second gate electrode of two types of channel-type insulated gate field effect transistors, respectively, upper and side wall portions of the first gate electrode and the second gate electrode, and the semiconductor substrate Forming a protective insulating film thereon; forming non-doped polycrystalline silicon on sidewalls of the first gate electrode and the second gate electrode via the protective insulating film; A source / drain diffusion layer forming region of the insulated gate field effect transistor and polycrystalline silicon on the side wall of the first gate electrode; Implanting the same conductivity type impurity ions into the polycrystalline silicon on the source / drain diffusion layer formation region of the insulated gate field effect transistor and on the side wall of the second gate electrode on the well layer. Diffusing the impurities implanted into the polycrystalline silicon by heat treatment through the protective insulating film to the surface of the semiconductor substrate or the surface of the well layer, and activating the impurities in the source / drain diffusion layer formation region. .

In such a method of manufacturing a semiconductor device, the protective insulating film is formed of a silicon oxide film containing excess silicon atoms. The implantation of the impurity ions is performed by oblique ion implantation. Here, BF ₂ or arsenic ion is used as the impurity ion.

As described above, according to the present invention, the source / drain diffusion region of the insulated gate field effect transistor can be formed into the LDD structure by a simple method, and the manufacturing cost of the semiconductor device can be reduced.

[0017]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 and FIG.
FIG. 7 is a cross-sectional view in the order of the manufacturing steps when the present invention is applied to the manufacture of a CMOS semiconductor device.

As shown in FIG. 1A, an N well 2 is formed in a predetermined region on the surface of a P-type silicon substrate 1. Then, a field oxide film 3 is formed in the inactive region by a known method. Further, a gate oxide film 4 is formed in the active region by a thermal oxidation method.

Next, a gate electrode 5 is formed on the gate oxide film 4 using polycrystalline silicon having a thickness of about 200 nm and doped with phosphorus impurities. Then, a protective insulating film 6 is formed on the entire surface by the CVD method. Here, the protective insulating film 6 is formed of a silicon dioxide film having a thickness of about 10 nm.

Next, the PMOS formation region is covered with a photoresist, and an N diffusion layer 7 is formed by ions in a region to be the source / drain region of the NMOS.

Next, a non-doped polysilicon film having a thickness of about 100 nm is formed by the CVD method, and thereafter, an etch back is performed. Then, as shown in FIG. 1B, a side wall 8 made of non-doped polysilicon is formed on the side wall of the gate electrode 5 with the protective insulating film 6 interposed therebetween.

Next, as shown in FIG.
A resist mask 9 is formed in the formation region, and BF ₂ ions 10 are implanted into the PMOS formation region at an implantation energy of 50 keV and at a dose of 3 × 10 ¹⁵ / cm ² . Here, the implantation of the BF ₂ ions 10 is preferably performed by rotational oblique ion implantation. By this oblique ion implantation, the BF ₂ ions 10 are effectively introduced into the side walls 8. In this manner, the P ⁺ implanted layer 11 is formed on the surface of the N well 2, and a boron impurity is introduced into the side wall 8.
A sidewall 8a containing boron impurities is formed.

Next, after removing the resist mask 9, 8
Heat treatment is performed at 00 ° C. for about 30 minutes. By this heat treatment, as shown in FIG. 1D, a P diffusion layer 12 is easily formed on the surface of the N well 2 immediately below the sidewall 8a. Here, there is a protective insulating film 6 made of a silicon dioxide film between the N well 2 and the side wall 8a. A large amount of boron impurities melt into this protective insulating film 6. For this reason, boron impurities easily diffuse into the surface of the silicon substrate 1 even at a low-temperature heat treatment, and the P diffusion layer 12 is formed. At the same time, the boron impurity in the P ⁺ implantation layer 11 is activated, and the P ⁺ diffusion layer 13 is formed. The presence of F (fluorine) atoms in the protective insulating film 6 promotes the formation of the P diffusion layer 12.

Next, the PMOS formation region is covered with a resist mask 14, and 50 nm of arsenic ions are implanted into the NMOS formation region.
Ions are implanted at a dose of 2 × 10 ¹⁵ / cm ² with V implantation energy. Then, a heat treatment of 850 ° C. is performed,
The arsenic impurity is activated, and as shown in FIG.
An N ⁺ diffusion layer 15 is formed.

Next, the resist mask 14 is removed by a known method, and the sidewall 8 and the sidewall 8a are removed. After that, according to the normal manufacturing process, FIG.
As shown in (b), an interlayer insulating film 16 is formed, a contact hole is opened, and an aluminum electrode 17 connected to the P ⁺ diffusion layer 13 or the N ⁺ diffusion layer 15 is formed. Thus, the CM having the source / drain region having the LDD structure
An OS is formed.

In this manner, the photolithography step, the impurity introduction step, and the polycrystalline silicon deposition step can be omitted once each from the conventional manufacturing steps. As described above, according to the method of the present invention, a highly reliable CMOS can be easily formed by a simple manufacturing process.

Next, a second embodiment of the present invention will be described with reference to FIGS. 3 and 4 are cross-sectional views in the order of manufacturing steps when the present invention is applied to the manufacture of a CMOS semiconductor device. Here, the same components as those described in the first embodiment are denoted by the same reference numerals.

As shown in FIG. 3A, an N well 2 is formed in a predetermined region on the surface of a P-type silicon substrate 1. Then, a field oxide film 3 is formed, and a gate oxide film 4 is formed in the active region by a thermal oxidation method. Next, a gate electrode 5 is formed on the gate oxide film 4 using polycrystalline silicon. Then, a protective insulating film 6a is formed on the entire surface by the CVD method. Here, the protective insulating film 6a is formed of a silicon oxide film containing excess silicon atoms. The silicon oxide film containing excessive silicon atoms contains 5 to 10 at% more silicon atoms than a silicon oxide film formed of stoichiometric silicon dioxide. This effect will be described later. The silicon oxide film containing excess silicon atoms has a thickness of 10 nm.
It is about.

Next, in the same manner as in the first embodiment, a non-doped polysilicon film is formed to a thickness of about 100 nm, and thereafter, etch back is performed. Then, as shown in FIG. 3B, a side wall 8 made of non-doped polysilicon is formed on the side wall of the gate electrode 5 via the protective insulating film 6a.

Next, as shown in FIG.
A resist mask 9 is formed in the formation region, and BF ₂ ions 10 are ion-implanted in the PMOS formation region in the same manner as described in the first embodiment. In this way, the P ⁺ implantation layer 11 is formed on the surface of the N well 2, and a boron impurity is introduced into the sidewall 8 to form the sidewall 8 a containing the boron impurity.

Similarly, as shown in FIG.
A resist mask 14 is formed in the S formation region, and arsenic ions 18 are implanted into the NMOS formation region at an implantation energy of 50 keV and at a dose of 2 × 10 ¹⁵ / cm ² .
Here, the implantation of the arsenic ions 18 is preferably performed by rotational oblique ion implantation. This oblique ion implantation allows arsenic ions 1
8 is effectively introduced into the sidewall 8. In this way, an N ⁺ implanted layer 19 is formed on the surface of the silicon substrate 1 and an arsenic impurity is introduced into the sidewalls 8.
A sidewall 8b containing an arsenic impurity is formed.

Next, after removing the resist mask 14,
Heat treatment is performed at 850 ° C. for about 30 minutes. In this heat treatment,
As shown in FIG. 4A, the N just below the sidewall 8a
P diffusion layer 12 is easily formed on the surface of well 2. Here, between the N well 2 and the sidewall 8a, there is a protective insulating film 6 made of a silicon oxide film containing excess silicon. This protective insulating film, unlike the silicon dioxide film, allows boron impurities to pass well. For this reason, the P diffusion layer 12 is easily formed even when the heat treatment is performed at a low temperature.
At the same time, the boron impurity in the P ⁺ implantation layer 11 is activated, and the P ⁺ diffusion layer 13 is formed.

At the same time, as shown in FIG. 4A, the N diffusion layer 7 is formed on the surface of the silicon substrate 1 immediately below the side walls 8b by this heat treatment. Here, between the silicon substrate 1 and the side wall 8b, there is a protective insulating film 6 composed of a silicon oxide film containing excess silicon. This protective insulating film, unlike a silicon dioxide film, allows arsenic impurities to pass well. For this reason, the N diffusion layer 7 is easily formed even when the heat treatment is performed at a low temperature. And N ⁺ injection layer 1
The arsenic impurity in 9 is activated, and an N ⁺ diffusion layer 15 is formed.

Next, the side walls 8a and 8b
Is removed. Then, a silicon oxide film is deposited on the entire surface by the CVD method, and is etched back. Thus, FIG.
As shown in (b), a side wall insulating film 20 is formed on the side wall of the gate electrode 5 with the protective insulating film 6a interposed therebetween.

Next, the oxide film on the gate electrode 5, the P ⁺ diffusion layer 13 and the N ⁺ diffusion layer 15 is removed, and titanium is deposited by sputtering. Then, heat treatment is performed to form a silicide layer 21 on gate electrode 5, P ⁺ diffusion layer 13 and N ⁺ diffusion layer 15.

Next, as shown in FIG. 4C, an interlayer insulating film 16 is formed, a contact hole is opened, and the contact hole is connected to the silicide layer 21 on the P ⁺ diffusion layer 13 or the N ⁺ diffusion layer 15. An aluminum electrode 17 is formed. Thus, L
A CMOS having source / drain regions having a DD structure is formed.

In the second embodiment, the source and drain regions of the NMOS and the PMOS are simultaneously formed in the LDD structure. For this reason, the manufacturing process is further simplified than in the first embodiment, and a highly reliable CMOS can be easily formed.

Although the silicide layer is made of titanium silicide, it should be noted that a silicide layer of a refractory metal such as cobalt or tungsten can be similarly formed instead of titanium silicide.

In the embodiment of the present invention, the case where the protective insulating film is formed of a silicon dioxide film or a silicon oxide film containing excess silicon atoms has been described. It should be noted that a similar insulating film has the same effect.

[0040]

As described above, according to the present invention, when forming a source / drain diffusion layer of a MOS transistor in a shallow LDD structure, a side wall made of non-doped polysilicon is formed on a side wall of a gate electrode. Impurities are simultaneously introduced into the source / drain diffusion layer formation region and the sidewalls. Then, by the same heat treatment, a low concentration region and a high concentration region of the LDD structure are simultaneously formed.

For this reason, the number of manufacturing steps can be greatly reduced. The LDD structure formed according to the present invention is
The junction becomes shallower than that formed by the ion implantation of the prior art, and enables miniaturization of the MOS transistor with high reliability and controllability.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating a C for explaining a first embodiment of the present invention;
It is sectional drawing of the manufacturing process order of a MOS transistor.

FIG. 2 is a diagram for explaining C according to the first embodiment of the present invention;
It is sectional drawing of the manufacturing process order of a MOS transistor.

FIG. 3 is a diagram illustrating a C for explaining a second embodiment of the present invention;
It is sectional drawing of the manufacturing process order of a MOS transistor.

FIG. 4 is a diagram illustrating a C for explaining a second embodiment of the present invention;
It is sectional drawing of the manufacturing process order of a MOS transistor.

FIG. 5 is a sectional view illustrating a conventional technique in the order of manufacturing steps of a MOS transistor.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1, 101 Silicon substrate 2 N well 3, 102 Field oxide film 4, 103 Gate oxide film 5, 104 Gate electrode 6, 6a Protective insulating film 7 N injection layer 8, 8a, 8b, 106 Side wall 9, 14 Resist mask 10 BF ₂ ions 11 P ⁺ implanted layer 12 P diffused layer 13 P ⁺ diffused layer 15 N ⁺ diffused layer 16 interlayer insulating film 17 aluminum electrode 18, 107 arsenic ion 19 N ⁺ implanted layer 20 sidewall insulating film 21 silicide layer 105 thermal oxide film 108 High density area 109 Low density area

Claims (5)

[Claims] 1. A gate electrode of an insulated gate field effect transistor is formed on a semiconductor substrate of one conductivity type via a gate insulating film, and a protective insulating film is formed on the upper and side walls of the gate electrode and on the semiconductor substrate. Performing a step of forming non-doped polycrystalline silicon on the side wall portion of the gate electrode via the protective insulating film; and a step of forming a source / drain diffusion layer forming region of the insulated gate field effect transistor and the polycrystalline silicon in reverse. Implanting conductivity type impurity ions, and diffusing the impurities implanted into the polycrystalline silicon by heat treatment through the protective insulating film to the surface of the semiconductor substrate and activating the impurities in the source / drain diffusion layer formation region A method of manufacturing a semiconductor device. 2. A two-channel insulated gate field effect transistor having a well layer of the opposite conductivity type formed on a semiconductor substrate of one conductivity type and a gate insulating film formed on the surface of the semiconductor substrate and the well layer. Forming a first gate electrode and a second gate electrode respectively, and forming a protective insulating film on the upper and side walls of the first gate electrode and the second gate electrode and on the semiconductor substrate. ,
Forming non-doped polycrystalline silicon on sidewalls of the first gate electrode and the second gate electrode via the protective insulating film; and forming a source / drain of an insulated gate field effect transistor on the semiconductor substrate. Implanting impurity ions of the opposite conductivity type into the diffusion layer formation region and the polycrystalline silicon on the side wall of the first gate electrode; and forming the source / drain diffusion layer formation region of the insulated gate field effect transistor on the well layer and Implanting impurity ions of the same conductivity type into the polycrystalline silicon on the side walls of the second gate electrode; and implanting the impurities implanted into the polycrystalline silicon by heat treatment through the protective insulating film into the surface of the semiconductor substrate or the well layer. While diffusing to the surface,
Activating the impurities in the source / drain diffusion layer formation region. 3. The method of manufacturing a semiconductor device according to claim 1, wherein said protective insulating film is made of a silicon oxide film containing excess silicon atoms. 4. The method according to claim 1, wherein the implantation of the impurity ions is performed by oblique ion implantation. 5. The method for manufacturing a semiconductor device according to claim 1, wherein said impurity ions are BF ₂ or arsenic ions.