JPH11163002A - Semiconductor element mounting board - Google Patents
Semiconductor element mounting boardInfo
- Publication number
- JPH11163002A JPH11163002A JP32844697A JP32844697A JPH11163002A JP H11163002 A JPH11163002 A JP H11163002A JP 32844697 A JP32844697 A JP 32844697A JP 32844697 A JP32844697 A JP 32844697A JP H11163002 A JPH11163002 A JP H11163002A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- thermal expansion
- resin
- young
- package
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Wire Bonding (AREA)
- Die Bonding (AREA)
- Compositions Of Macromolecular Compounds (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体素子を実装
した配線基板に関し、 特に大型形状の表面実装型の高熱
膨張特性を有する絶縁基板を具備する配線基板上に、半
導体素子を熱硬化性樹脂を用いて、固定および封止する
にあたり、熱履歴特性、使用耐久性、信頼性の改良に関
するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board on which a semiconductor element is mounted, and more particularly, to a method for mounting a semiconductor element on a wiring board having a large-sized surface mounting type insulating substrate having high thermal expansion characteristics. The present invention relates to improvement of thermal hysteresis characteristics, durability in use, and reliability in fixing and sealing by using.
【０００２】[0002]
【従来技術】従来、配線基板は、絶縁基板の表面あるい
は内部にメタライズ配線層が配設された構造からなる。
また、この配線基板の代表的な例として、半導体素子、
特にＬＳＩ（大規模集積回路素子）等の半導体集積回路
素子を載置するための半導体素子収納用パッケージは、
一般にアルミナセラミックスからなる絶縁基板の表面お
よび内部に、タングステン、モリブデン等の高融点金属
粉末から成る複数個のメタライズ配線層が配設され、上
部に載置される半導体素子とワイヤーを介して電気的に
接続される。2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is disposed on the surface or inside of an insulating substrate.
Also, typical examples of the wiring board include a semiconductor element,
In particular, a semiconductor element storage package for mounting a semiconductor integrated circuit element such as an LSI (large-scale integrated circuit element)
In general, a plurality of metallized wiring layers made of a refractory metal powder such as tungsten and molybdenum are provided on the surface and inside of an insulating substrate made of alumina ceramics, and electrically connected to a semiconductor element mounted thereon through wires. Connected to.
【０００３】一般に、半導体素子の集積度が高まるほ
ど、半導体素子に形成される電極数も増大するが、これ
に伴いこれを収納する半導体収納用パッケージにおける
端子数も増大することになる。さらに年々、パッケージ
小型化への要求が高まっており、最近では、チップ面積
がパッケージの面積の５０％以上のチップサイズパッケ
ージ（ＣＳＰ）が主流となりつつある。Generally, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases. As a result, the number of terminals in a semiconductor housing package for housing the same increases. Furthermore, the demand for a smaller package is increasing year by year, and recently, a chip size package (CSP) having a chip area of 50% or more of the package area is becoming mainstream.
【０００４】また、パッケージにおける半導体素子の実
装は、半導体素子に形成された接続用電極と、パッケー
ジ側の素子搭載部周辺に形成されたメタライズ層とをと
をワイヤーでつなぐワイヤボンディング方式が従来より
広く使われている。このワイヤーボンディングによる半
導体素子の実装においては、半導体素子は、熱硬化性樹
脂をパッケージとの間に塗布し、 硬化接着して固定され
る。[0004] A semiconductor element is mounted on a package by a wire bonding method in which a connection electrode formed on the semiconductor element and a metallized layer formed around the element mounting portion on the package side are connected by a wire. Widely used. In mounting a semiconductor element by wire bonding, the semiconductor element is fixed by applying a thermosetting resin between the package and the package and curing and bonding.
【０００５】さらに、前記半導体素子が装着されたパッ
ケージ（配線基板) は、その底面に形成された接続端子
と、マザーボード等の外部電気回路基板表面に形成され
た配線導体とをロウ材などの導電性接着剤によって電気
的に接続して実装される。一般に、この外部電気回路基
板は、プリント基板などの樹脂成分を含有する有機質材
料、あるいは有機質材料と無機質材料との複合材で構成
される。Further, the package (wiring board) on which the semiconductor element is mounted is formed by connecting connection terminals formed on the bottom surface of the package and wiring conductors formed on the surface of an external electric circuit board such as a motherboard with a conductive material such as brazing material. It is mounted by being electrically connected with a conductive adhesive. Generally, the external electric circuit board is made of an organic material containing a resin component, such as a printed board, or a composite material of an organic material and an inorganic material.
【０００６】[0006]
【発明が解決しようとする課題】上記の配線基板におけ
る絶縁基板として従来より使用されているアルミナ、ム
ライトなどのセラミックスは、２００ＭＰａ以上の高強
度を有し、しかもメタライズ配線層などとの多層化技術
として信頼性の高い点で多用されているが、半導体素子
を載置、実装した場合、半導体素子の作動時に発する熱
が絶縁基板と外部電気回路基板の両方に繰り返し印加さ
れると、前記樹脂成分を含む外部電気回路基板と前記セ
ラミック絶縁基板との熱膨張係数差が１０ｐｐｍ／℃以
上と大きいために、熱応力歪みが発生する。また、ヤン
グ率が３００ＧＰａ以上と大きいために基板自体が変形
しにくいために高い熱応力が集中することになる。Ceramics such as alumina and mullite which have been conventionally used as an insulating substrate in the above-mentioned wiring board have a high strength of 200 MPa or more and have a multi-layered technology with a metallized wiring layer and the like. Although it is often used in terms of high reliability, when the semiconductor element is mounted and mounted, when the heat generated during the operation of the semiconductor element is repeatedly applied to both the insulating substrate and the external electric circuit board, the resin component The thermal stress distortion occurs because the difference in thermal expansion coefficient between the external electric circuit board including the above and the ceramic insulating board is as large as 10 ppm / ° C. or more. Further, since the Young's modulus is as large as 300 GPa or more, the substrate itself is not easily deformed, so that high thermal stress is concentrated.
【０００７】この熱応力は、搭載される半導体素子にお
ける電極数およびパッケージにおける接続端子数が３０
０以下と比較的少ない場合には、半導体素子から発生す
る熱応力も小さいが、電極数や接続端子数が３００以上
の場合には、半導体素子からの発熱量も大きく、しかも
パッケージ自体も大型化し、半導体素子の作動／停止に
よりこれがパッケージの半導体素子の実装部に繰り返し
印加されると、パッケージの外部電気回路基板との接続
端子の外周部及び界面に応力が集中し、パッケージの接
続端子が絶縁基板から剥離したり、パッケージの接続端
子を外部電気回路の配線導体に長期にわたり安定に電気
的接続させることができないという致命的な欠点を有し
ていた。This thermal stress is caused by the fact that the number of electrodes in a semiconductor element to be mounted and the number of connection terminals in a package are 30.
When the number is relatively small, ie, 0 or less, the thermal stress generated from the semiconductor element is small. However, when the number of electrodes and the number of connection terminals are 300 or more, the heat generation from the semiconductor element is large, and the package itself becomes large. When this is repeatedly applied to the mounting portion of the semiconductor element of the package due to the operation / stop of the semiconductor element, stress concentrates on the outer peripheral portion and interface of the connection terminal with the external electric circuit board of the package, and the connection terminal of the package is insulated It has a fatal disadvantage that it cannot be peeled off from the substrate or cannot be stably electrically connected to a wiring conductor of an external electric circuit for a long time.
【０００８】この不都合を解消するため、本出願人は、
先に従来のアルミナ、ムライト等のセラミックスに替え
て、外部電気回路基板と近似した熱膨張係数を有する高
熱膨張のセラミックス、例えば、特願平８−３２２０３
８号に記載されているようなガラスセラミック焼結体を
絶縁基板材料として用いることが検討された。[0008] To solve this inconvenience, the present applicant has
First, instead of conventional ceramics such as alumina and mullite, ceramics of high thermal expansion having a thermal expansion coefficient similar to that of an external electric circuit board, for example, Japanese Patent Application No. 8-32203
Use of a glass ceramic sintered body as described in No. 8 as an insulating substrate material has been studied.
【０００９】この熱膨張のガラスセラミックスは、熱膨
張係数が８乃至２５ｐｐｍ／℃とアルミナに比較してか
なり高く、また、ヤング率が２００ＧＰａ以下と低く、
上記したパッケージと外部電気回路基板の接続部との間
に生ずる接続不良は回避できる。しかしながら、このよ
うな高熱膨張のガラスセラミック焼結体を絶縁基板材料
として用いた配線基板においては、シリコンより成る半
導体素子（熱膨張係数：２乃至３ｐｐｍ／℃) との熱膨
張差が逆に大きくなり、半導体素子の接続用電極と絶縁
基板に設けられたメタライズ配線層との間に接続不良が
発生したり、この熱膨張差による応力で、低いヤング率
によって配線基板自体に反りが発生し、外部電気回路基
板との接続部に不良が発生するなどの新たな問題を生ず
る。この配線基板自体の反りの発生は、ＣＳＰ型パッケ
ージにおいて特に顕著である。This glass ceramic of thermal expansion has a coefficient of thermal expansion of 8 to 25 ppm / ° C., which is considerably higher than that of alumina, and has a Young's modulus as low as 200 GPa or less.
The above-described connection failure between the package and the connection portion of the external electric circuit board can be avoided. However, in a wiring board using such a high thermal expansion glass ceramic sintered body as an insulating substrate material, the difference in thermal expansion from a semiconductor element made of silicon (coefficient of thermal expansion: 2 to 3 ppm / ° C.) is large. A connection failure occurs between the connection electrode of the semiconductor element and the metallized wiring layer provided on the insulating substrate, or the wiring substrate itself is warped due to a low Young's modulus due to the stress due to the difference in thermal expansion, A new problem arises, such as the occurrence of a defect in the connection portion with the external electric circuit board. This warpage of the wiring board itself is particularly remarkable in the CSP type package.
【００１０】従って、本発明は、高熱膨張の配線基板表
面に対して、半導体素子を作動／停止による熱サイクル
の印加に対しても、強固に且つ長期にわたり安定した接
続状態を維持できる半導体素子実装基板を提供すること
を目的とするものである。Therefore, the present invention provides a semiconductor element mounting which can maintain a strong and stable connection state for a long time even when a thermal cycle is applied to the surface of a wiring board having high thermal expansion by operating / stopping the semiconductor element. It is intended to provide a substrate.
【００１１】[0011]
【課題を解決するための手段】本発明者らは、上記した
半導体素子の高熱膨張の絶縁基板を具備した配線基板へ
の実装時において発生する熱応力を緩和させる方法につ
いて種々検討を重ねた結果、パッケージ上に半導体素子
を接着固定させるのに用いる熱硬化性樹脂の熱膨張係数
とヤング率を特定範囲に制御することにより、発生した
熱応力が吸収され、応力歪みが緩和される結果、前記目
的が達成されることを見いだし、本発明に至った。Means for Solving the Problems The present inventors have conducted various studies on a method for relaxing thermal stress generated when a semiconductor element is mounted on a wiring board having an insulating substrate having a high thermal expansion. By controlling the thermal expansion coefficient and the Young's modulus of the thermosetting resin used for bonding and fixing the semiconductor element on the package to a specific range, the generated thermal stress is absorbed, and the stress distortion is reduced. The inventors have found that the object is achieved, and have reached the present invention.
【００１２】即ち、本発明の半導体素子実装基板は、４
０℃から４００℃における熱膨張係数が８〜２５ｐｐｍ
／℃、ヤング率が２００ＧＰａ以下の絶縁基板の表面に
メタライズ配線層を被着形成してなる配線基板の表面
に、接続用電極を具備する半導体素子を熱硬化性樹脂に
より接着固定し、前記メタライズ配線層と前記接続用電
極とを導電性接続部材によって接続してなる半導体素子
実装基板において、前記固定用の熱硬化性樹脂の−４０
℃〜２５℃における熱膨張係数が１０〜４０ｐｐｍ／℃
であり、かつ前記温度範囲におけるヤング率が５〜１０
ＧＰａであることを特徴とするものであり、前記熱硬化
性樹脂は、フェノールノボラック型エポキシ樹脂または
クレゾールノボラック型エポキシ樹脂のいずれかからな
ることが望ましい。さらに、本発明によれば、前記半導
体素子の面積が前記配線基板の面積の８０％以上である
ことが特に望ましい。That is, the semiconductor device mounting substrate of the present invention
The coefficient of thermal expansion from 0 ° C to 400 ° C is 8 to 25 ppm
/ ° C., a semiconductor element having connection electrodes is adhered and fixed with a thermosetting resin on the surface of a wiring board formed by applying a metallized wiring layer on the surface of an insulating substrate having a Young's modulus of 200 GPa or less. In a semiconductor element mounting substrate in which a wiring layer and the connection electrode are connected by a conductive connection member, the fixing thermosetting resin -40 may be used.
Coefficient of thermal expansion at 25 ° C to 10 to 40 ppm / ° C
And the Young's modulus in the temperature range is 5 to 10
GPa, and the thermosetting resin is desirably made of either a phenol novolak epoxy resin or a cresol novolak epoxy resin. Furthermore, according to the present invention, it is particularly desirable that the area of the semiconductor element is 80% or more of the area of the wiring board.
【００１３】本発明の半導体素子実装基板においては、
半導体素子と配線基板における絶縁基板の熱膨張係数の
差によって生ずる熱応力を、半導体素子を接着固定する
熱硬化性樹脂として、前記特定の熱膨張係数とヤング率
とを有する熱硬化性樹脂を用いることにより、半導体素
子の配線基板への接合部を補強すると共に、熱応力の低
減化、分散化を図ることができる結果，半導体素子と配
線基板との間に発生する応力の集中が回避され、半導体
素子と配線基板との間で接続不良を起こすことが無く、
長期にわたり確実に、強固な電気的接続が保持され、長
期使用に対しても高い信頼性が担保される。In the semiconductor device mounting board of the present invention,
The thermal stress caused by the difference between the thermal expansion coefficients of the insulating element in the semiconductor element and the wiring board is used.The thermosetting resin having the specific thermal expansion coefficient and the Young's modulus is used as the thermosetting resin for bonding and fixing the semiconductor element. As a result, the joint between the semiconductor element and the wiring board can be reinforced, and the thermal stress can be reduced and dispersed. As a result, the concentration of stress generated between the semiconductor element and the wiring board can be avoided, No connection failure between the semiconductor element and the wiring board
Strong electrical connections are reliably maintained for a long time, and high reliability is ensured even for long-term use.
【００１４】[0014]
【発明の実施の形態】以下に、本発明の半導体実装配線
基板を図面に基づき詳細に説明する。 図１は、本発明の
半導体実装基板の一例を示す図であり、かかる例では、
絶縁基板の表面にメタライズ配線層が被着形成された配
線基板の表面に半導体素子が実装されたものであるが、
この図１では、配線基板としてボールグリッドアレイ
（ＢＧＡ）型のチップサイズパッケージを用いた場合の
実装構造を示している。なお、図１において、ＡはＢＧ
Ａ型パッケージ、Ｂは半導体素子である。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a semiconductor mounting wiring board according to the present invention will be described in detail with reference to the drawings. FIG. 1 is a diagram showing an example of a semiconductor mounting board of the present invention.
A semiconductor element is mounted on the surface of a wiring board in which a metallized wiring layer is formed on the surface of an insulating substrate.
FIG. 1 shows a mounting structure when a ball grid array (BGA) type chip size package is used as a wiring board. In FIG. 1, A is BG
A type package and B are semiconductor elements.
【００１５】パッケージＡによれば、絶縁基板１の表面
には、半導体素子Ｂと接続されるメタライズ配線層２が
形成されている。また、絶縁基板１の底面には、外部電
気回路基板と接続するための接続端子３が取り付けられ
ており、この接続端子３は、メタライズ配線層２と、絶
縁基板１の内部に形成されたメタライズ配線層４やビア
ホール導体５を介して電気的に接続されている。図１の
ＢＧＡ型パッケージにおいては、接続端子３は、ボール
状の半田ボールにより構成され、絶縁基板１の底面に形
成された接続パッド６に対して半田等により取着されて
いる。According to the package A, the metallized wiring layer 2 connected to the semiconductor element B is formed on the surface of the insulating substrate 1. A connection terminal 3 for connecting to an external electric circuit board is attached to the bottom surface of the insulating substrate 1. The connection terminal 3 is formed by a metallized wiring layer 2 and a metallized layer formed inside the insulating substrate 1. They are electrically connected via the wiring layer 4 and the via-hole conductor 5. In the BGA type package of FIG. 1, the connection terminal 3 is formed of a ball-shaped solder ball, and is attached to a connection pad 6 formed on the bottom surface of the insulating substrate 1 by soldering or the like.
【００１６】一方、半導体素子Ｂは、Ｓｉ材料からな
り、熱硬化性樹脂７により絶縁基板１表面に接着固定さ
れている。また、半導体素子Ｂには、接続用電極８が設
けられており、この接続用電極８はワイヤー９などの導
電性接続部材によってメタライズ配線層２と電気的に接
続されている。また、この半導体素子Ｂおよびワイヤー
９は封止用樹脂１０によって完全に被覆されている。On the other hand, the semiconductor element B is made of a Si material, and is bonded and fixed to the surface of the insulating substrate 1 by a thermosetting resin 7. The semiconductor element B is provided with a connection electrode 8, and the connection electrode 8 is electrically connected to the metallized wiring layer 2 by a conductive connection member such as a wire 9. The semiconductor element B and the wire 9 are completely covered with the sealing resin 10.
【００１７】上記ＢＧＡ型パッケージＡに半導体素子Ｂ
を実装するには、絶縁基板１表面に未硬化（軟質状態）
の熱硬化性樹脂を塗布した後、半導体素子Ｂを載置して
接着した後、約１００乃至２００度の温度に加熱するこ
とにより熱硬化性樹脂を完全硬化して固定される。The BGA type package A has a semiconductor element B
Is mounted on the surface of the insulating substrate 1 in an uncured (soft) state.
After the thermosetting resin is applied, the semiconductor element B is placed and bonded, and then heated to a temperature of about 100 to 200 ° C., whereby the thermosetting resin is completely cured and fixed.
【００１８】また、半導体素子Ｂが実装されたパッケー
ジＡは、絶縁基体１１の表面に配線導体１２が形成され
た外部電気回路基板Ｃに対して、パッケージＡの接続端
子３を配線導体１２に対して、半田などのロウ材により
接着して、パッケージＡが基板Ｃに実装される。The package A on which the semiconductor element B is mounted is connected to the external electric circuit board C on which the wiring conductor 12 is formed on the surface of the insulating base 11 by connecting the connection terminal 3 of the package A to the wiring conductor 12. Then, the package A is mounted on the substrate C by bonding with a brazing material such as solder.
【００１９】本発明によれば、上記絶縁基板１が、４０
乃至４００℃における熱膨張係数が８乃至２５ｐｐｍ／
℃、同温度範囲におけるヤング率が２００ＧＰａ以下で
あることが必要である。このように絶縁基板の熱膨張係
数を上記の範囲に調整することにより、配線基板をプリ
ント基板などの有機樹脂を含む絶縁基板からなる外部電
気回路基板に対して長期に安定した実装構造が提供でき
る。According to the present invention, when the insulating substrate 1 is
Has a coefficient of thermal expansion of 8 to 25 ppm /
It is necessary that the Young's modulus in the same temperature range is 200 GPa or less. By adjusting the thermal expansion coefficient of the insulating substrate to the above range in this manner, it is possible to provide a long-term stable mounting structure of the wiring substrate to an external electric circuit board made of an insulating substrate containing an organic resin such as a printed circuit board. .
【００２０】また、この配線基板における絶縁基板は、
４０乃至４００℃でのヤング率が２００ＧＰａ以下、特
に１５０ＧＰａ以下のセラミック焼結体からなることが
望ましい。これはヤング率が２００ＧＰａよりも高い
と、高温もしくは低温においてパッケージの変形が小さ
く、そのため発生応力が高くなる可能性があるためであ
る。Further, the insulating substrate in this wiring board is
It is desirable to use a ceramic sintered body having a Young's modulus at 40 to 400 ° C. of 200 GPa or less, particularly 150 GPa or less. This is because if the Young's modulus is higher than 200 GPa, the deformation of the package is small at a high temperature or a low temperature, so that the generated stress may increase.
【００２１】このような焼結体として、例えば、前記特
願平８−３２２０３８号の明細書中に記載されているよ
うなリチウム珪酸系ガラス、ＰｂＯ系ガラス、ＺｎＯ系
ガラス、ＢａＯ系ガラス等の高熱膨張の結晶化ガラス粉
末に対して、エンステタイト、フォルステライト、フォ
ルステライト、クオーツ、トリジマイト、クリストバラ
イト、ＭｇＯ、ＺｒＯ2 、ペタライト、ネフェリン等の
各種高熱膨張のセラミックフィラーを混合し、８００〜
１０５０℃で焼成して得られる。Examples of such a sintered body include lithium silicate glass, PbO glass, ZnO glass, BaO glass and the like as described in the specification of Japanese Patent Application No. 8-322038. against the crystallized glass powder of high thermal expansion, mixed Ensutetaito, forsterite, forsterite, quartz, tridymite, cristobalite, MgO, ZrO 2, petalite, the ceramic filler of various high thermal expansion, such as nepheline, 800
It is obtained by firing at 1050 ° C.
【００２２】特に好適な焼結体としては、Ｌｉ2 Ｏを５
乃至３０重量％含有する屈伏点が４００℃乃至８００℃
のリチウム珪酸ガラスを２０乃至８０体積％と、必須成
分としてフォルステライトと、クオーツやクリストバラ
イトなどのＳｉＯ2 系フィラーとを２０乃至８０体積％
の割合で含有する成形体を焼成して得られた焼結体を挙
げることができる。Particularly preferred sintered bodies include Li 2 O
Yield point of 400 to 800 ° C containing from 30 to 30% by weight
20 to 80% by volume of lithium silicate glass, forsterite as an essential component, and 20 to 80% by volume of a SiO 2 filler such as quartz or cristobalite.
And a sintered body obtained by firing a molded body containing the above-mentioned sintered body.
【００２３】この焼結体は、 均質の製品を再現性良く比
較的容易に製造できるだけでなく、ガラス成分として、
上記Ｌｉ2 Ｏを５乃至３０重量％含有するリチウム珪酸
ガラスを用いることにより、焼結後の焼結体中に高熱膨
張のリチウムシリケート（例えば、Ｌｉ2 ＳｉＯ3 ）を
析出することができ、屈伏点が比較的低く、ガラスの添
加量が少なくても低温焼成が可能であるために、Ｃｕ、
Ａｇ等からなるメタライズ配線層と同時に焼成すること
ができるため好都合である。This sintered body not only can produce a homogeneous product relatively easily with good reproducibility, but also as a glass component,
By using the lithium silicate glass containing 5 to 30% by weight of Li 2 O, lithium silicate (for example, Li 2 SiO 3 ) having high thermal expansion can be deposited in the sintered body after sintering, and the yielding can be reduced. Points are relatively low, and low-temperature firing is possible even with a small amount of glass added.
This is convenient because it can be fired simultaneously with the metallized wiring layer made of Ag or the like.
【００２４】さらに、用いるリチウム珪酸ガラスの屈伏
点が４００℃乃至８００℃であることにより、ガラス含
有量を低減しフィラー量を増加することができ、また焼
成収縮開始温度を上昇することが可能である。それによ
り、成形時に添加された有機樹脂等の成形用バインダー
を効率的に除去できるとともに、絶縁体と同時焼成され
るメタライズ層との焼成条件をマッチングさせることが
できる。Further, when the deformation point of the lithium silicate glass used is 400 ° C. to 800 ° C., the glass content can be reduced, the filler amount can be increased, and the firing shrinkage starting temperature can be increased. is there. Thus, the molding binder such as an organic resin added at the time of molding can be efficiently removed, and the firing conditions of the insulator and the metallized layer that is simultaneously fired can be matched.
【００２５】また、本発明によれば、半導体素子Ｂを接
着固定するための熱硬化性樹脂７が、硬化後の−４０乃
至２５℃における熱膨張係数が１０乃至４０ｐｐｍ／℃
で、同様の温度範囲におけるヤング率が５乃至１０ＧＰ
ａであることが重要である。この熱硬化性樹脂の熱膨張
係数が１０ｐｐｍ／℃より低い場合、高温または低温時
の熱膨張、収縮が小さく半導体素子を圧迫し、高応力が
生じてしまい、また、４０ｐｐｍ／℃を越える場合は逆
に高温低温時の熱膨張収縮が大きく、同様に半導体素子
に高応力が生じる。熱膨張係数の好ましい範囲は、１０
〜３０ｐｐｍ／℃である。According to the present invention, the thermosetting resin 7 for bonding and fixing the semiconductor element B has a coefficient of thermal expansion at -40 to 25 ° C. after curing of 10 to 40 ppm / ° C.
And the Young's modulus in the same temperature range is 5 to 10 GP.
It is important that a. When the thermal expansion coefficient of this thermosetting resin is lower than 10 ppm / ° C., the thermal expansion and shrinkage at high or low temperature are small and the semiconductor element is pressed, and high stress is generated. Conversely, thermal expansion and contraction at high and low temperatures are large, and high stress is similarly generated in the semiconductor element. The preferred range of the coefficient of thermal expansion is 10
３０30 ppm / ° C.
【００２６】また、ヤング率が５ＧＰａより低いと、熱
硬化性樹脂の変形が大きく、半導体素子と絶縁基板との
接続が不十分となり、１０ＧＰａより大きいと変形量が
小さく半導体素子と絶縁基板との熱膨張差の違いにより
反りが発生し高応力が生じてしまう。ヤング率の好まし
い範囲は、７〜９ＧＰａである。On the other hand, if the Young's modulus is lower than 5 GPa, the thermosetting resin is greatly deformed and the connection between the semiconductor element and the insulating substrate is insufficient. If the Young's modulus is higher than 10 GPa, the deformation is small and the distance between the semiconductor element and the insulating substrate is small. Warpage occurs due to a difference in thermal expansion, and high stress occurs. A preferred range of the Young's modulus is 7 to 9 GPa.
【００２７】このような特性を有する熱硬化性樹脂とし
ては、上記の特性を満足するものであれば、特に限定す
るものではないが、例えば、例えば、フェノール樹脂、
ユリア樹脂、 メラミン樹脂、 エポキシ樹脂、 不飽和ポリ
エステル樹脂、 フタル酸ジアリル樹脂、 ポリイミド樹
脂、 シリコーン樹脂、 ポリウレタン樹脂などを挙げるこ
とができる。The thermosetting resin having such characteristics is not particularly limited as long as it satisfies the above characteristics. For example, a phenol resin,
Examples include urea resin, melamine resin, epoxy resin, unsaturated polyester resin, diallyl phthalate resin, polyimide resin, silicone resin, and polyurethane resin.
【００２８】これらの内でも、 ビスフェノール系エポキ
シ樹脂、 フェノールノボラック系エポキシ樹脂、 クレゾ
ールノボラック系エポキシ樹脂、 ブロム化エポキシ樹
脂、 脂環式エポキシ樹脂などのエポキシ系樹脂が特に好
ましく、さらには、フェノールノボラック型エポキシ樹
脂、クレゾールノボラック型エポキシ樹脂が硬化温度が
低く、硬化時の発生応力が小さい点で最も望ましい。Of these, epoxy resins such as bisphenol epoxy resin, phenol novolak epoxy resin, cresol novolak epoxy resin, brominated epoxy resin, and alicyclic epoxy resin are particularly preferable. Epoxy resins and cresol novolak type epoxy resins are the most desirable in that the curing temperature is low and the stress generated during curing is small.
【００２９】また、熱硬化性樹脂７のヤング率および熱
膨張係数を前記の範囲に制御するためには、前に熱硬化
性樹脂に対して、石英ガラス、アルミナ、マイカ、ジル
コニウムシリケート、リチウムシリケート等の無機質フ
ィラーを樹脂１００重量部に対して、１０〜２００重量
部の割合で配合することにより調整できる。Further, in order to control the Young's modulus and the coefficient of thermal expansion of the thermosetting resin 7 within the above-mentioned ranges, the thermosetting resin must be made of quartz glass, alumina, mica, zirconium silicate, lithium silicate. Can be adjusted by blending the inorganic filler such as 10 to 200 parts by weight with respect to 100 parts by weight of the resin.
【００３０】本発明に於いては、既に前述したように配
線基板を形成する絶縁基板はヤング率が２００ＧＰａ以
下であると共に、その４０〜４００℃における熱膨張係
数が８乃至２５ｐｐｍ／℃であることがより好ましい。In the present invention, as described above, the insulating substrate forming the wiring substrate has a Young's modulus of 200 GPa or less and a coefficient of thermal expansion at 40 to 400 ° C. of 8 to 25 ppm / ° C. Is more preferred.
【００３１】前述した高熱膨張を有する絶縁基板を具備
する配線基板に対して、前記特定範囲の熱膨張係数およ
びヤング率を有する熱硬化性樹脂により半導体素子を接
着固定することにより、半導体素子の作動に伴う発熱に
より、配線基板と半導体素子の熱膨張差に起因して発生
した熱応力を絶縁基板のたわみと歪みによって吸収でき
発生する熱応力自体を小さくすることができる。The semiconductor element is bonded and fixed to the wiring board having the above-mentioned insulating substrate having a high thermal expansion with a thermosetting resin having a specific range of thermal expansion coefficient and Young's modulus. As a result, the thermal stress generated due to the difference in thermal expansion between the wiring substrate and the semiconductor element can be absorbed by the deflection and distortion of the insulating substrate, and the generated thermal stress itself can be reduced.
【００３２】なお、図１において、半導体素子Ｂおよび
ワイヤを封止する樹脂としては、エポキシ樹脂、フェノ
ール樹脂、メラミン樹脂、ポリイミド樹脂、シリコーン
樹脂等が用いられるが、特にこれらの封止用樹脂は、低
温で硬化が可能なフェノールノボラック型やクレゾール
ノボラック型などのエポキシ樹脂が特に望ましい。In FIG. 1, epoxy resin, phenol resin, melamine resin, polyimide resin, silicone resin and the like are used as the resin for sealing the semiconductor element B and the wire. Epoxy resins such as phenol novolak type and cresol novolak type, which can be cured at a low temperature, are particularly desirable.
【００３３】[0033]
【実施例】表１に示す各種セラミック材料について、５
×４×４０ｍｍの形状の焼結体を作製した後、各焼結体
について４０〜４００℃における熱膨張係数およびヤン
グ率を測定し表１に示した。EXAMPLES For various ceramic materials shown in Table 1, 5
After preparing sintered bodies having a shape of × 4 × 40 mm, the thermal expansion coefficient and Young's modulus of each sintered body at 40 to 400 ° C. were measured and are shown in Table 1.
【００３４】また、表１に示す各種セラミック材料を絶
縁基板として用いて、その表面に半導体素子と接続され
る接続パッドを含む配線層、内部配線層およびビアホー
ル導体、底面にボール状端子を取り付けるための接続パ
ッドを銅ペーストの印刷、あるいは充填により周知の方
法に従って、同時焼成して形成した。そして、底面の接
続パッドには、高融点半田（Ｓｎ：Ｐｂ重量比＝１０：
９０）からなるボール状端子を低融点半田（Ｓｎ：Ｐｂ
重量比６３：３７）により取り付けて配線基板を作製し
た。作製した配線基板は、縦×横が１３ｍｍ×１３ｍ
ｍ、厚みが０．４ｍｍとした。Also, various ceramic materials shown in Table 1 are used as an insulating substrate, and a wiring layer including a connection pad connected to a semiconductor element, an internal wiring layer and a via-hole conductor on a surface thereof, and a ball-shaped terminal on a bottom surface. Were formed by simultaneous firing by printing or filling with a copper paste according to a known method. Then, a high melting point solder (Sn: Pb weight ratio = 10:
90) with a low melting point solder (Sn: Pb).
(Weight ratio 63:37) to produce a wiring board. The manufactured wiring board is 13 mm x 13 m in length x width
m and the thickness were 0.4 mm.
【００３５】一方、Ｓｉからなり４０〜４００℃におけ
る熱膨張係数が２．６ｐｐｍ／℃の半導体素子を準備
し、これを配線基板上面に表２に示す各種の熱硬化性樹
脂に対して石英ガラスまたはアルミナを表２の比率で配
合し、混練して調整したペースト上の熱硬化性樹脂を塗
布し、その上に１０ｍｍ×１０ｍｍのサイズの半導体素
子を載置し、大気雰囲気中で１８０℃で２時間熱処理
し、熱硬化性樹脂を硬化させて半導体素子を配線基板に
固着した。On the other hand, a semiconductor element made of Si and having a coefficient of thermal expansion of 2.6 ppm / ° C. at 40 to 400 ° C. is prepared, and is placed on the upper surface of the wiring board with various thermosetting resins shown in Table 2 with quartz glass. Alternatively, alumina was blended in the ratio shown in Table 2, a thermosetting resin on the paste adjusted by kneading was applied, and a semiconductor element having a size of 10 mm × 10 mm was placed thereon, and was heated at 180 ° C. in an air atmosphere. Heat treatment was performed for 2 hours to cure the thermosetting resin, and the semiconductor element was fixed to the wiring board.
【００３６】そして、半導体素子の接続用電極と、配線
基板表面の接続パッドとを金によるワイヤボンディング
により電気的に接続し、さらに、この半導体素子とワイ
ヤボンディング部をフェノールノボラック型エポキシ樹
脂からなる封止用樹脂を流して１５０℃に加熱硬化して
封止用樹脂を硬化させた。The connection electrodes of the semiconductor element and the connection pads on the surface of the wiring board are electrically connected by gold wire bonding, and the semiconductor element and the wire bonding portion are sealed with a phenol novolak type epoxy resin. The sealing resin was flown and heated and cured at 150 ° C. to cure the sealing resin.
【００３７】（熱サイクル試験）上記のようにして半導
体素子をパッケージ用配線基板に実装したものをガラス
エポキシ基板からなる４０〜２００℃における熱膨張係
数が１５ｐｐｍ／℃の絶縁基体の表面に銅箔からなる配
線導体が形成されたプリント基板を準備し、上記のパッ
ケージ用配線基板をプリント基板の上の配線導体とパッ
ケージ用絶縁基板の接続端子が接続されるように位置合
わせして低融点半田を用いてＮ2 雰囲気中で２６０℃で
３分間熱処理してパッケージをプリント基板の表面に実
装した。(Thermal cycle test) A semiconductor element mounted on a wiring board for a package as described above is coated with a copper foil on a surface of an insulating substrate made of a glass epoxy substrate and having a thermal expansion coefficient of 15 ppm / ° C at 40 to 200 ° C. Prepare a printed circuit board on which a wiring conductor made of is formed, align the wiring board for the package so that the wiring conductor on the printed board and the connection terminal of the insulating board for the package are connected, and apply a low melting point solder. The package was mounted on the surface of a printed circuit board by heat treatment at 260 ° C. for 3 minutes in an N 2 atmosphere.
【００３８】このようにしてパッケージをプリント基板
に実装したものを大気の雰囲気にて−４０℃と１２５℃
の各温度に制御した恒温槽に試験サンプルを１５分／１
５分の保持を１サイクルとして最高１０００サイクル繰
り返した。The package mounted on the printed circuit board in this manner is subjected to an air atmosphere at -40 ° C. and 125 ° C.
The test sample was placed in a thermostatic chamber controlled at each temperature for 15 minutes / 1.
Up to 1,000 cycles were repeated with one cycle of holding for 5 minutes.
【００３９】そして、１００サイクル毎にパッケージと
外部電気回路基板の配線導体との電気抵抗を測定し電気
抵抗に変化が現れるまでのサイクル数をカウントした。
結果を表２に示す。Then, the electric resistance between the package and the wiring conductor of the external electric circuit board was measured every 100 cycles, and the number of cycles until the electric resistance changed was counted.
Table 2 shows the results.
【００４０】[0040]
【表１】 [Table 1]
【００４１】[0041]
【表２】 [Table 2]
【００４２】表１、表２より明らかなように、固定用の
熱硬化性樹脂として、熱膨張係数が１０〜４０ｐｐｍ／
℃、ヤング率が５〜１０ＧＰａの樹脂を用いた試料Ｎ
ｏ．４，５，９，１０，１１，１６，１７，２１，２２
では、パッケージと外部電気回路基板との間に電気抵抗
変化は熱サイクル１０００回まで全く見られず、極めて
安定で良好な電気的接続状態を維持できた。As is clear from Tables 1 and 2, the thermosetting resin for fixing has a coefficient of thermal expansion of 10 to 40 ppm /
C using a resin having a Young's modulus of 5 to 10 GPa
o. 4,5,9,10,11,16,17,21,22
No change in electric resistance was observed between the package and the external electric circuit board up to 1000 thermal cycles, and an extremely stable and favorable electric connection state was maintained.
【００４３】これに対して、熱膨張係数またはヤング率
が上記の範囲を逸脱する試料Ｎo.１，２，３，６，７，
８，１２，１３，１４，１５，１８，１９，２０，２
３，２４では１０００サイクル未満で抵抗変化が検出さ
れ、実装後の信頼性に欠けることがわかった。On the other hand, samples Nos. 1, 2, 3, 6, 7, and whose thermal expansion coefficient or Young's modulus deviated from the above range were used.
8, 12, 13, 14, 15, 18, 19, 20, 2
In Nos. 3 and 24, a resistance change was detected in less than 1000 cycles, and it was found that reliability after mounting was lacking.
【００４４】[0044]
【発明の効果】上述したように、本発明の配線基板の実
装構造によれば、半導体素子を高熱膨張の配線基板上に
実装した場合に、両者の熱膨張係数の差に起因する応力
発生を緩和し、半導体素子と配線基板とを長期間にわた
り正確、かつ強固に電気的接続させることが可能とな
る。As described above, according to the wiring board mounting structure of the present invention, when a semiconductor element is mounted on a wiring board having a high thermal expansion, stress generation due to a difference in thermal expansion coefficient between the two is prevented. As a result, the semiconductor element and the wiring substrate can be accurately and firmly electrically connected for a long period of time.
【図１】本発明におけるボールグリッドアレイ型の半導
体素子収納用パッケージにおけるの半導体素子の実装構
造を説明するための断面図である。FIG. 1 is a cross-sectional view illustrating a mounting structure of a semiconductor element in a ball grid array type semiconductor element storage package according to the present invention.
１ 絶縁基板 ２ メタライズ配線層 ３ 接続端子 ６ 接続パッド ７ 固定用熱硬化性樹脂 ８ 電極パッド ９ ワイヤ １０ 封止用樹脂 １１ 絶縁基体 １２ 配線導体 Ａ 配線基板（パッケージ） Ｂ 半導体素子 Ｃ 外部電気回路基板 REFERENCE SIGNS LIST 1 insulating substrate 2 metallized wiring layer 3 connection terminal 6 connection pad 7 fixing thermosetting resin 8 electrode pad 9 wire 10 sealing resin 11 insulating base 12 wiring conductor A wiring substrate (package) B semiconductor element C external electric circuit board
───────────────────────────────────────────────────── フロントページの続き (72)発明者 永江 謙一 鹿児島県国分市山下町１番４号 京セラ株 式会社総合研究所内 (72)発明者 民 保秀 鹿児島県国分市山下町１番４号 京セラ株 式会社総合研究所内 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Kenichi Nagae 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Inside the Kyocera Research Institute (72) Inventor Yasuhide Minami 1-4-4 Yamashita-cho, Kokubu-shi, Kagoshima Kyocera Inside Research Institute, Inc.
Claims (3)
８〜２５ｐｐｍ／℃、ヤング率が２００ＧＰａ以下の絶
縁基板の表面にメタライズ配線層を被着形成してなる配
線基板の表面に、接続用電極を具備する半導体素子を熱
硬化性樹脂により接着固定し、前記メタライズ配線層と
前記接続用電極とを導電性接続部材によって接続してな
る半導体素子実装基板において、前記固定用の熱硬化性
樹脂の−４０℃〜２５℃における熱膨張係数が１０〜４
０ｐｐｍ／℃であり、かつ前記温度範囲におけるヤング
率が５〜１０ＧＰａであることを特徴とする半導体素子
実装基板。An insulating substrate having a coefficient of thermal expansion of 8 to 25 ppm / ° C. at a temperature of 40 ° C. to 400 ° C. and a Young's modulus of 200 GPa or less is provided with a metallized wiring layer formed on a surface thereof. In a semiconductor element mounting substrate in which a semiconductor element having electrodes is bonded and fixed with a thermosetting resin and the metallized wiring layer and the connection electrode are connected by a conductive connection member, the fixing thermosetting resin Has a coefficient of thermal expansion at −40 ° C. to 25 ° C. of 10 to 4
A semiconductor element mounting substrate, wherein the substrate has 0 ppm / ° C. and a Young's modulus in the temperature range of 5 to 10 GPa.
ク型エポキシ樹脂、 クレゾールノボラック型エポキシ樹
脂のいずれかである請求項１記載の半導体素子実装基
板。2. The semiconductor element mounting board according to claim 1, wherein the thermosetting resin is one of a phenol novolak type epoxy resin and a cresol novolak type epoxy resin.
積の８０％以上であることを特徴とする請求項１記載の
半導体素子実装基板。3. The semiconductor element mounting board according to claim 1, wherein an area of said semiconductor element is 80% or more of an area of said wiring board.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32844697A JP3336240B2 (en) | 1997-11-28 | 1997-11-28 | Semiconductor element mounting board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP32844697A JP3336240B2 (en) | 1997-11-28 | 1997-11-28 | Semiconductor element mounting board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11163002A true JPH11163002A (en) | 1999-06-18 |
| JP3336240B2 JP3336240B2 (en) | 2002-10-21 |
Family
ID=18210372
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP32844697A Expired - Fee Related JP3336240B2 (en) | 1997-11-28 | 1997-11-28 | Semiconductor element mounting board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3336240B2 (en) |
Cited By (11)
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|---|---|---|---|---|
| JP2001015649A (en) * | 1999-06-29 | 2001-01-19 | Kyocera Corp | Semiconductor element mounting wiring substrate and wiring substrate mounting structure |
| JP2001035953A (en) * | 1999-07-16 | 2001-02-09 | Hitachi Ltd | Semiconductor device |
| JP2001217350A (en) * | 2000-01-31 | 2001-08-10 | Kyocera Corp | Mounting structure of semiconductor element mounting/ wiring board |
| JP2002299393A (en) * | 2001-01-23 | 2002-10-11 | Nec Corp | Conductive cured resin for semiconductor device and semiconductor device |
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| KR100651800B1 (en) * | 2000-12-21 | 2006-11-30 | 삼성테크윈 주식회사 | Adhesive for semiconductor package and semiconductor package therewith |
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Cited By (16)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001015649A (en) * | 1999-06-29 | 2001-01-19 | Kyocera Corp | Semiconductor element mounting wiring substrate and wiring substrate mounting structure |
| JP2001035953A (en) * | 1999-07-16 | 2001-02-09 | Hitachi Ltd | Semiconductor device |
| JP2001217350A (en) * | 2000-01-31 | 2001-08-10 | Kyocera Corp | Mounting structure of semiconductor element mounting/ wiring board |
| KR100651800B1 (en) * | 2000-12-21 | 2006-11-30 | 삼성테크윈 주식회사 | Adhesive for semiconductor package and semiconductor package therewith |
| JP2002299393A (en) * | 2001-01-23 | 2002-10-11 | Nec Corp | Conductive cured resin for semiconductor device and semiconductor device |
| US7800210B2 (en) | 2005-03-18 | 2010-09-21 | Fujitsu Semiconductor Limited | Semiconductor device |
| JPWO2006100738A1 (en) * | 2005-03-18 | 2008-08-28 | 富士通株式会社 | Semiconductor device and manufacturing method thereof |
| KR100924705B1 (en) | 2005-03-18 | 2009-11-04 | 후지쯔 마이크로일렉트로닉스 가부시키가이샤 | Semiconductor device |
| WO2006100738A1 (en) * | 2005-03-18 | 2006-09-28 | Fujitsu Limited | Semiconductor device and method for manufacturing same |
| US20160113127A1 (en) * | 2014-10-16 | 2016-04-21 | Infineon Technologies Ag | Electronic module having an electrically insulating structure with material having a low modulus of elasticity |
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| US10813229B2 (en) * | 2014-10-16 | 2020-10-20 | Infineon Technologies Ag | Electronic module having an electrically insulating structure with material having a low modulus of elasticity |
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| JP2020079808A (en) * | 2020-03-02 | 2020-05-28 | 日立オートモティブシステムズ株式会社 | Thermal air flowmeter |
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