JP3318498B2 - Circuit board for mounting semiconductor elements - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board for mounting a semiconductor element, and more particularly, to a method for mounting a semiconductor element on a large-sized surface mounting wiring board, and further including a resin between the wiring board and the semiconductor element. The present invention relates to a semiconductor element mounting wiring board having a heat history characteristic, a use durability, and an excellent reliability having a mounting structure in which an agent is injected and cured.

[0002]

2. Description of the Related Art Conventionally, a wiring board has a structure in which a metallized wiring layer is provided on the surface or inside of an insulating substrate.
A typical example of the wiring board is a semiconductor element housing package for mounting a semiconductor element, particularly a semiconductor integrated circuit element such as an LSI (large scale integrated circuit element), which is generally an insulating substrate made of alumina ceramics. A plurality of metallized wiring layers made of a high melting point metal powder such as tungsten and molybdenum are arranged on the surface and inside of the semiconductor device, and are electrically connected to a semiconductor element mounted thereon.

In general, as the degree of integration of a semiconductor device increases, the number of electrodes formed on the semiconductor device also increases. As a result, the number of terminals in a semiconductor housing package for housing the same increases.

If the installation density of the corresponding connection terminals does not change as the number of electrodes increases, the size of the package itself needs to be increased. However, recently, there is a strong need to reduce the size of the package. Growth is limited.

Therefore, the connection density of the connection terminals in the package must be rapidly increased. However, the conventional wire bonding connection method is not enough for the recent high integration tendency of semiconductor devices. Response has become difficult and is approaching its limits.

Therefore, recently, the connection between the package and the semiconductor element has been made by directly bonding the connection electrode on the lower surface of the semiconductor element and the connection terminal of the package by a wire bonding method in which a wire is connected from the periphery of the semiconductor element to the connection terminal of the package. It is shifting to the flip chip specification to be attached.

In connection with the flip chip specification, a filler such as a thermosetting resin is injected between the semiconductor element and the package, and the filler is hardened to mechanically reinforce the brazed connection portion of the semiconductor element. Often done.

Further, the mounting structure of the wiring board is formed by electrically connecting the connection terminals of the package (wiring board) on which the semiconductor element is mounted and the wiring conductors of the external electrode circuit board. The external electrode circuit board is often made of an organic material containing a resin component such as a printed board or a composite material of an organic material and an inorganic material.

[0009]

Conventionally, ceramics such as alumina and mullite have a high strength of 200 MPa or more as an insulating substrate in the above-mentioned package, and have a multi-layered technology with a metallized wiring layer and the like. In the case of insulating substrates such as alumina, heat generated during the operation of the semiconductor element in the mounting structure on which the semiconductor element is mounted is often used for the insulating substrate and the printed circuit board. When repeatedly applied to both the external electric circuit board containing the resin component, the difference in thermal expansion coefficient between the insulating substrate of the package (wiring board) and the external electric circuit board becomes 10 pp.
Since the temperature is as large as m / ° C. or more, thermal stress distortion occurs between these connection parts.

This thermal stress is caused by the fact that the number of terminals of the package is 30.
In the case of a relatively small number of less than 0, the generated thermal stress is small and its influence is not so much a problem. However, in a large package having 300 or more connection terminals, the generated thermal stress increases and the When this is repeatedly applied to the mounting portion of the semiconductor element of the package by the start / stop cycle, the stress strain is concentrated on the joint interface between the connection terminal of the package and the connection portion of the external electric circuit board, and the connection is caused by the stress strain. A connection failure occurs due to the terminal peeling off from the insulating substrate or the connection terminal peeling off from the wiring conductor of the external electric circuit, and the connection terminal of the package is stably electrically connected to the wiring conductor of the external electrode circuit for a long time. Had a fatal defect that it could not be performed.

In order to solve this inconvenience, instead of conventional ceramics such as alumina and mullite, a glass ceramic having a high coefficient of thermal expansion having a higher coefficient of thermal expansion, for example, Japanese Patent Application Laid-Open No. Hei 8-279574 and Japanese Patent Application No. Hei 8-322038. The use of a material such as a glass-ceramic sintered body as described in the specification of U.S. Pat.

This glass ceramic having a high coefficient of thermal expansion has a coefficient of thermal expansion of 8 to 25 ppm / .degree. C., which is considerably higher than that of alumina. However, when such a high-thermal-expansion glass-ceramic sintered body is used as an insulating substrate material, the difference in thermal expansion from a semiconductor element (coefficient of thermal expansion: 2 to 3 ppm) made of silicon is increased. A new problem arises in that a connection failure occurs between the connection electrode of the semiconductor element and the metallized wiring layer provided on the insulating substrate.

The present inventors have conducted various studies on a method of alleviating the thermal stress generated at the time of mounting the semiconductor element on a wiring board such as a package or the like, and as a result, have found that the By limiting the thermal expansion coefficient and Young's modulus of the reinforcing filler to be filled to a certain range, it has been found that the generated thermal stress is absorbed and the stress distortion is reduced, and the present invention has been achieved.

Therefore, according to the present invention, a semiconductor element is brazed to a wiring board such as a semiconductor package or the like, and a specific filler containing a thermosetting resin is injected and cured between connecting portions between the semiconductor package and the semiconductor element. Accordingly, the above-described defect is completely avoided, and it is an object of the present invention to provide a semiconductor element mounting wiring board which is remarkably excellent in long-term use reliability capable of maintaining a strong and stable electric connection for a long time. Is what you do.

[0015]

According to the present invention, the thermal expansion coefficient at 40 to 400 ° C. is 8 to 25 ppm / ° C.
A semiconductor element having connection electrodes is mounted on the surface of a wiring board having an insulating substrate and a metallized wiring layer disposed on the surface of the insulating substrate, and the metallized wiring layer of the wiring board and the semiconductor A semiconductor element mounting wiring board obtained by brazing an element connection electrode and injecting and curing a filler containing at least a thermosetting resin between the wiring board and the semiconductor element; 40 to 4 after curing of the agent
A coefficient of thermal expansion at 00 ° C. of 20 to 50 ppm / ° C.,
A semiconductor element mounting substrate is provided, wherein the Young's modulus in the temperature range is 5 to 10 GPa.

In the semiconductor element-mounted wiring board of the present invention, the thermal stress generated by the difference between the thermal expansion coefficients of the semiconductor element, the wiring board and the brazing material has the thermal expansion coefficient and the Young's modulus. It is a remarkable feature that, by injecting and hardening a specific filler between the semiconductor element and the wiring substrate, the bonding portion is reinforced and the thermal stress is reduced and dispersed.

As a result, the concentration of stress generated in the semiconductor element and the wiring board is avoided, and no poor connection is caused between the semiconductor element and the wiring board, and a strong electrical connection is reliably maintained for a long period of time. Thus, high reliability is ensured even for long-term use.

[0018]

BEST MODE FOR CARRYING OUT THE INVENTION The wiring substrate used in the present invention and the insulating substrate of the package for accommodating a semiconductor element are 40
8 to 25 ppm /
° C, and especially the Young's modulus at 40 to 400 ° C is 20
An insulating substrate made of a sintered ceramic having a strength of 0 GPa or less is preferable, and the Young's modulus is more preferably 150 GPa or less.

Examples of such a sintered body include lithium silicate glass, PbO glass, ZnO, and the like as described in the specification of Japanese Patent Application No. 8-322038.
Enstatite, forsterite, forsterite and SiO ₂
System filler, MgO, ZrO _2, and mixed various ceramic filler such as petalite, obtained by firing 40-4
A sintered body having a thermal expansion coefficient of 8 to 18 ppm / ° C. at 00 ° C. can be exemplified.

Particularly preferred sintered bodies are Li ₂ O
Molded product containing 20 to 80% by volume of lithium silicate glass having a deformation point of 400 to 800 ° C. and containing forsterite and quartz or forstrite and cristobalite in an amount of 20 to 80% by volume. And a sintered body obtained by baking.

This sintered body can not only produce a homogeneous product relatively easily with good reproducibility, but also as a glass component.
By using the lithium silicate glass containing 5 to 30% by weight of Li ₂ O, a lithium silicate having a high coefficient of thermal expansion (for example, Li ₂ SiO ₃ ) is obtained in the sintered body after sintering.
Can be deposited, the yield point is relatively low, and low-temperature sintering is possible even with a small amount of glass.
This is advantageous because it can be fired simultaneously with the metallized wiring layer made of u, Ag or the like.

Further, when the deformation point of the lithium silicate glass used is 400 to 800 ° C., the glass content can be reduced, the filler amount can be increased, and the firing shrinkage starting temperature can be raised. . Thereby,
It is possible to efficiently remove a molding binder such as an organic resin added at the time of molding, and to match the sintering conditions of the insulator and the metallized layer to be co-fired.

The filler containing at least the thermosetting resin used in the present invention may be 40 to 4 after the thermosetting resin has been cured.
Coefficient of thermal expansion at 00 ° C is 20 to 50 ppm / ° C
And the Young's modulus in the same temperature range is 5 to 10 GP
There is no particular limitation as long as it has a value in the range of a. Examples of suitable resins to be incorporated into the filler include, for example, phenolic resins, urea resins, melamine resins, epoxy resins, unsaturated polyester resins, diallyl phthalate resins, polyimide resins, silicone resins, polyurethane resins, and the like. I can do it.

Among them, epoxy resins such as bisphenol epoxy resin, phenol novolak epoxy resin, cresol novolak epoxy resin, brominated epoxy resin and alicyclic epoxy resin are particularly preferable.

In the present invention, specific examples of particularly preferred curable resins include phenol novolak type epoxy resins and cresol novolak type epoxy resins.

Further, in order to control the Young's modulus and the coefficient of thermal expansion of the filler within the above-mentioned ranges, the thermosetting resin must first be mixed with an inorganic substance such as quartz glass, alumina, mica, zirconium silicate, lithium silicate or the like. Is adjusted by mixing 50 to 300 parts by weight with respect to 100 parts by weight of the resin.

Hereinafter, a semiconductor-mounted wiring board according to the present invention will be described in detail with reference to the accompanying drawings. FIG. 1 is a view showing an example of the present invention, which is based on a so-called wiring board having a metallized wiring layer disposed on the surface or inside of an insulating substrate. As BGA
3 shows a mounting structure when a type package is used.

In FIG. 1, A is a semiconductor device, B is BG
It is an A type package. The package B includes an insulating substrate 1, a metallized wiring layer 2, and connection terminals 3. On the other hand, the semiconductor element A is made of a Si material, and a connection electrode 4 is formed on a lower surface thereof.

A semiconductor element A is mounted on the BGA type package B.
2, a connection electrode (solder bump) 4 made of solder of the semiconductor element A is mounted on the land 5 of the metallized wiring layer 2 on the upper surface of the insulating substrate 1 of the package B as shown in the enlarged view of the main part of FIG. Place and contact, then about 250 to 40
Heating at a temperature of 0 ° C. to melt the solder bumps and join the connection electrodes 4 of the semiconductor element A to the land portions 5 of the wiring board B;
Implemented.

Thereafter, in order to reinforce the joint, a filler 6 containing a thermosetting resin is injected between the semiconductor element A and the BGA type package B and cured at a temperature of about 100 to 200 ° C.

According to the present invention, in the mounting structure as shown in FIG.
~ 50ppm / ℃ and Young's modulus is 5 ~ 10GPa
It is particularly important that

The thermal expansion coefficient of this filler is 20 ppm / ° C.
If the temperature is lower, the thermal expansion and shrinkage at high or low temperature are too small to compress the connection terminal and generate high stress. Also, 50p
If it exceeds pm / ° C., on the contrary, the thermal expansion and contraction at high and low temperatures is too large, and similarly high stress is generated in the connection terminals.

If the Young's modulus is lower than 5 GPa, the stress deformation of the filler is too large, and the reinforcement of the connection terminal is insufficient. If it is higher than 10 GPa, the deformation is too small to absorb the distortion due to the difference in thermal expansion with the connection terminal. I can't do it.

In the present invention, as described above, the insulating substrate for forming the wiring substrate has a Young's modulus of 200 GPa or less and a coefficient of thermal expansion at 40 to 400 ° C. of 8 to 25 ppm / ° C. Is more preferred.

In FIG. 1, the semiconductor element A mounted on the surface of the wiring board B is hermetically sealed by a lid (not shown). By using an insulating substrate having such Young's modulus and coefficient of thermal expansion in combination with the filler, the generated thermal stress can be absorbed by the bending and distortion of the insulating substrate, and the coefficient of thermal expansion can be reduced by the connection terminal and the thermosetting. The thermal stress itself generated by being closer to that of the conductive resin can be reduced.

From this viewpoint, in the present invention, the above-mentioned Li ₂ O is used as an insulating substrate material in an amount of 5 to 30% by weight.
It is particularly preferable to use a glass-ceramic sintered body obtained by shaping a mixture comprising 20 to 80% by volume of a crystalline lithium silicate glass to be contained and 20 to 80% by volume of a filler component containing at least forsterite and quartz, and firing the mixture. Furthermore, as crystalline lithium silicate glass,
It is preferable to use one having a yield point of 400 to 650 ° C.

[0037]

EXAMPLES For various ceramic materials shown in Table 1, 5
After preparing sintered bodies having a shape of × 4 × 40 mm, the Young's modulus and the coefficient of thermal expansion at 40 to 400 ° C. were measured for each sintered body. Table 1 shows the measured values.

Further, using various ceramic materials shown in Table 1, metallized wiring layers and through-holes made of copper are formed in these ceramic materials, and a large number of connection pads made of Cu metallized are formed on the upper surface of the substrate at locations connected to the through-holes. Was formed to produce a package wiring board. The thickness of all the wiring boards was 0.4 mm. On the other hand, a semiconductor element made of Si, having a coefficient of thermal expansion at 40 to 400 ° C. of 2.6 ppm / ° C. and having a solder bump formed on the bottom surface was prepared. Then, the solder bumps of the semiconductor element are aligned so that the connection pads of the package wiring board are connected to each other, and are heat-treated at 350 ° C. for 3 minutes in an N ₂ atmosphere to melt the solder bumps of the semiconductor element. This was connected to the connection pad of the wiring board.

After that, as shown in Table 2 between the semiconductor element and the wiring board.
The filler prepared by mixing quartz glass or alumina in the ratio shown in Table 2 with the thermosetting resin shown in Table 2 and kneading the mixture was injected, and cured at 180 ° C. for 2 hours in the atmosphere.

[0040]

[Table 1]

(Thermal Cycle Test) The semiconductor element mounted on the package substrate as described above was used as a test sample, and the test sample was placed in a thermostat controlled at -40 ° C. and 125 ° C. for 15 minutes each. This was kept as one cycle, and this cycle was repeated up to 1000 times.

Then, the electric resistance between the semiconductor element and the package substrate was measured for each cycle, and the number of cycles until the electric resistance changed was counted. Table 2 shows the results.

[0043]

[Table 2]

As apparent from Table 1, the filler has a coefficient of thermal expansion of 20 to 50 ppm / ° C. and a Young's modulus of 5 to 10
GPa, that is, a sample No. 4, 5, 9, 1
At 0, 16, 17, 21 and 22, no change in electric resistance was observed between the semiconductor element and the package substrate in the thermal cycle test up to 1000 times, and an extremely stable and good electric connection was obtained. maintain. Samples outside the above range, no.
1, 2, 3, 6, 7, 8, 11, 12, 13, 14, 1
In 5, 18, 19, 20, 23 and 24 (samples outside the scope of the present invention), a resistance change was detected in less than 1000 cycles,
It turns out that the reliability after mounting is lacking.

[0045]

As described above, according to the semiconductor element mounting circuit board of the present invention, when a semiconductor element is mounted on a wiring board, stress generation due to a difference in thermal expansion coefficient between the two is reduced. Element and wiring board accurate for a long time,
In addition, it is possible to make a strong electrical connection.

[Brief description of the drawings]

FIG. 1 shows a ball grid array (BG) according to the present invention.
Sectional drawing for demonstrating the mounting structure of the semiconductor element storage package of A type.

FIG. 2 is an enlarged view of a main part of the mounting structure of FIG. 1;

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 insulating substrate 2 metallized wiring layer 3 connection terminal 4 connection electrode (solder bump) 5 land 6 resin layer 7 external electric circuit board A semiconductor element B BGA type package

Continuing from the front page (72) Inventor Masaya Kokubu 1-4 Yamashita-cho, Kokubu-shi, Kagoshima Prefecture Inside Kyocera Research Institute (72) Inventor Yasuhide Minami 1-4 Yamashita-cho, Kokubu-shi, Kagoshima Kyocera Corporation (56) References JP-A-2-110949 (JP, A) JP-A-3-224245 (JP, A) JP-A-8-298269 (JP, A) (58) Fields investigated (Int. . ^7, DB name) H01L 21/56 H01L 21/60 H01L 23/12

Claims (2)

(57) [Claims] An electrode for connection is provided on a surface of a wiring board including an insulating substrate having a thermal expansion coefficient of 8 to 25 ppm / ° C. at 40 to 400 ° C. and a metallized wiring layer disposed on the surface of the insulating substrate. Is mounted, a metallized wiring layer of the wiring substrate and a connection electrode of the semiconductor device are brazed, and at least a thermosetting resin is provided between the wiring substrate and the semiconductor device. What is claimed is: 1. A semiconductor element-mounted wiring board obtained by injecting and curing a filler, wherein said filler has a coefficient of thermal expansion at 40 to 400 ° C. of 20 after curing.
A semiconductor element mounting wiring board, wherein the Young's modulus in the temperature range is 5 to 10 GPa. 2. The wiring board according to claim 1, wherein the thermosetting resin is one of a phenol novolak type epoxy resin and a cresol novolak type epoxy resin.