JPH11162973A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH11162973A JPH11162973A JP9327608A JP32760897A JPH11162973A JP H11162973 A JPH11162973 A JP H11162973A JP 9327608 A JP9327608 A JP 9327608A JP 32760897 A JP32760897 A JP 32760897A JP H11162973 A JPH11162973 A JP H11162973A
- Authority
- JP
- Japan
- Prior art keywords
- ion implantation
- ions
- implanted
- implantation step
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 39
- 238000004519 manufacturing process Methods 0.000 title claims description 27
- 150000002500 ions Chemical class 0.000 claims abstract description 34
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 34
- 239000010703 silicon Substances 0.000 claims abstract description 34
- 239000000758 substrate Substances 0.000 claims abstract description 32
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 31
- 238000000034 method Methods 0.000 claims abstract description 20
- 238000007254 oxidation reaction Methods 0.000 claims abstract description 20
- 238000005468 ion implantation Methods 0.000 claims description 43
- 230000003647 oxidation Effects 0.000 claims description 18
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 12
- 239000007789 gas Substances 0.000 claims description 8
- 229910052760 oxygen Inorganic materials 0.000 claims description 8
- 239000001301 oxygen Substances 0.000 claims description 8
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 7
- 229910052736 halogen Inorganic materials 0.000 claims description 7
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 6
- 229910052801 chlorine Inorganic materials 0.000 claims description 6
- 239000000460 chlorine Substances 0.000 claims description 6
- 229910052731 fluorine Inorganic materials 0.000 claims description 6
- 239000011737 fluorine Substances 0.000 claims description 6
- 229910052743 krypton Inorganic materials 0.000 claims description 6
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 claims description 6
- 229910052724 xenon Inorganic materials 0.000 claims description 6
- FHNFHKCVQCLJFQ-UHFFFAOYSA-N xenon atom Chemical compound [Xe] FHNFHKCVQCLJFQ-UHFFFAOYSA-N 0.000 claims description 6
- 150000002367 halogens Chemical class 0.000 claims description 4
- PXGOKWXKJXAPGV-UHFFFAOYSA-N Fluorine Chemical compound FF PXGOKWXKJXAPGV-UHFFFAOYSA-N 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 12
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052681 coesite Inorganic materials 0.000 abstract 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 229910052682 stishovite Inorganic materials 0.000 abstract 2
- 229910052905 tridymite Inorganic materials 0.000 abstract 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 28
- 229910052757 nitrogen Inorganic materials 0.000 description 14
- 229910004298 SiO 2 Inorganic materials 0.000 description 13
- -1 silicon ions Chemical class 0.000 description 7
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- 230000002411 adverse Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 2
- 238000010586 diagram Methods 0.000 description 1
- 238000005204 segregation Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/823462—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02123—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon
- H01L21/02164—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing silicon the material being a silicon oxide, e.g. SiO2
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66015—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene
- H01L29/66037—Multistep manufacturing processes of devices having a semiconductor body comprising semiconducting carbon, e.g. diamond, diamond-like carbon, graphene the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66045—Field-effect transistors
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- General Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- High Energy & Nuclear Physics (AREA)
- Toxicology (AREA)
- Health & Medical Sciences (AREA)
- Ceramic Engineering (AREA)
- Formation Of Insulating Films (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、本発明は同一基板
上に複数の膜厚のゲート酸化膜を有するＭＯＳ型半導体
装置の製造方法に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a MOS type semiconductor device having a plurality of gate oxide films on the same substrate.
【０００２】[0002]
【従来の技術】ＭＯＳ型半導体集積回路装置の駆動速度
を高速化するために、電源電圧を低くし、ＭＯＳＦＥＴ
のゲート酸化膜を薄膜化することが進められている。し
かし、一つの装置内で多種の電源電圧をもつ半導体集積
回路装置を混用せざるをえないために、ＭＯＳ型半導体
集積回路装置への外部からの入力信号の電圧が、電源電
圧よりも高い場合があり、信頼性の面から、入力信号を
受けるＭＯＳＦＥＴのゲート酸化膜は薄膜化することは
できない。したがって、同一基板上に複数の膜厚のゲー
ト酸化膜を形成する必要がある。2. Description of the Related Art In order to increase the driving speed of a MOS type semiconductor integrated circuit device, a power supply voltage is reduced and MOSFETs are reduced.
The thickness of the gate oxide film has been reduced. However, in order to inevitably mix semiconductor integrated circuit devices having various power supply voltages in one device, when a voltage of an external input signal to the MOS type semiconductor integrated circuit device is higher than the power supply voltage. Therefore, from the viewpoint of reliability, the gate oxide film of the MOSFET receiving the input signal cannot be reduced in thickness. Therefore, it is necessary to form a plurality of gate oxide films on the same substrate.
【０００３】従来、このような同一基板上に複数の膜厚
のゲート酸化膿を形成する方法として、特開昭５８−５
４６３８号公報等に記載されている方法が知られてい
る。即ち、この方法では、半導体基板上に選択的に窒素
又は窒素を含むイオン注入を行い、イオン注入を行った
領域の熱酸化速度を遅くすることで同一基板上に複数の
膜厚のゲート酸化膜を形成している。Conventionally, a method for forming a plurality of gate oxide punishes on the same substrate has been disclosed in Japanese Patent Application Laid-Open No. 58-5 / 1983.
A method described in Japanese Patent No. 4638 is known. That is, in this method, nitrogen or ion containing nitrogen is selectively implanted on a semiconductor substrate, and a thermal oxidation rate in a region where the ion implantation is performed is reduced, so that a gate oxide film having a plurality of film thicknesses is formed on the same substrate. Is formed.
【０００４】この従来の半導体装置の製造方法の一実施
例を図を用いて説明する。同一基板上に複数の膜厚のゲ
ート酸化膜を形成する従来の半導体装置の製造方法の工
程を図２（ａ）〜（ｄ）に示す。図２（ａ）に示すよう
にシリコン基板２０上にホトレジスト２２でパターンを
形成し、窒素又は窒素を含むイオンを選択的にイオン注
入する。次いでホトレジスト２２を除去した後、熱酸化
を行う。この際に注入された窒素がシリコン表面に偏析
し、酸化を抑止する。このために窒素又は窒素を含むイ
オンの注入領域２４と未注入領域とでシリコンの酸化速
度に差ができ、図２（ｂ）のようにＳｉＯ2 膜２６の厚
みの異なる領域を同時に形成することができる。次いで
図２（ｃ）のようにＳｉＯ2 膜２６上に多結晶シリコン
膜２８を成長し、パターンを形成後、これをマスクとし
てＳｉＯ2 膜２６をエッチングすることによって図２
（ｄ）に示すような異なるＳｉＯ2 膜厚のＭＯＳＦＥＴ
のゲート酸化膜を同時に形成する。An embodiment of this conventional method for manufacturing a semiconductor device will be described with reference to the drawings. 2A to 2D show steps of a conventional method for manufacturing a semiconductor device in which a gate oxide film having a plurality of film thicknesses is formed on the same substrate. As shown in FIG. 2A, a pattern is formed on a silicon substrate 20 with a photoresist 22, and nitrogen or ions containing nitrogen are selectively implanted. Next, after removing the photoresist 22, thermal oxidation is performed. At this time, the implanted nitrogen segregates on the silicon surface and suppresses oxidation. For this reason, there is a difference in the oxidation rate of silicon between the implanted region 24 and the non-implanted region of nitrogen or ions containing nitrogen, and regions having different thicknesses of the SiO 2 film 26 as shown in FIG. Can be. Next, as shown in FIG. 2C, a polycrystalline silicon film 28 is grown on the SiO 2 film 26, a pattern is formed, and the SiO 2 film 26 is etched using the pattern as a mask.
MOSFETs with different SiO 2 film thickness as shown in (d)
Are simultaneously formed.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、従来の
方法では注入された窒素がシリコン表面に偏析する、す
なわち、薄いゲート酸化膜厚のＭＯＳＦＥＴのゲートの
シリコン基板と酸化膜の界面に窒素が偏析するために、
ＭＯＳＦＥＴのチャネルの移動度が減少し、オン状態で
の電流が流れにくくなり、ＭＯＳ型半導体集積回路装置
の駆動速度を遅くするという問題が生じる。ゲート酸化
膜の薄膜化は、ＭＯＳＦＥＴのオン状態での電流を大き
くするために行っているのであるから、ゲートのシリコ
ン基板と酸化膜の界面に窒素が偏析することで薄いゲー
ト酸化膜厚のＭＯＳＦＥＴのチャネルの移動度が減少
し、オン状態での電流が流れにくくなることは致命的な
問題である。However, in the conventional method, the implanted nitrogen segregates on the silicon surface, that is, nitrogen segregates at the interface between the silicon substrate and the oxide film of the MOSFET gate having a thin gate oxide film. for,
There is a problem that the mobility of the channel of the MOSFET decreases, the current in the ON state becomes difficult to flow, and the driving speed of the MOS semiconductor integrated circuit device is reduced. Since the thinning of the gate oxide film is performed in order to increase the current in the ON state of the MOSFET, a MOSFET having a thin gate oxide film is formed by segregation of nitrogen at the interface between the gate silicon substrate and the oxide film. It is a fatal problem that the mobility of the channel decreases and the current does not easily flow in the ON state.
【０００６】さらに、半導体素子の微細化がすすむにつ
れて、ゲート酸化膜厚がますます薄膜化するが従来の方
法では、基板上で最も薄いゲート酸化膜厚のＭＯＳＦＥ
Ｔのゲートのシリコン基板と酸化膜の界面に窒素が偏析
することとなり、強固なゲート酸化膜を形成することが
難しく、信頼性の面からも問題である。前記の問題は、
窒素でない別の元素をシリコン表面に偏析させ熱酸化速
度を遅くすることで同一基板上に複数の膜厚のゲート酸
化膜を形成する場合にも問題となる。[0006] Further, as the size of the semiconductor device is further reduced, the thickness of the gate oxide film is becoming thinner and thinner.
Nitrogen segregates at the interface between the silicon substrate and the oxide film of the T gate, and it is difficult to form a strong gate oxide film, which is a problem in terms of reliability. The above problem is
Another problem arises when a gate oxide film having a plurality of film thicknesses is formed on the same substrate by segregating another element other than nitrogen on the silicon surface to reduce the thermal oxidation rate.
【０００７】本発明は、複数の膜厚のゲート酸化膜のＭ
ＯＳＦＥＴを有する半導体装置において、ＭＯＳ型半導
体集積回路装置の駆動速度を遅くすることなく、信頼性
を確保し、同一基板上に複数の膜厚のゲート酸化膜を形
成する方法を提供することを目的とする。According to the present invention, a plurality of gate oxide films having different thicknesses are formed.
An object of the present invention is to provide a method for forming a gate oxide film having a plurality of film thicknesses on the same substrate while ensuring reliability without reducing the driving speed of a MOS semiconductor integrated circuit device in a semiconductor device having an OSFET. And
【０００８】[0008]
【課題を解決するための手段】本発明によれば、シリコ
ン基板上に選択的に、熱酸化速度を速くするためのイオ
ン注入を行い同一基板上に複数の膜厚の酸化膜を形成す
ることを特徴とする半導体装置の製造方法が得られる。According to the present invention, a plurality of oxide films are formed on the same substrate by selectively performing ion implantation on the silicon substrate to increase the thermal oxidation rate. Thus, a method for manufacturing a semiconductor device characterized by the following is obtained.
【０００９】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンが酸素又は酸素を含ん
だものであることを特徴とする半導体装置の製造方法が
得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized in that the ions to be implanted in the ion implantation step include oxygen or oxygen.
【００１０】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンがシリコン又はシリコ
ンを含んだものであることを特徴とする半導体装置の製
造方法が得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized in that the ions to be implanted in the ion implantation step are silicon or silicon-containing ions.
【００１１】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンが希ガス又は希ガスを
含んだものであることを特徴とする半導体装置の製造方
法が得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized in that the ions to be implanted in the ion implantation step are a rare gas or a gas containing a rare gas.
【００１２】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンがアルゴン又はアルゴ
ンを含んだものであることを特徴とする半導体装置の製
造方法が得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized in that the ions to be implanted in the ion implantation step include argon or argon.
【００１３】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンがクリプトン又はクリ
プトンを含んだものであることを特徴とする半導体装置
の製造方法が得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized in that the ions to be implanted in the ion implantation step include krypton or krypton.
【００１４】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンがキセノン又はキセノ
ンを含んだものであることを特徴とする半導体装置の製
造方法が得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein in the ion implantation step, ions to be implanted include xenon or xenon.
【００１５】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンがハロゲン又はハロゲ
ンを含んだものであることを特徴とする半導体装置の製
造方法が得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, characterized in that the ions to be implanted in the ion implantation step are halogen or halogen-containing ions.
【００１６】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンがフッ素又はフッ素を
含んだものであることを特徴とする半導体装置の製造方
法が得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein in the ion implantation step, ions to be implanted are fluorine or fluorine-containing ions.
【００１７】さらに、本発明によれば、前記イオン注入
工程において、注入されるイオンが塩素又は塩素を含ん
だものであることを特徴とする半導体装置の製造方法が
得られる。Further, according to the present invention, there is provided a method of manufacturing a semiconductor device, wherein in the ion implantation step, ions to be implanted are chlorine or chlorine-containing ions.
【００１８】さらに、本発明によれば、前記イオン注入
工程において、イオン注入のドーズ量が１×１０16〜１
×１０17であることを特徴とする半導体装置の製造方法
が得られる。Further, according to the present invention, in the ion implantation step, the ion implantation dose is 1 × 10 16 to 1 × 10 16.
× 10 17 is obtained.
【００１９】さらに、本発明によれば、前記イオン注入
工程において、イオン注入のドーズ量が１×１０15〜１
×１０16であることを特徴とする半導体装置の製造方法
が得られる。Further, according to the present invention, in the ion implantation step, the ion implantation dose is 1 × 10 15 to 1 × 10 15.
A method for manufacturing a semiconductor device characterized by × 10 16 is obtained.
【００２０】さらに、本発明によれば、前記イオン注入
工程において、イオン注入のドーズ量が１×１０15〜１
×１０16であることを特徴とする半導体装置の製造方法
が得られる。Further, according to the present invention, in the ion implantation step, the ion implantation dose is 1 × 10 15 to 1 × 10 15.
A method for manufacturing a semiconductor device characterized by × 10 16 is obtained.
【００２１】さらに、本発明によれば、前記イオン注入
工程において、イオン注入のドーズ量が１×１０14〜１
×１０15であることを特徴とする半導体装置の製造方法
が得られる。Further, according to the present invention, in the ion implantation step, the ion implantation dose is 1 × 10 14 -1.
× 10 15 is obtained.
【００２２】[0022]
【作用】本発明では、シリコン基板上に選択的に、熱酸
化速度を速くするためのイオン注入を行い同一基板上に
複数の膜厚の酸化膜を形成する。この注入されたイオン
は、酸素、シリコンイオンの場合はいうまでもないが、
希ガス、ハロゲンイオンの場合も熱酸化中に拡散してし
まい、シリコン基板と酸化膜の界面に残らないために、
厚いゲート酸化膜厚のＭＯＳＦＥＴに悪影響をもたらさ
ない。According to the present invention, a plurality of oxide films are formed on the same substrate by selectively performing ion implantation on the silicon substrate to increase the thermal oxidation rate. The implanted ions are, of course, oxygen and silicon ions,
Rare gas and halogen ions also diffuse during thermal oxidation and do not remain at the interface between the silicon substrate and the oxide film.
It does not adversely affect MOSFETs with a large gate oxide thickness.
【００２３】薄いゲート酸化膜厚のＭＯＳＦＥＴは、こ
のイオン注入が行われていない領域であるから、もちろ
ん、チャネルの移動度の減少はなく、オン状態で電流が
流れにくくなることもないため、ＭＯＳ型半導体集積回
路装置の駆動速度を遅くする問題もなく、また、ゲート
のシリコン基板と酸化膜の界面に窒素が偏析することも
ないので、強固なゲート酸化膜が形成できる。すなわ
ち、本発明では、ＭＯＳ型半導体集積回路装置の駆動速
度を遅くすることも信頼性劣化の問題もなく、複数の膜
厚のゲート酸化膜のＭＯＳＦＥＴを有する半導体装置を
形成することができる。Since the MOSFET having a small gate oxide film thickness is a region where the ion implantation is not performed, the mobility of the channel does not decrease and the current does not easily flow in the ON state. There is no problem of lowering the driving speed of the semiconductor integrated circuit device, and no nitrogen segregates at the interface between the gate silicon substrate and the oxide film, so that a strong gate oxide film can be formed. That is, according to the present invention, it is possible to form a semiconductor device having a MOSFET having a gate oxide film with a plurality of film thicknesses without slowing down the driving speed of the MOS type semiconductor integrated circuit device and without deteriorating reliability.
【００２４】[0024]
【発明の実施の形態】以下、本発明に係る半導体装置の
製造方法の実施の形態について図１を参照して説明す
る。シリコン基板１０上にホトレジスト１２でパターン
を形成し、熱酸化速度を速くするためのイオンを選択的
に注入する。次いでホトレジスト１２を除去した後、熱
酸化を行う。この際にイオンが注入されたシリコン表面
は、熱酸化速度が速く、イオン注入領域１４と未注入領
域とでシリコンの酸化速度に差ができ、ＳｉＯ2 膜１６
の厚みの異なる領域を同時に形成することができる。次
いで、ＳｉＯ2 膜１６上に多結晶シリコン膜１８を成長
し、パターンを形成することによって異なるＳｉＯ2 膜
厚のＭＯＳＦＥＴのゲート酸化膜を同時に形成する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a method for manufacturing a semiconductor device according to the present invention will be described below with reference to FIG. A pattern is formed on the silicon substrate 10 with a photoresist 12, and ions for increasing the thermal oxidation rate are selectively implanted. Next, after removing the photoresist 12, thermal oxidation is performed. In this case silicon surface ions are implanted into the fast thermal oxidation rate can difference in oxidation rate of the silicon in the non-implanted region and the ion-implanted region 14, SiO 2 film 16
Regions having different thicknesses can be formed simultaneously. Next, a polycrystalline silicon film 18 is grown on the SiO 2 film 16 and a pattern is formed to simultaneously form gate oxide films of MOSFETs having different SiO 2 film thicknesses.
【００２５】[0025]
【実施例】以下、本発明の第１の実施例について説明す
る。図１（ａ）に示すようにシリコン基板１０上にホト
レジスト１２でパターンを形成し、酸素イオンを選択的
に、例えばドーズ量１×１０16〜１×１０17ｃｍ-2イオ
ン注入する。次いでホトレジスト１２を除去した後、熱
酸化を行う。この際に酸素が注入されたシリコン表面
は、熱酸化速度が速く、イオン注入領域１４と未注入領
域とでシリコンの酸化速度に差ができ、図１（ｂ）のよ
うにＳｉＯ2 膜１６の厚みの異なる領域を同時に形成す
ることができる。次いで図１（ｃ）のようにＳｉＯ2 膜
１６上に多結晶シリコン膜１８を成長し、パターンを形
成することによって図１（ｄ）に示すような異なるＳｉ
Ｏ2 膜厚のＭＯＳＦＥＴのゲート酸化膜を同時に形成す
る。The first embodiment of the present invention will be described below. As shown in FIG. 1A, a pattern is formed on a silicon substrate 10 with a photoresist 12, and oxygen ions are selectively implanted, for example, at a dose of 1 × 10 16 to 1 × 10 17 cm −2 . Next, after removing the photoresist 12, thermal oxidation is performed. At this time the silicon surface oxygen is injected, the fast thermal oxidation rate can difference in oxidation rate of the silicon in the non-implanted region and the ion implanted region 14, FIG. 1 of the SiO 2 film 16 as shown in (b) Regions having different thicknesses can be formed simultaneously. Next, as shown in FIG. 1C, a polycrystalline silicon film 18 is grown on the SiO 2 film 16 and a pattern is formed to form a different Si film as shown in FIG.
A gate oxide film of a MOSFET having an O 2 film thickness is simultaneously formed.
【００２６】次に、本発明の第２の実施例について説明
する。図１（ａ）に示すようにシリコン基板１０上にホ
トレジスト１２でパターンを形成し、シリコンイオンを
選択的に、例えばドーズ量１×１０15〜１×１０16ｃｍ
-2イオン注入する。その後、第１の製造方法と同様にし
て、図１（ｄ）に示すような異なるＳｉＯ2 膜厚のＭＯ
ＳＦＥＴのゲート酸化膜を同時に形成する。Next, a second embodiment of the present invention will be described. As shown in FIG. 1A, a pattern is formed on a silicon substrate 10 with a photoresist 12, and silicon ions are selectively applied, for example, at a dose of 1 × 10 15 to 1 × 10 16 cm.
-2 ion implantation. Thereafter, in the same manner as in the first manufacturing method, MOs having different SiO 2 film thicknesses as shown in FIG.
A gate oxide film of the SFET is formed at the same time.
【００２７】次に、本発明の第３の実施例について説明
する。図１（ａ）に示すようにシリコン基板１０上にホ
トレジスト１２でパターンを形成し、希ガスイオンを選
択的に、例えばドーズ量１×１０15〜１×１０16ｃｍ-2
イオン注入する。その後、第１の製造方法と同様にし
て、図１（ｄ）に示すような異なるＳｉＯ2 膜厚のＭＯ
ＳＦＥＴのゲート酸化膜を同時に形成する。Next, a third embodiment of the present invention will be described. As shown in FIG. 1A, a pattern is formed on a silicon substrate 10 with a photoresist 12, and rare gas ions are selectively applied, for example, at a dose of 1 × 10 15 to 1 × 10 16 cm −2.
Ions are implanted. Thereafter, in the same manner as in the first manufacturing method, MOs having different SiO 2 film thicknesses as shown in FIG.
A gate oxide film of the SFET is formed at the same time.
【００２８】次に、本発明の第４の実施例について説明
する。図１（ａ）に示すようにシリコン基板１０上にホ
トレジスト１２でパターンを形成し、ハロゲンイオンを
選択的に、例えばドーズ量１×１０14〜１×１０15ｃｍ
-2イオン注入する。その後、第１の製造方法と同様にし
て、図１（ｄ）に示すような異なるＳｉＯ2 膜厚のＭＯ
ＳＦＥＴのゲート酸化膜を同時に形成する。Next, a fourth embodiment of the present invention will be described. As shown in FIG. 1A, a pattern is formed on a silicon substrate 10 with a photoresist 12, and halogen ions are selectively formed, for example, at a dose of 1 × 10 14 to 1 × 10 15 cm.
-2 ion implantation. Thereafter, in the same manner as in the first manufacturing method, MOs having different SiO 2 film thicknesses as shown in FIG.
A gate oxide film of the SFET is simultaneously formed.
【００２９】イオン注入工程において、前記イオンのイ
オン種は上記以外に、アルゴン又はアルゴンを含んだも
の、クリプトン又はクリプトンを含んだもの、キセノン
又はキセノンを含んだもの、フッ素又はフッ素を含んだ
もの、塩素又は塩素を含んだものであってもよい。In the ion implantation step, the ionic species of the ions other than those described above are argon or argon-containing, krypton or krypton-containing, xenon or xenon-containing, fluorine or fluorine-containing, It may contain chlorine or chlorine.
【００３０】[0030]
【発明の効果】本発明によれば、シリコン基板上に選択
的に、熱酸化速度を速くするためのイオン注入を行い、
同一基板上に複数の膜厚の酸化膜を形成するが、この注
入されたイオンは、酸素、シリコンイオンの場合はいう
までもないが、希ガス、ハロゲンイオンの場合も熱酸化
中に拡散してしまい、シリコン基板と酸化膜の界面に残
らないために、厚いゲート酸化膜厚のＭＯＳＦＥＴに悪
影響をもたらさない。According to the present invention, ion implantation for selectively increasing the thermal oxidation rate is performed on a silicon substrate,
An oxide film having a plurality of film thicknesses is formed on the same substrate. The implanted ions, not to mention oxygen and silicon ions, but also rare gas and halogen ions diffuse during thermal oxidation. Since it does not remain at the interface between the silicon substrate and the oxide film, it does not adversely affect the MOSFET having a large gate oxide film thickness.
【００３１】薄いゲート酸化膜厚のＭＯＳＦＥＴは、こ
のイオン注入が行なわれていない領域であるから、もち
ろん、チャネルの移動度の減少はなく、オン状態で電流
が流れにくくなることもないため、ＭＯＳ型半導体集積
回路装置の駆動速度を遅くする問題もなく、また、ゲー
トのシリコン基板と酸化膜の界面に窒素が偏析すること
もないので、強固なゲート酸化膜が形成できる。すなわ
ち、本発明では、ＭＯＳ型半導体集積回路装置の駆動速
度を遅くすることも信頼性劣化の問題もなく、複数の膜
厚のゲート酸化膜のＭＯＳＦＥＴを有する半導体装置を
形成することができる。Since the MOSFET having a small gate oxide film thickness is a region where the ion implantation is not performed, the mobility of the channel does not decrease and the current does not easily flow in the ON state. There is no problem of lowering the driving speed of the semiconductor integrated circuit device, and no nitrogen segregates at the interface between the gate silicon substrate and the oxide film, so that a strong gate oxide film can be formed. That is, according to the present invention, it is possible to form a semiconductor device having a MOSFET having a gate oxide film with a plurality of film thicknesses without slowing down the driving speed of the MOS type semiconductor integrated circuit device and without deteriorating reliability.
【図１】本発明に係る半導体装置の製造方法の工程を示
した図である。FIG. 1 is a view showing steps of a method for manufacturing a semiconductor device according to the present invention.
【図２】従来の半導体装置の製造方法の工程を示した図
である。FIG. 2 is a diagram showing steps of a conventional method for manufacturing a semiconductor device.
１０ シリコン基板 １２ ホトレジスト １４ イオン注入領域 １６ ＳｉＯ2 膜 １８ 多結晶シリコン膜10 a silicon substrate 12 photoresist 14 ion-implanted region 16 SiO 2 film 18 a polycrystalline silicon film
Claims (14)
を速くするためのイオン注入を行い同一基板上に複数の
膜厚の酸化膜を形成することを特徴とする半導体装置の
製造方法。1. A method for manufacturing a semiconductor device, comprising: ion-implanting a silicon substrate to selectively increase a thermal oxidation rate; and forming oxide films having a plurality of film thicknesses on the same substrate.
るイオンが酸素又は酸素を含んだものであることを特徴
とする請求項１記載の半導体装置の製造方法。2. The method according to claim 1, wherein the ions to be implanted in the ion implantation step include oxygen or oxygen.
るイオンがシリコン又はシリコンを含んだものであるこ
とを特徴とする請求項１記載の半導体装置の製造方法。3. The method according to claim 1, wherein the ions to be implanted in the ion implantation step include silicon or silicon.
るイオンが希ガス又は希ガスを含んだものであることを
特徴とする請求項１記載の半導体装置の製造方法。4. The method of manufacturing a semiconductor device according to claim 1, wherein in the ion implantation step, ions to be implanted include a rare gas or a rare gas.
るイオンがアルゴン又はアルゴンを含んだものであるこ
とを特徴とする請求項１記載の半導体装置の製造方法。5. The method according to claim 1, wherein in the ion implantation step, the ions to be implanted include argon or argon.
るイオンがクリプトン又はクリプトンを含んだものであ
ることを特徴とする請求項１記載の半導体装置の製造方
法。6. The method according to claim 1, wherein the ions to be implanted in the ion implantation step include krypton or krypton.
るイオンがキセノン又はキセノンを含んだものであるこ
とを特徴とする請求項１記載の半導体装置の製造方法。7. The method of manufacturing a semiconductor device according to claim 1, wherein the ions to be implanted in the ion implantation step include xenon or xenon.
るイオンがハロゲン又はハロゲンを含んだものであるこ
とを特徴とする請求項１記載の半導体装置の製造方法。8. The method according to claim 1, wherein the ions to be implanted in the ion implantation step include halogen or halogen.
るイオンがフッ素又はフッ素を含んだものであることを
特徴とする請求項１記載の半導体装置の製造方法。9. The method of manufacturing a semiconductor device according to claim 1, wherein the ions to be implanted in the ion implantation step include fluorine or fluorine.
れるイオンが塩素又は塩素を含んだものであることを特
徴とする請求項１記載の半導体装置の製造方法。10. The method according to claim 1, wherein the ions to be implanted in the ion implantation step include chlorine or chlorine.
注入のドーズ量が１×１０16〜１×１０17であることを
特徴とする請求項２記載の半導体装置の製造方法。11. The method according to claim 2, wherein in the ion implantation step, a dose of the ion implantation is 1 × 10 16 to 1 × 10 17 .
注入のドーズ量が１×１０15〜１×１０16であることを
特徴とする請求項３記載の半導体装置の製造方法12. The method according to claim 3, wherein in the ion implantation step, a dose of the ion implantation is 1 × 10 15 to 1 × 10 16.
注入のドーズ量が１×１０15〜１×１０16であることを
特徴とする請求項４記載の半導体装置の製造方法。13. The method of manufacturing a semiconductor device according to claim 4, wherein in the ion implantation step, a dose of the ion implantation is 1 × 10 15 to 1 × 10 16 .
注入のドーズ量が１×１０14〜１×１０15であることを
特徴とする請求項８記載の半導体装置の製造方法。14. The method according to claim 8, wherein in the ion implantation step, a dose amount of the ion implantation is 1 × 10 14 to 1 × 10 15 .
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9327608A JPH11162973A (en) | 1997-11-28 | 1997-11-28 | Manufacture of semiconductor device |
| KR1019980051392A KR19990045667A (en) | 1997-11-28 | 1998-11-27 | Manufacturing Method of Semiconductor Device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP9327608A JPH11162973A (en) | 1997-11-28 | 1997-11-28 | Manufacture of semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH11162973A true JPH11162973A (en) | 1999-06-18 |
Family
ID=18200966
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP9327608A Pending JPH11162973A (en) | 1997-11-28 | 1997-11-28 | Manufacture of semiconductor device |
Country Status (2)
| Country | Link |
|---|---|
| JP (1) | JPH11162973A (en) |
| KR (1) | KR19990045667A (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2001244345A (en) * | 2000-02-29 | 2001-09-07 | Fujitsu Ltd | Method for fabricating semiconductor device |
| JP2001351989A (en) * | 2000-06-05 | 2001-12-21 | Nec Corp | Manufacturing method of semiconductor device |
| WO2002005335A1 (en) * | 2000-07-10 | 2002-01-17 | Shin-Etsu Handotai Co.,Ltd. | Single crystal wafer and solar battery cell |
| KR20020014055A (en) * | 2000-08-16 | 2002-02-25 | 박종섭 | Method for formining gate oxide layers in semiconductor device |
| US6388504B1 (en) | 1999-09-17 | 2002-05-14 | Nec Corporation | Integrated circuit device with switching between active mode and standby mode controlled by digital circuit |
| JP2006222151A (en) * | 2005-02-08 | 2006-08-24 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| JP2009218267A (en) * | 2008-03-07 | 2009-09-24 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device |
| JP2012089802A (en) * | 2010-10-22 | 2012-05-10 | Toyota Motor Corp | Manufacturing method of semiconductor device |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4105353B2 (en) * | 1999-07-26 | 2008-06-25 | 財団法人国際科学振興財団 | Semiconductor device |
-
1997
- 1997-11-28 JP JP9327608A patent/JPH11162973A/en active Pending
-
1998
- 1998-11-27 KR KR1019980051392A patent/KR19990045667A/en not_active Application Discontinuation
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6388504B1 (en) | 1999-09-17 | 2002-05-14 | Nec Corporation | Integrated circuit device with switching between active mode and standby mode controlled by digital circuit |
| US6664148B2 (en) | 1999-09-17 | 2003-12-16 | Nec Corporation | Integrated circuit device with switching between active mode and standby mode controlled by digital circuit |
| JP2001244345A (en) * | 2000-02-29 | 2001-09-07 | Fujitsu Ltd | Method for fabricating semiconductor device |
| JP2001351989A (en) * | 2000-06-05 | 2001-12-21 | Nec Corp | Manufacturing method of semiconductor device |
| US6853037B2 (en) | 2000-06-05 | 2005-02-08 | Nec Electronics Corporation | Fabrication of low power CMOS device with high reliability |
| WO2002005335A1 (en) * | 2000-07-10 | 2002-01-17 | Shin-Etsu Handotai Co.,Ltd. | Single crystal wafer and solar battery cell |
| KR100804247B1 (en) | 2000-07-10 | 2008-02-20 | 신에쯔 한도타이 가부시키가이샤 | Single crystal wafer and solar battery cell |
| US7459720B2 (en) * | 2000-07-10 | 2008-12-02 | Shin-Etsu Handotai Co., Ltd. | Single crystal wafer and solar battery cell |
| KR20020014055A (en) * | 2000-08-16 | 2002-02-25 | 박종섭 | Method for formining gate oxide layers in semiconductor device |
| JP2006222151A (en) * | 2005-02-08 | 2006-08-24 | Oki Electric Ind Co Ltd | Method for manufacturing semiconductor device |
| JP2009218267A (en) * | 2008-03-07 | 2009-09-24 | Fuji Electric Device Technology Co Ltd | Method of manufacturing semiconductor device |
| JP2012089802A (en) * | 2010-10-22 | 2012-05-10 | Toyota Motor Corp | Manufacturing method of semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| KR19990045667A (en) | 1999-06-25 |
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