JPH11150159A - Wiring board - Google Patents
Wiring boardInfo
- Publication number
- JPH11150159A JPH11150159A JP31879697A JP31879697A JPH11150159A JP H11150159 A JPH11150159 A JP H11150159A JP 31879697 A JP31879697 A JP 31879697A JP 31879697 A JP31879697 A JP 31879697A JP H11150159 A JPH11150159 A JP H11150159A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- printed wiring
- semiconductor chip
- electronic component
- mounting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
- Wire Bonding (AREA)
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】本発明はプリント配線板に関
し、例えば半導体チツプをフリツプチツプ実装するプリ
ント配線板に適用して好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed wiring board, and is suitably applied to, for example, a printed wiring board on which a semiconductor chip is flip-chip mounted.
【０００２】[0002]
【従来の技術】従来、半導体チツプをベアでプリント配
線板上に実装する実装方法の１つとしてフリツプチツプ
実装法がある。2. Description of the Related Art Conventionally, as one of mounting methods for mounting a semiconductor chip on a printed wiring board by bare, there is a flip chip mounting method.
【０００３】フリツプチツプ実装法は、図４（Ａ）に示
すように、半導体チツプ１の回路面に設けられた各電極
（以下、パツドと呼ぶ）２上にそれぞれ突起電極である
バンプ３を形成し、これら各バンプ３を図４（Ｂ）のよ
うにフエースダウンでそれぞれプリント配線板４の対応
する電極（以下、ランドと呼ぶ）５Ａと接合する実装方
法であり、半導体チツプ１を高密度で実装できる利点を
有している。In the flip-chip mounting method, as shown in FIG. 4A, bumps 3 which are projecting electrodes are formed on respective electrodes (hereinafter referred to as pads) 2 provided on a circuit surface of a semiconductor chip 1. This is a mounting method in which each of the bumps 3 is joined to the corresponding electrode (hereinafter, referred to as a land) 5A of the printed wiring board 4 face down as shown in FIG. 4B, and the semiconductor chip 1 is mounted at a high density. It has the advantages that it can.
【０００４】そしてこのようなフリツプチツプ実装法に
対応したプリント配線板４では、例えば図５に示すよう
に、半導体チツプ１の各バンプ３にそれぞれ対応させ
て、当該半導体チツプ１の回路面の対応する辺と垂直な
方向に引き出すように各配線ライン５Ｂが形成されると
共に、これら各配線ライン５Ｂの延長上に各ランド５Ａ
がそれぞれ形成されていた。In a printed wiring board 4 corresponding to such a flip-chip mounting method, for example, as shown in FIG. 5, the circuit surface of the semiconductor chip 1 corresponds to each bump 3 of the semiconductor chip 1. Each wiring line 5B is formed so as to extend in a direction perpendicular to the side, and each land 5A extends on an extension of each wiring line 5B.
Was formed respectively.
【０００５】[0005]
【発明が解決しようとする課題】ところでフリツプチツ
プ実装法において、半導体チツプ１の各バンプ３とプリ
ント配線板４の対応するランド５Ａとを接合する接合方
法の１つとして、半導体チツプ１の各バンプ３をプリン
ト配線板４の対応するランド５Ａ上に加熱及び加圧によ
り圧着させる方法がある。In the flip chip mounting method, one of the joining methods for joining each bump 3 of the semiconductor chip 1 and the corresponding land 5A of the printed wiring board 4 is as follows. On the corresponding land 5A of the printed wiring board 4 by heating and pressing.
【０００６】ところがこの接合方法によると、半導体チ
ツプ１を加熱及び加圧したときに図４（Ｂ）のプリント
配線板４のランド５Ａが当該半導体チツプ１のバンプ３
から受ける圧力によつて窪むことがあつた。However, according to this bonding method, when the semiconductor chip 1 is heated and pressed, the land 5A of the printed wiring board 4 shown in FIG.
Dents due to the pressure received from them.
【０００７】そしてこのようにプリント配線板４のラン
ド５Ａが窪んだ場合、当該プリント配線板４上に実装さ
れている第１の半導体チツプ１を新たな第２の半導体チ
ツプ１と交換（リペア）するリペア作業では、通常、第
２の半導体チツプ１が第１の半導体チツプ１とほぼ同じ
位置に位置決めされて実装されるために、第２の半導体
チツプ１の各バンプ３がプリント配線板４の対応するラ
ンド５Ａにおける窪んだ部位と同じ又はほぼ同じ部位上
に位置し、この結果この第２の半導体チツプ１の各バン
プ３を確実にプリント配線板４の対応するランド５Ａと
接合し得なくなることがあつた。そしてこのことは、リ
ペア実装時における実装の信頼性が低くなることを意味
する。When the land 5A of the printed wiring board 4 is depressed, the first semiconductor chip 1 mounted on the printed wiring board 4 is replaced with a new second semiconductor chip 1 (repair). In the repairing operation, since the second semiconductor chip 1 is usually positioned and mounted at substantially the same position as the first semiconductor chip 1, each bump 3 of the second semiconductor chip 1 is mounted on the printed wiring board 4. It is located on the same or almost the same portion as the depressed portion of the corresponding land 5A, so that each bump 3 of the second semiconductor chip 1 cannot be securely connected to the corresponding land 5A of the printed wiring board 4. There was. This means that the reliability of mounting at the time of repair mounting is reduced.
【０００８】本発明は以上の点を考慮してなされたもの
で、リペア実装時における実装の信頼性を向上させ得る
配線板を提案しようとするものである。The present invention has been made in view of the above points, and has as its object to propose a wiring board that can improve the reliability of mounting at the time of repair mounting.
【０００９】[0009]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、表面実装型電子部品の各突起電極
にそれぞれ対応させて複数の電極が形成された配線板に
おいて、各電極を互いに平行に形成するようにした。According to the present invention, there is provided a wiring board in which a plurality of electrodes are formed corresponding to the respective projecting electrodes of a surface-mounted electronic component. To be formed.
【００１０】この結果このプリント配線板では、表面実
装型電子部品をリペア実装する場合、元の表面実装型電
子部品が実装されていた位置から当該表面実装型電子部
品の各電極と平行な方向にずらして実装することがで
き、従つて例えば元の表面実装型電子部品を実装する際
に電極に窪みが形成された場合においても、当該窪みの
一部又は全部を避けて表面実装型電子部品の各突起電極
を対応する電極と接合することができる。[0010] As a result, in this printed wiring board, when the surface-mounted electronic component is repair-mounted, it is moved from the position where the original surface-mounted electronic component is mounted to a direction parallel to each electrode of the surface-mounted electronic component. Therefore, even if a dent is formed in the electrode when mounting the original surface-mounted electronic component, for example, a part or all of the dent is avoided and the surface-mounted electronic component can be mounted. Each protruding electrode can be joined to a corresponding electrode.
【００１１】[0011]
【発明の実施の形態】以下図面について、本発明の一実
施の形態を詳述する。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.
【００１２】図１（Ａ）及び（Ｂ）において、１０は全
体として本実施の形態によるプリント配線板を示し、絶
縁基板１１の一面１１Ａ上に、実装対象の半導体チツプ
１（図４（Ａ））の各バンプ３とそれぞれ対応させて導
体材料からなる複数のランド１２Ａが形成されると共
に、これら各ランド１２Ａのうちの対応するランド１２
Ａと導通するように複数の配線ライン１２Ｂが形成され
ている。1A and 1B, reference numeral 10 denotes a printed wiring board according to the present embodiment as a whole, and a semiconductor chip 1 to be mounted (see FIG. 4A) on one surface 11A of an insulating substrate 11. ), A plurality of lands 12A made of a conductive material are formed so as to correspond to the respective bumps 3, and the corresponding lands 12A of the lands 12A are formed.
A plurality of wiring lines 12B are formed so as to conduct with A.
【００１３】この場合各配線ライン１２Ｂは、図２
（Ａ）に示すように、それぞれ実装される半導体チツプ
１の回路面の対応する辺と垂直な方向（矢印ｘ方向又は
矢印ｙ方向）に引き出すように形成されており、また各
ランド１２Ａはそれぞれ対応する配線ライン１２Ｂに対
して例えば45〔°〕の配線角度θがつけられることによ
り互いに平行に形成されている。In this case, each wiring line 12B is
As shown in FIG. 1A, each of the lands 12A is formed so as to extend in a direction (an arrow x direction or an arrow y direction) perpendicular to the corresponding side of the circuit surface of the semiconductor chip 1 to be mounted. The wiring lines 12B are formed in parallel with each other by forming a wiring angle θ of 45 ° for example with respect to the corresponding wiring line 12B.
【００１４】これによりこのプリント配線板１０では、
半導体チツプ１の実装位置を、図２（Ｂ）において破線
で示す位置（半導体チツプ１の回路面の隣接する２辺に
沿つて形成された各バンプ３がそれぞれプリント配線板
１０の対応するランド１２Ａの矢印ｃ方向の後端部と対
向する位置）から、図２（Ｂ）において実線で示す位置
（半導体チツプ１の回路面の隣接する２辺に沿つて形成
された各バンプ３がそれぞれプリント配線板１０の対応
するランド１２Ａの矢印ｃ方向の前端部と対向する位
置）までの矢印ｃ方向の範囲内において自由に選定し得
るようになされている。As a result, in this printed wiring board 10,
The mounting position of the semiconductor chip 1 is indicated by a broken line in FIG. 2B (the bumps 3 formed along two adjacent sides of the circuit surface of the semiconductor chip 1 correspond to the corresponding lands 12A of the printed wiring board 10). 2B, the bumps 3 formed along two adjacent sides of the circuit surface of the semiconductor chip 1 are printed wiring lines, respectively, from the position facing the rear end in the direction of arrow c. The position can be freely selected within the range of the arrow c direction up to the position corresponding to the front end of the corresponding land 12A of the plate 10 in the arrow c direction).
【００１５】またこのときプリント配線板１０の各ラン
ド１２Ａの矢印ｃ方向の長さは、実装対象の半導体チツ
プ１のパツド２上に形成されるバンプ３の直径の２倍以
上の大きさに選定されている。At this time, the length of each land 12A of the printed wiring board 10 in the direction of the arrow c is selected to be at least twice as large as the diameter of the bump 3 formed on the pad 2 of the semiconductor chip 1 to be mounted. Have been.
【００１６】これによりこのプリント配線板１０では、
通常時、図２（Ｂ）において破線で示す位置に第１の半
導体チツプ１をフリツプチツプ実装し、当該第１の半導
体チツプ１をリペアする必要があるときには、同図にお
いて実線で示す位置に第２の半導体チツプ１′をリペア
実装するように第１及び第２の半導体チツプ１、１′の
実装位置を選定することによつて、図３のように第２の
半導体チツプ１′を、その各バンプ３′をプリント配線
板１０の対応するランド１２Ａに形成された窪み１２Ａ
Ｘを避けて当該ランド１２Ａと接合するようにプリント
配線板１０上に実装することができるようになされてい
る。Thus, in the printed wiring board 10,
Normally, the first semiconductor chip 1 is flip-chip mounted at the position shown by the broken line in FIG. 2B, and when it is necessary to repair the first semiconductor chip 1, the second semiconductor chip 1 is placed at the position shown by the solid line in FIG. By selecting the mounting positions of the first and second semiconductor chips 1, 1 'so as to repair the semiconductor chip 1', the second semiconductor chip 1 'as shown in FIG. The bumps 3 ′ are formed on the corresponding lands 12 A of the printed wiring board 10 by depressions 12 A.
It can be mounted on the printed wiring board 10 so as to be bonded to the land 12A while avoiding X.
【００１７】以上の構成において、このプリント配線板
１０上に実装された第１の半導体チツプ１を第２の半導
体チツプ１′に交換する場合、当該プリント配線板１０
上から第１の半導体チツプ１を除去した後、第２の半導
体チツプ１′を、第１の半導体チツプ１′の実装位置か
ら矢印ｃ方向に少なくともバンプ３の直径よりも大きい
距離だけ離れた位置に平行移動した状態に位置決めして
実装する。In the above configuration, when replacing the first semiconductor chip 1 mounted on the printed wiring board 10 with the second semiconductor chip 1 ', the printed wiring board 10
After removing the first semiconductor chip 1 from above, the second semiconductor chip 1 'is moved away from the mounting position of the first semiconductor chip 1' by at least a distance larger than the diameter of the bump 3 in the direction of arrow c. Is mounted in a state where it is moved in parallel to.
【００１８】この結果このプリント配線板１０では、第
１の半導体チツプ１のバンプ３によつて形成された窪み
１２ＡＸを確実に避けて、第２の半導体チツプ１′の各
バンプ３′をそれぞれ対応するランド１２Ａと接合する
ことができる。As a result, in this printed wiring board 10, the bumps 12AX formed by the bumps 3 of the first semiconductor chip 1 are surely avoided, and the bumps 3 'of the second semiconductor chip 1' correspond to each other. To the land 12A.
【００１９】従つてこのプリント配線板１０では、リペ
ア実装時における半導体チツプ１の各バンプ３と、プリ
ント配線板１０の対応するランド１２Ａとの間の接続不
良の発生を未然にかつ確実に回避することができる。Therefore, in the printed wiring board 10, the occurrence of connection failure between the bumps 3 of the semiconductor chip 1 and the corresponding lands 12A of the printed wiring board 10 during repair mounting is reliably and obviated. be able to.
【００２０】以上の構成によれば、プリント配線板１０
において、半導体チツプ１の各バンプ３とそれぞれ対応
する各ランド１２Ａを互いに平行に形成するようにした
ことにより、当該半導体チツプ１の実装位置に矢印ｃ方
向の範囲をもたせることができる。かくするにつきプリ
ント配線板１０の対応するランド１２Ａとの間の接続不
良の発生を未然にかつ確実に回避することができ、かく
してリペア実装時における実装の信頼性を向上させ得る
プリント配線板を実現できる。According to the above configuration, the printed wiring board 10
In the above, the lands 12A respectively corresponding to the bumps 3 of the semiconductor chip 1 are formed in parallel with each other, so that the mounting position of the semiconductor chip 1 can have a range in the direction of arrow c. As a result, a printed wiring board which can prevent the occurrence of a connection failure between the corresponding land 12A of the printed wiring board 10 and the above in advance and reliably and thus can improve the reliability of mounting at the time of repair mounting is realized. it can.
【００２１】なお上述の実施の形態においては、本発明
を半導体チツプ１をフリツプチツプ実装するプリント配
線板１０に適用するようにした場合について述べたが、
本発明はこれに限らず、要は、表面実装型電子部品の各
突起電極にそれぞれ対応させて複数の電極が形成され、
当該表面実装型電子部品が圧力をかけて実装されるこの
他種々の配線板に広く適用することがきる。In the above-described embodiment, a case has been described in which the present invention is applied to the printed wiring board 10 on which the semiconductor chip 1 is flip-chip mounted.
The present invention is not limited to this, in short, a plurality of electrodes are formed respectively corresponding to each protruding electrode of the surface mount electronic component,
It can be widely applied to various other wiring boards on which the surface-mounted electronic component is mounted under pressure.
【００２２】また上述の実施の形態においては、本発明
を単層のプリント配線板１０に適用するようにした場合
について述べたが、本発明はこれに限らず、多層の配線
板にも広く適用することができる。In the above-described embodiment, the case where the present invention is applied to a single-layer printed wiring board 10 has been described. However, the present invention is not limited to this, and is widely applied to a multilayer wiring board. can do.
【００２３】さらに上述の実施の形態においては、プリ
ント配線板１０の各ランド１２Ａの長さを半導体チツプ
１の各バンプ３の直径の２倍以上の長さに形成するよう
にした場合について述べたが、本発明はこれに限らず、
この他種々の長さを広く適用することができる。Further, in the above-described embodiment, the case where the length of each land 12A of the printed wiring board 10 is formed to be twice or more the diameter of each bump 3 of the semiconductor chip 1 has been described. However, the present invention is not limited to this,
In addition, various lengths can be widely applied.
【００２４】ただしこの場合、プリント配線板１０の各
ランド１２Ａの長さを、半導体チツプ１の各バンプ３の
うち、プリント配線板１０の各ランド１２Ａと接触する
先端部分の径の２倍よりも長く選定することによつて、
プリント配線板１０の各ランド１２Ａに形成された窪み
を確実に避けて半導体チツプ１の各バンプ３を当該プリ
ント配線板１０の対応するランド１２Ａと接合すること
ができるため、その分リペア実装の信頼性を確実に向上
させることができる。In this case, however, the length of each land 12A of the printed wiring board 10 is longer than twice the diameter of the tip portion of each bump 3 of the semiconductor chip 1 which comes into contact with each land 12A of the printed wiring board 10. By choosing for a long time,
Since the bumps 3 of the semiconductor chip 1 can be bonded to the corresponding lands 12A of the printed wiring board 10 by reliably avoiding the depressions formed in the lands 12A of the printed wiring board 10, the reliability of the repair mounting is accordingly increased. Properties can be reliably improved.
【００２５】またプリント配線板１０の各ランド１２Ａ
の長さを、半導体チツプ１の各バンプ３のうち、プリン
ト配線板１０の各ランド１２Ａと接触する先端部分の径
の２倍よりも極僅かに短く選定した場合においても、プ
リント配線板１０の各ランド１２Ａに形成された窪みの
ほとんどを避けて半導体チツプ１の各バンプ３を当該プ
リント配線板１０の対応するランド１２Ａと接合するこ
とができるため、リペア実装の信頼性をある程度向上さ
せることができる。Each land 12A of the printed wiring board 10
The length of the printed wiring board 10 is set to be slightly shorter than twice the diameter of the tip portion of each bump 3 of the semiconductor chip 1 which contacts the land 12A of the printed wiring board 10. Since the bumps 3 of the semiconductor chip 1 can be joined to the corresponding lands 12A of the printed wiring board 10 by avoiding most of the depressions formed in the lands 12A, the reliability of the repair mounting can be improved to some extent. it can.
【００２６】さらに上述の実施の形態においては、プリ
ント配線板１０の各ランド１２Ａにそれぞれ対応する配
線ライン１２Ｂに対して例えば45〔°〕の配線角度θを
つけるようにした場合について述べたが、本発明はこれ
に限らず、配線角度θとしてはこの他種々の値を広く適
用できる。ただしこの実施の形態のように配線角度を45
〔°〕とすることによつて、四方を囲むランド１２Ａ間
の干渉を少なくできる利点がある。Furthermore, in the above-described embodiment, a case has been described in which the wiring angle θ of, for example, 45 ° is provided to the wiring line 12B corresponding to each land 12A of the printed wiring board 10. The present invention is not limited to this, and various other values can be widely applied as the wiring angle θ. However, as in this embodiment, the wiring angle is 45
By setting [°], there is an advantage that interference between the lands 12A surrounding the four sides can be reduced.
【００２７】さらに上述の実施の形態においては、プリ
ント配線板１０の各ランド１２Ａに配線角度θをつける
ようにした場合について述べたが、本発明はこれに限ら
ず、各ランド１２Ａと共に各配線ライン１２Ｂをも矢印
ｃ方向に引き出すように形成（すなわち各配線ライン１
２Ｂを対応するランド１２Ａの延長方向に引き出すよう
に形成）するようにしても良い。Further, in the above-described embodiment, a case has been described in which the wiring angle θ is given to each land 12A of the printed wiring board 10. However, the present invention is not limited to this, and each land 12A and each wiring line 12B is also drawn out in the direction of arrow c (that is, each wiring line 1
2B may be formed so as to be drawn out in the extension direction of the corresponding land 12A).
【００２８】[0028]
【発明の効果】上述のように本発明によれば、表面実装
型電子部品の各突起電極にそれぞれ対応させて複数の電
極が形成された配線板において、各電極を互いに平行に
形成するようにしたことにより、表面実装型電子部品を
リペア実装する場合、新たな表面実装型電子部品を元の
表面実装型電子部品が実装されていた位置から配線板の
各電極と平行な方向にずらした位置に実装することがで
きる。かくするにつき元の表面実装型電子部品を実装す
る際に電極に窪みが形成された場合においても、当該窪
みの一部又は全部を避けて表面実装型電子部品の各突起
電極を対応する電極と接合することができ、かくしてリ
ペア実装時における実装の信頼性を向上させ得る配線板
を実現できる。As described above, according to the present invention, in a wiring board on which a plurality of electrodes are formed corresponding to the respective projecting electrodes of a surface mount type electronic component, the electrodes are formed in parallel with each other. As a result, when repairing a surface-mounted electronic component, a new surface-mounted electronic component is shifted from the position where the original surface-mounted electronic component was mounted in a direction parallel to each electrode of the wiring board. Can be implemented. Thus, even when a depression is formed in the electrode when mounting the original surface-mounted electronic component, each projecting electrode of the surface-mounted electronic component is avoided by avoiding part or all of the depression and the corresponding electrode. It is possible to realize a wiring board which can be joined and thus can improve the reliability of mounting at the time of repair mounting.
【図１】本実施の形態によるプリント配線板の構成を示
す平面図及びそのＸ−Ｘ′端面図である。FIG. 1 is a plan view showing a configuration of a printed wiring board according to the present embodiment and an XX ′ end view thereof.
【図２】本実施の形態によるプリント配線板への半導体
チツプの実装位置の説明に供する平面図である。FIG. 2 is a plan view for describing a mounting position of a semiconductor chip on a printed wiring board according to the present embodiment.
【図３】本実施の形態によるプリント配線板へのリペア
実装の説明に供する端面図である。FIG. 3 is an end view for explaining repair mounting on a printed wiring board according to the present embodiment;
【図４】フリツプチツプ実装法の説明に供する端面図で
ある。FIG. 4 is an end view for explaining a flip-chip mounting method;
【図５】従来のプリント配線板の説明に供する平面図で
ある。FIG. 5 is a plan view for explaining a conventional printed wiring board.
１……半導体チツプ、２……パツド、３……バンプ、１
０……プリント配線板、１１……絶縁基板、１２Ａ……
ランド、１２Ｂ……配線ライン。1 ... semiconductor chip, 2 ... pad, 3 ... bump, 1
0 ... printed wiring board, 11 ... insulating substrate, 12A ...
Land, 12B ... wiring line.
Claims (2)
れ対応させて複数の電極が形成された配線板において、 各上記電極が互いに平行に形成されたことを特徴とする
配線板。1. A wiring board in which a plurality of electrodes are formed corresponding to respective projecting electrodes of a surface mount electronic component, wherein the electrodes are formed in parallel with each other.
面実装型電子部品の上記突起電極のうち、上記電極と接
触する先端部分の直径の２倍以上の大きさに選定された
ことを特徴とする請求項１に記載の配線板。2. The method according to claim 1, wherein the length of each of the electrodes is selected to be at least twice as large as the diameter of the tip of the protruding electrode of the surface-mounted electronic component, which is in contact with the electrode. The wiring board according to claim 1, wherein:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31879697A JP3627895B2 (en) | 1997-11-19 | 1997-11-19 | Wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31879697A JP3627895B2 (en) | 1997-11-19 | 1997-11-19 | Wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH11150159A true JPH11150159A (en) | 1999-06-02 |
| JP3627895B2 JP3627895B2 (en) | 2005-03-09 |
Family
ID=18103049
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31879697A Expired - Fee Related JP3627895B2 (en) | 1997-11-19 | 1997-11-19 | Wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3627895B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184812A (en) * | 2000-12-15 | 2002-06-28 | Murata Mfg Co Ltd | Electronic component device |
| JP2010010611A (en) * | 2008-06-30 | 2010-01-14 | Toshiba Corp | Printed circuit board and electronic equipment |
-
1997
- 1997-11-19 JP JP31879697A patent/JP3627895B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2002184812A (en) * | 2000-12-15 | 2002-06-28 | Murata Mfg Co Ltd | Electronic component device |
| JP2010010611A (en) * | 2008-06-30 | 2010-01-14 | Toshiba Corp | Printed circuit board and electronic equipment |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3627895B2 (en) | 2005-03-09 |
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