JPH1187873A - Wiring board, manufacture thereof, and semiconductor device - Google Patents

Wiring board, manufacture thereof, and semiconductor device

Info

Publication number
JPH1187873A
JPH1187873A JP24323297A JP24323297A JPH1187873A JP H1187873 A JPH1187873 A JP H1187873A JP 24323297 A JP24323297 A JP 24323297A JP 24323297 A JP24323297 A JP 24323297A JP H1187873 A JPH1187873 A JP H1187873A
Authority
JP
Japan
Prior art keywords
electrode
semiconductor chip
insulating substrate
electrodes
interposer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP24323297A
Other languages
Japanese (ja)
Inventor
Takayuki Honda
位行 本多
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP24323297A priority Critical patent/JPH1187873A/en
Publication of JPH1187873A publication Critical patent/JPH1187873A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Abstract

PROBLEM TO BE SOLVED: To improve a working efficiency when a semiconductor chip is mounted on a mother board. SOLUTION: An insulting board 4 formed of transparent or semitransparent material, first electrodes 5 formed on the one surface of the insulating board 4 corresponding to a semiconductor chip 3, second electrodes 6 each formed on the one or other surface of the insulating board 4 corresponding to the first electrodes 5 and larger in inter-electrode pitch than the first electrodes 5, and conductor connecting means which connect the corresponding electrodes 5 and 6 together with a conductor are provided.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【目次】以下の順序で本発明を説明する。[Table of Contents] The present invention will be described in the following order.

【0002】発明の属する技術分野 従来の技術 発明が解決しようとする課題 課題を解決するための手段 発明の実施の形態 (1)第1の実施の形態(図1及び図2) (2)第2の実施の形態(図3及び図4) (3)他の実施の形態 発明の効果BACKGROUND OF THE INVENTION Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) First Embodiment (FIGS. 1 and 2) (2) Second Embodiment Second Embodiment (FIGS. 3 and 4) (3) Other Embodiments Effects of the Invention

【0003】[0003]

【発明の属する技術分野】本発明は配線板及びその製造
方法並びに半導体装置に関し、例えば電極間隔が狭ピツ
チ化された半導体チツプをマザー基板に実装する際に当
該半導体チツプのピツチ間隔を拡げる目的で用いる中間
基板及び当該中間基板に半導体チツプが実装されてなる
半導体装置に適用して好適なものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board, a method of manufacturing the same, and a semiconductor device, for example, for mounting a semiconductor chip having a narrow pitch between electrodes on a mother board, for expanding the pitch between the semiconductor chips. The present invention is suitably applied to an intermediate substrate to be used and a semiconductor device in which a semiconductor chip is mounted on the intermediate substrate.

【0004】[0004]

【従来の技術】従来、半導体チツプをマザー基板に実装
する実装方法の1つとしてフリツプチツプ実装法があ
る。
2. Description of the Related Art Conventionally, there is a flip chip mounting method as one of mounting methods for mounting a semiconductor chip on a mother board.

【0005】このフリツプチツプ実装法は、半導体チツ
プの回路面に設けられた各電極(以下、これをパツドと
呼ぶ)上にそれぞれ突起状電極でなるバンプを形成し、
当該半導体チツプをマザー基板の実装面上にフエースダ
ウンで直接実装する実装方法であり、半導体チツプを高
密度で実装することができる利点を有している。
In this flip-chip mounting method, bumps formed of projecting electrodes are formed on each electrode (hereinafter, referred to as a pad) provided on a circuit surface of a semiconductor chip.
This is a mounting method in which the semiconductor chip is directly mounted face down on the mounting surface of the mother board, and has an advantage that the semiconductor chip can be mounted at a high density.

【0006】ところが近年、エレクトロニクス機器は軽
薄短小傾向を強め、高機能集積化及び信号処理の高速化
が進んでおり、これに伴つて半導体チツプの電極間ピツ
チも益々狭ピツチ化が進んでいる。
In recent years, however, electronic devices have been becoming lighter, thinner and smaller, and high-performance integration and high-speed signal processing have been progressing. As a result, the pitch between electrodes of semiconductor chips has been increasingly narrow.

【0007】そしてこのような狭ピツチ化された半導体
チツプの各パツドに対応させてランド及び配線パターン
をマザー基板上に複数形成することは高度な技術を要
し、またコストアツプにもつながつていた。
Forming a plurality of lands and wiring patterns on a mother substrate in correspondence with each pad of such a narrow-pitch semiconductor chip requires a high level of technology and also leads to a cost increase. .

【0008】このため近年では、既存の実装技術を用い
て半導体チツプをマザー基板上に実装する方法として、
半導体チツプをインタポーザと呼ばれる中間基板を介し
てマザー基板上に実装する手法が拡く用いられている。
For this reason, in recent years, as a method of mounting a semiconductor chip on a mother board using an existing mounting technique,
2. Description of the Related Art A technique for mounting a semiconductor chip on a mother board via an intermediate board called an interposer has been widely used.

【0009】この場合インタポーザは、半導体チツプと
ほぼ同形状で1回り程度大きく形成されたガラスエポキ
シ樹脂やポリイミド等からなる絶縁基板の一面側に、半
導体チツプの各バンプと同じ位置関係で複数の第1の電
極が形成されると共に、絶縁基板の他面側(すなわち、
マザー基板の実装面と向かい合う側)に各第1の電極に
それぞれ対応させて第1の電極間ピツチよりも拡い間隔
で複数の第2の電極が形成され、これら対応する第1及
び第2の電極間が配線パターン及びスルーホールを順次
介して電気的に接続されることにより構成されている。
In this case, the interposer is formed on a surface of an insulating substrate made of glass epoxy resin, polyimide, or the like, which is substantially the same shape as the semiconductor chip and approximately one size larger, and has a plurality of first and second bumps in the same positional relationship as the semiconductor chips. One electrode is formed and the other side of the insulating substrate (ie,
On the side facing the mounting surface of the mother board), a plurality of second electrodes are formed at intervals larger than the pitch between the first electrodes so as to correspond to the first electrodes, respectively, and the corresponding first and second electrodes are formed. Are electrically connected via a wiring pattern and a through hole in order.

【0010】そしてこのインタポーザを用いた半導体チ
ツプのマザー基板への実装は、半導体チツプをインタポ
ーザの一面側にフリツプチツプ実装した後、当該インタ
ポーザをマザー基板上に実装することにより行われる。
The mounting of the semiconductor chip on the motherboard using the interposer is performed by mounting the semiconductor chip on one side of the interposer and then mounting the interposer on the motherboard.

【0011】従つてこのようなインタポーザを用いた方
法によれば、マザー基板の電極パターンをインタポーザ
の第2の電極の電極パターンに応じて形成すれば良い
分、マザー基板の電極間ピツチを拡くでき、その分容易
にかつ安価にマザー基板を形成し得る利点がある。
Therefore, according to the method using such an interposer, the pitch between the electrodes of the mother substrate is increased by the amount corresponding to forming the electrode pattern of the mother substrate in accordance with the electrode pattern of the second electrode of the interposer. Therefore, there is an advantage that the mother substrate can be formed easily and inexpensively.

【0012】[0012]

【発明が解決しようとする課題】ところでインタポーザ
を用いた半導体チツプの製造方法では、半導体チツプの
各バンプが回路面(すなわち底面)に設けられているた
め、半導体チツプをインタポーザにフリツプチツプ実装
した後、半導体チツプの各バンプとインタポーザの対応
する第1の電極との接合状態を外部から目視によつて確
認することができない。このためユーザは、回路に信号
を送つて1つ1つ確認することにより各接合部の導通状
態を検査しなければならず、作業効率が悪いという問題
があつた。
In a method of manufacturing a semiconductor chip using an interposer, since each bump of the semiconductor chip is provided on a circuit surface (that is, a bottom surface), the semiconductor chip is flip-chip mounted on the interposer. The bonding state between each bump of the semiconductor chip and the corresponding first electrode of the interposer cannot be visually confirmed from the outside. For this reason, the user has to check the conduction state of each joint by sending a signal to the circuit and confirming each one, and there is a problem that the working efficiency is poor.

【0013】本発明は以上の点を考慮してなされたもの
で、半導体チツプをマザー基板に実装する際の作業効率
を向上し得る配線板及びその製造方法並びに半導体装置
を提案しようとするものである。
The present invention has been made in view of the above points, and is intended to propose a wiring board, a method of manufacturing the same, and a semiconductor device capable of improving work efficiency when mounting a semiconductor chip on a mother board. is there.

【0014】[0014]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、透明又は半透明な材料を用いて形
成された絶縁基板と、当該絶縁基板の一面側に半導体チ
ツプの各電極にそれぞれ対応させて形成された複数の第
1の電極と、絶縁基板の一面側又は他面側に、各第1の
電極とそれぞれ対応させて第1の電極の電極間ピツチよ
りも拡い電極間ピツチで形成された第2の電極と、第1
及び第2の電極のうち対応するもの同士を導体接続する
導体接続手段とを設けるようにした。
According to the present invention, there is provided an insulating substrate formed using a transparent or translucent material, and an electrode of a semiconductor chip on one surface of the insulating substrate. A plurality of first electrodes formed in correspondence with each other, and an inter-electrode pitch wider than the inter-electrode pitch of the first electrodes on one surface side or the other surface side of the insulating substrate corresponding to each first electrode. A second electrode formed by
And a conductor connecting means for conducting a conductor connection between corresponding ones of the second electrodes.

【0015】これにより半導体チツプを配線板に実装し
た後の半導体チツプの各電極と絶縁基板に形成された第
1の電極との接合状態の検査を当該絶縁基板の透明さを
利用して目視によつて容易に確認することができる。
Thus, the inspection of the bonding state between each electrode of the semiconductor chip after the semiconductor chip is mounted on the wiring board and the first electrode formed on the insulating substrate is visually performed by utilizing the transparency of the insulating substrate. Therefore, it can be easily confirmed.

【0016】また透明又は半透明な材料を用いて形成さ
れた絶縁基板の一面側に半導体チツプの各電極にそれぞ
れ対応させて複数の第1の電極を形成すると共に、絶縁
基板の一面側又は他面側に各第1の電極とそれぞれ対応
させて第1の電極の電極間ピツチよりも拡い電極間ピツ
チで第2の電極を形成し、かつ第1及び第2の電極のう
ち対応するもの同士を導体接続する第1の工程と、絶縁
基板を所定温度に加熱した状態で当該絶縁基板の一面に
半導体チツプに応じた所定形状の治具を所定圧力及び所
定時間押し当てることにより、半導体チツプを収納する
凹部を形成する第2の工程とを設けるようにする。
Further, a plurality of first electrodes are formed on one surface of an insulating substrate formed using a transparent or translucent material, respectively, corresponding to the respective electrodes of the semiconductor chip. A second electrode is formed on the surface side with an inter-electrode pitch wider than the inter-electrode pitch of the first electrode corresponding to each first electrode, and the corresponding one of the first and second electrodes A first step of connecting the conductors to each other, and pressing a jig of a predetermined shape corresponding to the semiconductor chip against a surface of the insulating substrate in a state where the insulating substrate is heated to a predetermined temperature for a predetermined pressure and for a predetermined time to form a semiconductor chip. And a second step of forming a recess for accommodating therein.

【0017】これにより、上述の配線板を製造すること
ができるので、半導体チツプを配線板に実装した後の半
導体チツプの各電極と絶縁基板に形成された第1の電極
との接合状態の検査を当該絶縁基板の透明さを利用して
目視によつて容易に確認することができる。
Thus, the above-mentioned wiring board can be manufactured, and the inspection of the bonding state between each electrode of the semiconductor chip and the first electrode formed on the insulating substrate after the semiconductor chip is mounted on the wiring board. Can be easily confirmed visually using the transparency of the insulating substrate.

【0018】配線板の一面側に半導体チツプが実装され
てなる半導体装置において、配線板は、透明又は半透明
な材料を用いて形成された絶縁基板と、配線板の一面を
形成する絶縁基板の一面側に半導体チツプの各電極にそ
れぞれ対応させて形成された複数の第1の電極と、絶縁
基板の一面側又は他面側に各第1の電極とそれぞれ対応
させて第1の電極の電極間ピツチよりも拡い電極間ピツ
チで形成された第2の電極と、第1及び第2の電極のう
ち対応するもの同士を導体接続する導体接続手段とを設
けるようにする。
In a semiconductor device having a semiconductor chip mounted on one surface side of a wiring board, the wiring board includes an insulating substrate formed using a transparent or translucent material and an insulating substrate forming one surface of the wiring board. A plurality of first electrodes formed on one side corresponding to the respective electrodes of the semiconductor chip, and electrodes of the first electrodes corresponding to the respective first electrodes on one side or the other side of the insulating substrate. A second electrode formed by an inter-electrode pitch wider than the inter-electrode pitch and a conductor connecting means for electrically connecting corresponding ones of the first and second electrodes are provided.

【0019】これにより半導体チツプを配線板に実装し
た後の半導体チツプの各電極と絶縁基板に形成された第
1の電極との接合状態の検査を当該絶縁基板の透明さを
利用して目視によつて容易に確認した後、この半導体装
置をマザー基板に容易に実装することができる。
Thus, the bonding state between each electrode of the semiconductor chip and the first electrode formed on the insulating substrate after the semiconductor chip is mounted on the wiring board is visually inspected by utilizing the transparency of the insulating substrate. Thus, after easy confirmation, the semiconductor device can be easily mounted on the motherboard.

【0020】[0020]

【発明の実施の形態】以下図面について、本発明の一実
施の形態を詳述する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【0021】(1)第1の実施の形態 図1及び図2において、1は全体として第1の実施の形
態による半導体装置を示し、インタポーザ2に半導体チ
ツプ3がフリツプチツプ実装されている。
(1) First Embodiment In FIGS. 1 and 2, reference numeral 1 denotes a semiconductor device according to the first embodiment as a whole, and a semiconductor chip 3 is flip-chip mounted on an interposer 2.

【0022】この場合インタポーザ2は、絶縁基板4の
一面4A側に半導体チツプ3の各バンプ3Aとそれぞれ
対応させて複数の第1の電極5が形成されると共に、当
該絶縁基板4の他面4B側に第1の電極5とそれぞれ対
応させて第1の電極間ピツチ(例えば100[μm])よりも
拡いピツチ(例えば150[μm])で複数の第2の電極6が
形成され、これら第1の電極5及び第2の電極6のうち
の対応するもの同士が絶縁基板4の一面4A側に形成さ
れた配線パターン7とスルーホール8とを順次介して導
通接続されることにより構成されている。
In this case, in the interposer 2, a plurality of first electrodes 5 are formed on one surface 4A of the insulating substrate 4 in correspondence with the bumps 3A of the semiconductor chip 3, and the other surface 4B of the insulating substrate 4 is formed. A plurality of second electrodes 6 are formed on the sides with pitches (for example, 150 [μm]) wider than the first inter-electrode pitch (for example, 100 [μm]) corresponding to the first electrodes 5, respectively. Corresponding ones of the first electrode 5 and the second electrode 6 are electrically connected to each other via a wiring pattern 7 formed on the one surface 4A side of the insulating substrate 4 and a through hole 8 sequentially. ing.

【0023】また半導体チツプ3は、各電極上にそれぞ
れ形成されたバンプ3Aがインタポーザ2の絶縁基板4
の対応する第1の電極5と導通するように異方性導電接
着剤9を介して当該絶縁基板4の一面4A上に熱圧着さ
れている。
The semiconductor chip 3 has a bump 3A formed on each electrode and an insulating substrate 4 of the interposer 2.
The insulating substrate 4 is thermocompression-bonded via the anisotropic conductive adhesive 9 so as to be electrically connected to the corresponding first electrode 5.

【0024】これによりこの半導体装置1においては、
インタポーザ2の各第2の電極6上にそれぞれ形成され
る各バンプ10を外部電極として、これら各バンプ10
をそれぞれマザー基板11の対応するランド12と電気
的かつ物理的に接合するようにしてマザー基板11上に
実装できるようになされている。
As a result, in this semiconductor device 1,
Each of the bumps 10 formed on each of the second electrodes 6 of the interposer 2 is used as an external electrode.
Are electrically and physically bonded to the corresponding lands 12 of the motherboard 11 so that they can be mounted on the motherboard 11.

【0025】かかる構成に加えこの半導体装置1の場
合、インタポーザ2の絶縁基板4は透明なガラス材を用
いて形成されている。これによりこの半導体装置1にお
いては、半導体チツプ3のバンプ3Aとインタポーザ2
の第1の電極5との位置決めや接合状態の検査をインタ
ポーザ2を介して目視によつて行い得るようになされて
いる。
In addition to this configuration, in the case of the semiconductor device 1, the insulating substrate 4 of the interposer 2 is formed using a transparent glass material. Thereby, in the semiconductor device 1, the bump 3A of the semiconductor chip 3 and the interposer 2
The positioning with the first electrode 5 and the inspection of the bonding state can be visually performed via the interposer 2.

【0026】因みにこのようなインタポーザ2は、平板
状のガラス板からなる絶縁基板4の一面4A上に第1の
電極5及び配線パターン7を蒸着によつて形成した後、
当該配線パターン7の先端部分にドリルやレーザ等によ
る穴あけ処理を施し、内周面をめつき処理することによ
つてスルーホール8を形成し、他面4B上にスルーホー
ル8と導通接続した第2の電極6を形成することにより
製造することができる。
In the interposer 2, the first electrode 5 and the wiring pattern 7 are formed on one surface 4A of the insulating substrate 4 made of a flat glass plate by vapor deposition.
A drilling process is performed on the leading end portion of the wiring pattern 7 using a drill, a laser, or the like, and a through hole 8 is formed by plating the inner peripheral surface. The second hole 4 is electrically connected to the through hole 8 on the other surface 4B. It can be manufactured by forming two electrodes 6.

【0027】以上の構成において、この半導体装置1で
は、半導体チツプ3がインタポーザ2にフリツプチツプ
実装された後のこれら半導体チツプ3とインタポーザ2
との接合部分の状態を透明なガラス板からなるインタポ
ーザ2を介して目視により容易に確認することができ
る。
In the above configuration, in the semiconductor device 1, after the semiconductor chip 3 is flip-chip mounted on the interposer 2, the semiconductor chip 3 and the interposer 2 are mounted.
The state of the joint portion with can be easily visually confirmed via the interposer 2 made of a transparent glass plate.

【0028】従つてこの半導体装置1では、半導体チツ
プ3のバンプ3Aとインタポーザ2の対応する第1の電
極5との接合状態の検査を従来のように回路に信号を与
えて1つ1つ確認する場合に比べて格段的に簡易化する
ことができる。
Therefore, in the semiconductor device 1, the bonding state between the bump 3A of the semiconductor chip 3 and the corresponding first electrode 5 of the interposer 2 is inspected one by one by applying a signal to the circuit as in the prior art. This can be significantly simplified compared to the case where

【0029】またこの半導体装置1では、上述のように
インタポーザ2の絶縁基板4としてガラス板を用いる
分、従来のインタポーザのようにガラスエポキシ樹脂等
の絶縁性樹脂材からなる絶縁基板を用いる場合に比べて
絶縁基板4の表面の平坦度を高くすることができ、その
分半導体チツプ3とインタポーザ2との電気的導通を確
実にとることができることにより、電気的な接続不良を
低減させてインタポーザ2としての信頼性を向上させる
ことができる。
In the semiconductor device 1, the glass plate is used as the insulating substrate 4 of the interposer 2 as described above, so that the insulating substrate made of an insulating resin material such as a glass epoxy resin is used as in the conventional interposer. In comparison, the flatness of the surface of the insulating substrate 4 can be increased, and the electrical conduction between the semiconductor chip 3 and the interposer 2 can be ensured accordingly. Reliability can be improved.

【0030】さらにこの半導体装置1では、インタポー
ザ2の絶縁基板4がガラス材から形成されているため、
従来のインタポーザに比べて耐熱性が高く、この結果製
造時にインタポーザ2の第1の電極5及び配線パターン
7を蒸着法を用いて微細に形成することができる。従つ
て従来のインタポーザの絶縁基板に用いられたガラスエ
ポキシ樹脂のように露光によつて形成する場合に比べ
て、半導体チツプ3の電極間隔がより狭ピツチ化した場
合においても十分に対応することができる。
Further, in the semiconductor device 1, since the insulating substrate 4 of the interposer 2 is formed of a glass material,
The heat resistance is higher than that of the conventional interposer, and as a result, the first electrode 5 and the wiring pattern 7 of the interposer 2 can be finely formed by vapor deposition during manufacturing. Accordingly, it is possible to sufficiently cope with a case where the pitch between the electrodes of the semiconductor chip 3 is narrower than that in the case of forming by exposure such as glass epoxy resin used for the insulating substrate of the conventional interposer. it can.

【0031】以上の構成によれば、透明又は半透明な材
料を用いて形成された絶縁基板4の一面側に半導体チツ
プ3の各バンプ3Aにそれぞれ対応させて形成された複
数の第1の電極5と、絶縁基板4の他面側に各第1の電
極5とそれぞれ対応させて第1の電極5の電極間ピツチ
よりも拡い電極間ピツチで形成された第2の電極6と、
第1及び第2の電極5及び6のうち対応するもの同士を
導体接続する配線パターン7及びスルーホール8とが形
成されてなるインタポーザ2に半導体チツプ3をフリツ
プチツプ実装するようにしたことにより、半導体チツプ
3の各バンプ3Aとインタポーザ2の各第1の電極5と
の接合状態の検査を目視によつて容易に確認することが
でき、かくして半導体チツプ3をマザー基板11に実装
する際の作業効率を向上させ得る半導体装置1を実現で
きる。
According to the above configuration, the plurality of first electrodes formed on the one surface side of the insulating substrate 4 formed of a transparent or translucent material, respectively, correspond to the bumps 3A of the semiconductor chip 3. A second electrode 6 formed on the other surface of the insulating substrate 4 with an inter-electrode pitch wider than the inter-electrode pitch of the first electrode 5 corresponding to each first electrode 5;
The semiconductor chip 3 is flip-chip mounted on the interposer 2 in which a wiring pattern 7 and a through hole 8 for forming a conductor connection between corresponding ones of the first and second electrodes 5 and 6 are formed. Inspection of the bonding state between each bump 3A of the chip 3 and each first electrode 5 of the interposer 2 can be easily confirmed visually, and thus the work efficiency in mounting the semiconductor chip 3 on the mother substrate 11 can be confirmed. Semiconductor device 1 capable of improving the above can be realized.

【0032】(2)第2の実施の形態 図1との対応部分に同一符号を付して示す図3におい
て、20は全体として第2の実施の形態による半導体装
置を示し、インタポーザ21に半導体チツプ3が第1の
実施の形態とは反対向きの状態でフリツプチツプ実装さ
れている。
(2) Second Embodiment In FIG. 3, in which parts corresponding to those in FIG. 1 are assigned the same reference numerals, reference numeral 20 denotes a semiconductor device according to the second embodiment as a whole. The chip 3 is flip-chip mounted in a state opposite to that of the first embodiment.

【0033】この場合インタポーザ21は、半導体チツ
プ3より一回り大きな所定の大きさで形成された絶縁基
板22の一面側の中央部分に底面が半導体チツプ3の回
路面よりも僅かに大きく、かつバンプ3Aを含む半導体
チツプ3の厚みよりも僅かに深い大きさの凹部23が設
けられている。
In this case, the interposer 21 has a bottom surface slightly larger than the circuit surface of the semiconductor chip 3 at a central portion on one surface side of the insulating substrate 22 formed to have a predetermined size slightly larger than the semiconductor chip 3. A recess 23 having a size slightly deeper than the thickness of the semiconductor chip 3 including 3A is provided.

【0034】またこの絶縁基板22の凹部23の底面に
は、半導体チツプ3の各バンプ3Aとそれぞれ対応させ
て複数の第1の電極24が形成されると共に、当該絶縁
基板22の一面の周端部には第1の電極間ピツチ(例え
ば100[μm])よりも拡い電極間ピツチ(例えば150[μ
m])で複数の第2の電極25が形成され、これら第1の
電極24及び第2の電極25のうちの対応するもの同士
が絶縁基板22の一面に沿つて形成された配線パターン
26を介して導通接続されている。因みに、絶縁基板2
2の他面側には何も配されておらず、半導体装置20全
体の厚みが薄くなるように形成されている。
A plurality of first electrodes 24 are formed on the bottom surface of the concave portion 23 of the insulating substrate 22 so as to correspond to the bumps 3A of the semiconductor chip 3, respectively. In the portion, the inter-electrode pitch (for example, 150 [μm]) is wider than the first inter-electrode pitch (for example, 100 [μm]).
m]), a plurality of second electrodes 25 are formed, and the corresponding ones of the first electrode 24 and the second electrode 25 form a wiring pattern 26 formed along one surface of the insulating substrate 22. It is electrically connected through the switch. By the way, the insulating substrate 2
Nothing is arranged on the other surface side of the semiconductor device 2, and the semiconductor device 20 is formed so as to have a small thickness.

【0035】さらに半導体チツプ3は、各電極上にそれ
ぞれ形成されたバンプ3Aがインタポーザ21の絶縁基
板22の対応する第1の電極24と導通接続するように
異方性導電接着剤9を介して熱圧着されている。
Further, the semiconductor chip 3 is connected via the anisotropic conductive adhesive 9 such that the bumps 3A formed on the respective electrodes are electrically connected to the corresponding first electrodes 24 on the insulating substrate 22 of the interposer 21. Thermocompression bonded.

【0036】これによりこの半導体装置20において
は、インタポーザ21の各第2の電極25を外部電極と
して、これら各第2の電極25をそれぞれマザー基板1
1の対応するランド12と電気的かつ物理的に接合する
ようにしてマザー基板11上に実装できるようになされ
ている。
Thus, in this semiconductor device 20, each second electrode 25 of the interposer 21 is used as an external electrode, and each of the second electrodes 25 is
It can be mounted on the mother board 11 so as to be electrically and physically connected to one corresponding land 12.

【0037】さらにこの半導体装置20においては、マ
ザー基板11に実装される際に半導体チツプ3とマザー
基板11との間に放熱ゴム27を配置した状態で実装さ
れるようになされている。
Further, in the semiconductor device 20, when mounted on the mother substrate 11, the semiconductor device 20 is mounted with the heat radiation rubber 27 disposed between the semiconductor chip 3 and the mother substrate 11.

【0038】かかる構成に加えこの半導体装置20の場
合、インタポーザ21の絶縁基板22は透明なガラス材
を用いて形成されている。これにより半導体装置20に
おいては、半導体チツプ3のバンプ3Aとインタポーザ
21の第1の電極25との位置決めや接合状態の検査を
インタポーザ21を介して目視によつて行い得るように
なされている。
In addition to this configuration, in the case of the semiconductor device 20, the insulating substrate 22 of the interposer 21 is formed using a transparent glass material. Thus, in the semiconductor device 20, positioning of the bump 3A of the semiconductor chip 3 and the first electrode 25 of the interposer 21 and inspection of the bonding state can be visually performed via the interposer 21.

【0039】ここでこのような半導体装置20は、図4
(A)〜(D)に示す以下の手順により作製することが
できる。
Here, such a semiconductor device 20 corresponds to FIG.
It can be manufactured by the following procedures shown in (A) to (D).

【0040】すなわち図4(A)に示すように、所定の
大きさの平板状のガラス板(例えばソーダガラス)でな
る絶縁基板22の平坦な一面22A上に第1の電極24
と、第2の電極26と、第1及び第2の電極間を接続す
る配線パターン25とを蒸着法を用いて形成する。
That is, as shown in FIG. 4A, a first electrode 24 is formed on a flat surface 22A of an insulating substrate 22 made of a flat glass plate (for example, soda glass) having a predetermined size.
Then, a second electrode 26 and a wiring pattern 25 connecting between the first and second electrodes are formed by using an evaporation method.

【0041】次に図4(B)に示すように、第1の電極
24、第2の電極26及び配線パターン25の形成され
た絶縁基板22を所定温度(約500 度)に加熱した状態
で半導体チツプ3に応じた形状の治具Gを所定圧力及び
所定時間押し当てる。
Next, as shown in FIG. 4B, the insulating substrate 22 on which the first electrode 24, the second electrode 26, and the wiring pattern 25 are formed is heated to a predetermined temperature (about 500 degrees). A jig G having a shape corresponding to the semiconductor chip 3 is pressed at a predetermined pressure for a predetermined time.

【0042】続いて図4(C)に示すように、絶縁基板
22から治具Gを外した状態で所定時間放置することに
より冷却する。これにより半導体チツプ3を収納し得る
深さを持つ凹部23が形成され、半導体チツプ3を実装
したときにバンプ3Aのピツチ間隔よりも拡げられた第
2の電極26を持つインタポーザ21を作製することが
できる。
Subsequently, as shown in FIG. 4C, cooling is performed by leaving the jig G removed from the insulating substrate 22 for a predetermined time. As a result, a recess 23 having a depth capable of accommodating the semiconductor chip 3 is formed, and the interposer 21 having the second electrode 26 which is wider than the pitch between the bumps 3A when the semiconductor chip 3 is mounted is manufactured. Can be.

【0043】さらにこの後図4(D)に示すように、こ
うして形成されたインタポーザ21の凹部23の底面に
形成された第1の電極24と半導体チツプ3の各バンプ
3Aとを異方性導電接着剤9を介して電気的及び物理的
に接続する。これにより第2の電極25を介してマザー
基板11に容易に実装し得る半導体装置20を作製する
ことができる。
Thereafter, as shown in FIG. 4D, the first electrode 24 formed on the bottom surface of the recess 23 of the interposer 21 thus formed and each bump 3A of the semiconductor chip 3 are anisotropically conductive. Electrically and physically connected via an adhesive 9. Thereby, the semiconductor device 20 that can be easily mounted on the mother substrate 11 via the second electrode 25 can be manufactured.

【0044】以上の構成において、この半導体装置20
では、半導体チツプ3がインタポーザ21にフリツプチ
ツプ実装された後のこれら半導体チツプ3とインタポー
ザ21との接合部分の状態を透明なガラス板からなるイ
ンタポーザ21を介して目視によつて容易に確認するこ
とができる。
In the above configuration, the semiconductor device 20
Then, the state of the junction between the semiconductor chip 3 and the interposer 21 after the semiconductor chip 3 is flip-chip mounted on the interposer 21 can be easily visually confirmed via the interposer 21 made of a transparent glass plate. it can.

【0045】従つてこの半導体装置20では、半導体チ
ツプ3のバンプ3Aとインタポーザ21の対応する第1
の電極24との接合状態の検査を従来のように回路に信
号を与えて1つ1つ確認する場合に比べて格段的に簡易
化することができる。
Accordingly, in this semiconductor device 20, the bumps 3A of the semiconductor chip 3 and the corresponding first
Inspection of the bonding state with the electrode 24 can be significantly simplified as compared with the conventional case where a signal is applied to a circuit to check each one.

【0046】またこの半導体装置20では、インタポー
ザ21の絶縁基板22がガラス材から形成されているた
め、従来のインタポーザに比べて耐熱性が高く、この結
果製造時にインタポーザ21の第1の電極24、第2の
電極25及び配線パターン26を蒸着法を用いて形成す
ることができる。従つてこの半導体装置20では、従来
のインタポーザの絶縁基板に用いられたガラスエポキシ
樹脂のように露光によつて形成する場合と比べて半導体
チツプ3の電極間隔がより狭ピツチ化した場合にも十分
に対応することができる。
In the semiconductor device 20, since the insulating substrate 22 of the interposer 21 is formed of a glass material, the heat resistance is higher than that of the conventional interposer. As a result, the first electrode 24 of the interposer 21 is manufactured at the time of manufacture. The second electrode 25 and the wiring pattern 26 can be formed using an evaporation method. Therefore, in the semiconductor device 20, even when the pitch between the electrodes of the semiconductor chip 3 is narrower than in the case where the semiconductor chip 3 is formed by exposure, such as a glass epoxy resin used for an insulating substrate of a conventional interposer, it is sufficient. Can be handled.

【0047】さらにこの半導体装置20では、インタポ
ーザ21の絶縁基板22としてガラス板を用いる分、従
来のインタポーザのようにガラスエポキシ樹脂等の絶縁
性樹脂材からなる絶縁基板を用いる場合に比べて絶縁基
板22の表面の平坦度を高くすることができ、その分半
導体チツプ3とインタポーザ21との電気的導通を確実
にとることができることにより、電気的な接続不良を低
減させてインタポーザ21としての信頼性を向上させる
ことができる。
Further, in this semiconductor device 20, the use of a glass plate as the insulating substrate 22 of the interposer 21 makes the insulating substrate more insulated than the conventional interposer using an insulating substrate made of an insulating resin material such as glass epoxy resin. The flatness of the surface of the interposer 22 can be increased, and electrical conduction between the semiconductor chip 3 and the interposer 21 can be ensured by that much, so that poor electrical connection is reduced and the reliability of the interposer 21 is reduced. Can be improved.

【0048】さらにこの半導体装置20では、インタポ
ーザ21の絶縁基板22の表面に治具Gを押し当てるこ
とにより凹部23を形成し、当該凹部23に半導体チツ
プ3を実装して収納するようにしたことにより、マザー
基板11にインタポーザ21を実装したときに当該イン
タポーザ21によつて半導体チツプ3を保護することが
できる。
Further, in the semiconductor device 20, the concave portion 23 is formed by pressing the jig G against the surface of the insulating substrate 22 of the interposer 21, and the semiconductor chip 3 is mounted and stored in the concave portion 23. Accordingly, when the interposer 21 is mounted on the mother board 11, the semiconductor chip 3 can be protected by the interposer 21.

【0049】さらにこの半導体装置20では、インタポ
ーザ21の絶縁基板22の平坦な一面に第1の電極2
4、第2の電極25及び配線パターン26を形成し、治
具Gを押し当てることにより凹部23を形成するように
したことにより、半導体チツプ3をインタポーザ21に
実装したときに当該半導体チツプ3のバンプ3Aのピツ
チ間隔を第1の電極24、配線パターン26を介して接
続された第2の電極25によつて拡げることができ、か
くして第1の実施の形態のインタポーザ2のように絶縁
基板4にスルーホール8を形成して他面4B側に第2の
電極6を形成する工程を必要とせず、製造工程を簡素化
することができる。
Further, in this semiconductor device 20, the first electrode 2 is formed on one flat surface of the insulating substrate 22 of the interposer 21.
4. By forming the second electrode 25 and the wiring pattern 26 and pressing the jig G to form the concave portion 23, the semiconductor chip 3 is mounted on the interposer 21 when the semiconductor chip 3 is mounted on the interposer 21. The pitch interval between the bumps 3A can be expanded by the first electrode 24 and the second electrode 25 connected via the wiring pattern 26. Thus, the insulating substrate 4 can be extended like the interposer 2 of the first embodiment. In this case, there is no need for a step of forming the through-hole 8 and forming the second electrode 6 on the other surface 4B side, and the manufacturing process can be simplified.

【0050】さらにこの半導体装置20では、インタポ
ーザ21に半導体チツプ3を収納し得る凹部23を設
け、半導体チツプ3とマザー基板11との間に放熱ゴム
27を配置して実装するようにしたことにより、実装後
の半導体チツプ3を放熱ゴム27の弾性力によつて安定
させることができると共に、半導体チツプ3の熱を放熱
ゴム27を介してマザー基板11へ放熱することがで
き、回路の安定化を図ることができる。
Further, in this semiconductor device 20, the interposer 21 is provided with the concave portion 23 for accommodating the semiconductor chip 3, and the heat radiating rubber 27 is arranged between the semiconductor chip 3 and the mother substrate 11 for mounting. The semiconductor chip 3 after mounting can be stabilized by the elastic force of the heat radiation rubber 27, and the heat of the semiconductor chip 3 can be dissipated to the mother substrate 11 via the heat radiation rubber 27, thereby stabilizing the circuit. Can be achieved.

【0051】以上の構成によれば、透明又は半透明な材
料を用いて形成された絶縁基板22の一面側に半導体チ
ツプ3の各バンプ3Aにそれぞれ対応させて形成された
複数の第1の電極24と、絶縁基板22の一面側に各第
1の電極24とそれぞれ対応させて第1の電極24の電
極間ピツチよりも拡い電極間ピツチで形成された第2の
電極25と、第1及び第2の電極24及び25のうち対
応するもの同士を導体接続する配線パターン26とが形
成されてなるインタポーザ21に半導体チツプ3をフリ
ツプチツプ実装するようにしたことにより、半導体チツ
プ3の各バンプ3Aとインタポーザ21の各第1の電極
24との接合状態の検査を目視によつて容易に確認する
ことができ、かくして半導体チツプ3をマザー基板11
に実装する際の作業効率を向上させ得る半導体装置20
を実現することができる。
According to the above configuration, the plurality of first electrodes formed on the one surface side of the insulating substrate 22 formed using a transparent or translucent material, respectively, correspond to the bumps 3A of the semiconductor chip 3 respectively. 24, a second electrode 25 formed on one surface side of the insulating substrate 22 with an inter-electrode pitch wider than the inter-electrode pitch of the first electrode 24 corresponding to each of the first electrodes 24; Each of the bumps 3A of the semiconductor chip 3 is mounted by flip-chip mounting the semiconductor chip 3 on an interposer 21 in which a wiring pattern 26 for electrically connecting the corresponding one of the second electrodes 24 and 25 is formed. Inspection of the bonding state between the semiconductor chip 3 and each first electrode 24 of the interposer 21 can be easily confirmed visually, and thus the semiconductor chip 3 can be easily connected to the mother substrate 11.
Device 20 capable of improving work efficiency when mounting on semiconductor device 20
Can be realized.

【0052】(3)他の実施の形態 なお上述の第1及び第2の実施の形態においては、配線
板としてのインタポーザ2及び21の絶縁基板4及び2
2を透明なガラス板を用いて形成するようにした場合に
ついて述べたが、本発明はこれに限らず、半導体チツプ
3の各バンプ3Aとインタポーザ2及び21の各第1の
電極5及び24との接合状態を確認できれば、プラスチ
ツクや樹脂等の半透明部材を用いるようにしても良い。
この場合の製造方法は、ガラス基材のように加熱した状
態で治具Gを用いてプレスするのではなく、真空成形等
の種々の成形法により製造する。
(3) Other Embodiments In the first and second embodiments described above, the insulating substrates 4 and 2 of the interposers 2 and 21 as wiring boards are used.
2 has been described using a transparent glass plate, but the present invention is not limited to this, and each bump 3A of the semiconductor chip 3 and each of the first electrodes 5 and 24 of the interposers 2 and 21 are connected to each other. As long as the bonding state can be confirmed, a translucent member such as plastic or resin may be used.
In this case, the manufacturing method does not press the jig G in a heated state like a glass substrate, but manufactures by various forming methods such as vacuum forming.

【0053】また上述の第1及び第2の実施の形態にお
いては、半導体チツプ3のバンプ3Aとインタポーザ2
の第1の電極5や半導体チツプ3のバンプ3Aとインタ
ポーザ21の第1の電極24を異方性導電接着剤9を介
して熱圧着するようにした場合について述べたが、本発
明はこれに限らず、金材からなるワイヤを介して半導体
チツプ3のバンプ3Aとインタポーザ2及び21の第1
の電極5及び24とを導通接続する等、他の種々の方法
によつて半導体チツプ3をインタポーザ2及び21に実
装するようにしても良い。
In the first and second embodiments described above, the bump 3A of the semiconductor chip 3 and the interposer 2
Although the first electrode 5 or the bump 3A of the semiconductor chip 3 and the first electrode 24 of the interposer 21 are thermocompression-bonded via the anisotropic conductive adhesive 9, the present invention is not limited to this. The bumps 3A of the semiconductor chip 3 and the first of the interposers 2 and 21 are not limited to the above.
The semiconductor chip 3 may be mounted on the interposers 2 and 21 by other various methods such as conducting connection between the electrodes 5 and 24.

【0054】さらに上述の第1及び第2の実施の形態に
おいては、インタポーザ2及び21の絶縁基板4及び2
2の配線パターン7及び26を蒸着法を用いて形成する
ようにした場合について述べたが、本発明はこれに限ら
ず、半導体チツプ3とマザー基板11とを異方性導電接
着剤9を用いて実装する場合に、ニツケルめつきや金め
つきを用い、半導体チツプ3とマザー基板11とをはん
だを用いて実装する場合に半導体チツプ3との接続部で
ある第1の電極5にニツケルめつきや金めつきを用いる
と共に、マザー基板11との接続部である第2の電極6
に銅を用いるようにしても良い。
In the first and second embodiments, the insulating substrates 4 and 2 of the interposers 2 and 21 are used.
Although the case where the wiring patterns 7 and 26 of No. 2 are formed using the vapor deposition method has been described, the present invention is not limited to this, and the semiconductor chip 3 and the mother substrate 11 are formed using the anisotropic conductive adhesive 9. When mounting the semiconductor chip 3 and the mother board 11 using solder, the first electrode 5 which is a connection portion between the semiconductor chip 3 and the mother board 11 is used. And the second electrode 6 serving as a connection portion with the mother substrate 11.
You may make it use copper.

【0055】さらに上述の第2の実施の形態において
は、半導体チツプ3の熱を放熱させる放熱手段として放
熱ゴム27を用いるようにした場合について述べたが、
本発明はこれに限らず、要は半導体チツプ3の熱をマザ
ー基板11を介して放熱することができれば放熱樹脂等
の他の種々の放熱手段を用いるようにしても良い。
Further, in the above-described second embodiment, a case has been described in which the heat radiating rubber 27 is used as a heat radiating means for radiating the heat of the semiconductor chip 3.
The present invention is not limited to this. In other words, any other heat radiating means such as a heat radiating resin may be used as long as the heat of the semiconductor chip 3 can be radiated through the mother substrate 11.

【0056】さらに上述の第1及び第2の実施の形態に
おいては、導体接続手段として配線パターン7及びスル
ーホール8や配線パターン26を用いるようにした場合
について述べたが、本発明はこれに限らず、他の種々の
導体接続手段を用いるようにしても良い。
Further, in the above-described first and second embodiments, the case where the wiring pattern 7, the through hole 8, and the wiring pattern 26 are used as the conductor connecting means has been described, but the present invention is not limited to this. Instead, other various conductor connection means may be used.

【0057】[0057]

【発明の効果】上述のように本発明によれば、透明又は
半透明な材料を用いて形成された絶縁基板と、当該絶縁
基板の一面側に半導体チツプの各電極にそれぞれ対応さ
せて形成された複数の第1の電極と、絶縁基板の一面側
又は他面側に、各第1の電極とそれぞれ対応させて第1
の電極の電極間ピツチよりも拡い電極間ピツチで形成さ
れた第2の電極と、第1及び第2の電極のうち対応する
もの同士を導体接続する導体接続手段とを設けるように
したことにより、半導体チツプを配線板に実装した後の
半導体チツプの各電極と絶縁基板に形成された第1の電
極との接合状態の検査を当該絶縁基板の透明さを利用し
て目視によつて容易に確認することができ、かくして半
導体チツプをマザー基板に実装する際の作業効率を向上
させ得る配線板を実現できる。
As described above, according to the present invention, an insulating substrate formed using a transparent or translucent material, and one surface of the insulating substrate formed corresponding to each electrode of the semiconductor chip. A plurality of first electrodes and a first electrode corresponding to each first electrode on one surface side or the other surface side of the insulating substrate.
A second electrode formed with an inter-electrode pitch wider than the inter-electrode pitch of the first and second electrodes, and a conductor connection means for electrically connecting corresponding ones of the first and second electrodes. This makes it easy to visually inspect the bonding state between each electrode of the semiconductor chip and the first electrode formed on the insulating substrate after the semiconductor chip is mounted on the wiring board by utilizing the transparency of the insulating substrate. Thus, it is possible to realize a wiring board that can improve the working efficiency when mounting the semiconductor chip on the motherboard.

【0058】また透明又は半透明な材料を用いて形成さ
れた絶縁基板の一面側に半導体チツプの各電極にそれぞ
れ対応させて複数の第1の電極を形成すると共に、絶縁
基板の一面側又は他面側に各第1の電極とそれぞれ対応
させて第1の電極の電極間ピツチよりも拡い電極間ピツ
チで第2の電極を形成し、かつ第1及び第2の電極のう
ち対応するもの同士を導体接続する第1の工程と、絶縁
基板を所定温度に加熱した状態で当該絶縁基板の一面に
半導体チツプに応じた所定形状の治具を所定圧力及び所
定時間押し当てることにより、半導体チツプを収納する
凹部を形成する第2の工程とを設けるようにしたことに
より、上述の配線板を製造することができる。これによ
り、半導体チツプを配線板に実装した後の半導体チツプ
の各電極と絶縁基板に形成された第1の電極との接合状
態の検査を当該絶縁基板の透明さを利用して目視によつ
て容易に確認することができ、かくして半導体チツプを
マザー基板に実装する際の作業効率を向上させ得る配線
板の製造方法を実現できる。
Further, a plurality of first electrodes are formed on one surface of an insulating substrate formed using a transparent or translucent material, respectively, corresponding to each electrode of the semiconductor chip. A second electrode is formed on the surface side with an inter-electrode pitch wider than the inter-electrode pitch of the first electrode corresponding to each first electrode, and the corresponding one of the first and second electrodes A first step of connecting the conductors to each other, and pressing a jig of a predetermined shape corresponding to the semiconductor chip against a surface of the insulating substrate in a state where the insulating substrate is heated to a predetermined temperature for a predetermined pressure and for a predetermined time to form a semiconductor chip. The above-described wiring board can be manufactured by providing the second step of forming a concave portion for housing the wiring board. Thus, the bonding state between each electrode of the semiconductor chip and the first electrode formed on the insulating substrate after the semiconductor chip is mounted on the wiring board is visually inspected using the transparency of the insulating substrate. A method of manufacturing a wiring board which can be easily confirmed and thus can improve the working efficiency when mounting a semiconductor chip on a mother board can be realized.

【0059】配線板の一面側に半導体チツプが実装され
てなる半導体装置において、配線板は、透明又は半透明
な材料を用いて形成された絶縁基板と、配線板の一面を
形成する絶縁基板の一面側に半導体チツプの各電極にそ
れぞれ対応させて形成された複数の第1の電極と、絶縁
基板の一面側又は他面側に各第1の電極とそれぞれ対応
させて第1の電極の電極間ピツチよりも拡い電極間ピツ
チで形成された第2の電極と、第1及び第2の電極のう
ち対応するもの同士を導体接続する導体接続手段とを設
けるようにしたことにより、半導体チツプを配線板に実
装した後の半導体チツプの各電極と絶縁基板に形成され
た第1の電極との接合状態の検査を当該絶縁基板の透明
さを利用して目視によつて容易に確認した後、この半導
体装置をマザー基板に容易に実装することができる。
In a semiconductor device in which a semiconductor chip is mounted on one surface of a wiring board, the wiring board includes an insulating substrate formed using a transparent or translucent material and an insulating substrate forming one surface of the wiring board. A plurality of first electrodes formed on one side corresponding to the respective electrodes of the semiconductor chip, and electrodes of the first electrodes corresponding to the respective first electrodes on one side or the other side of the insulating substrate. A semiconductor chip is provided by providing a second electrode formed by an inter-electrode pitch wider than the inter-electrode pitch and a conductor connecting means for electrically connecting corresponding ones of the first and second electrodes. After the semiconductor chip is mounted on the wiring board and the inspection of the bonding state between each electrode of the semiconductor chip and the first electrode formed on the insulating substrate is easily confirmed visually by utilizing the transparency of the insulating substrate. This semiconductor device is It can be easily implemented in.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1の実施の形態による半導体装置の
構成を示す断面図である。
FIG. 1 is a sectional view showing a configuration of a semiconductor device according to a first embodiment of the present invention.

【図2】本発明の第1の実施の形態によるマザー基板に
実装された半導体装置を示す上面図である。
FIG. 2 is a top view showing the semiconductor device mounted on the motherboard according to the first embodiment of the present invention.

【図3】本発明の第2の実施の形態による半導体装置の
構成を示す断面図である。
FIG. 3 is a sectional view showing a configuration of a semiconductor device according to a second embodiment of the present invention.

【図4】本発明の第2の実施の形態によるインタポーザ
の製造方法を示す略線図である。
FIG. 4 is a schematic diagram illustrating a method of manufacturing an interposer according to a second embodiment of the present invention.

【符号の説明】[Explanation of symbols]

1、20……半導体装置、2、21……インタポーザ、
3……半導体チツプ、3A……バンプ、4、24……第
1の電極、6、26……第2の電極、7、25……配線
パターン、8……スルーホール、9……異方性導電接着
剤、11……マザー基板。
1, 20 ... semiconductor device, 2, 21 ... interposer,
3 ... semiconductor chip, 3A ... bump, 4, 24 ... first electrode, 6, 26 ... second electrode, 7, 25 ... wiring pattern, 8 ... through hole, 9 ... anisotropic Conductive adhesive, 11 ... mother board.

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】透明又は半透明な材料を用いて形成された
絶縁基板と、 上記絶縁基板の一面側に半導体チツプの各電極にそれぞ
れ対応させて形成された複数の第1の電極と、 上記絶縁基板の上記一面側又は他面側に、各上記第1の
電極とそれぞれ対応させて上記第1の電極の電極間ピツ
チよりも拡い電極間ピツチで形成された第2の電極と、 上記第1及び第2の電極のうち対応するもの同士を導体
接続する導体接続手段とを具えることを特徴とする配線
板。
An insulating substrate formed by using a transparent or translucent material; a plurality of first electrodes formed on one surface of the insulating substrate so as to correspond to respective electrodes of a semiconductor chip; A second electrode formed on the one surface side or the other surface side of the insulating substrate with an inter-electrode pitch wider than the inter-electrode pitch of the first electrode corresponding to each of the first electrodes; A wiring board, comprising: a conductor connecting means for conductor-connecting a corresponding one of the first and second electrodes.
【請求項2】上記絶縁基板を形成する上記透明又は半透
明な材料は、ガラス材でなることを特徴とする請求項1
に記載の配線板。
2. The method according to claim 1, wherein the transparent or translucent material forming the insulating substrate is a glass material.
The wiring board according to the above.
【請求項3】上記絶縁基板は、上記一面側に上記半導体
チツプを収納できる大きさの凹部を有することを特徴と
する請求項1に記載の配線板。
3. The wiring board according to claim 1, wherein the insulating substrate has a concave portion on the one surface side, the concave portion being large enough to accommodate the semiconductor chip.
【請求項4】透明又は半透明な材料を用いて形成された
絶縁基板の一面側に半導体チツプの各電極にそれぞれ対
応させて複数の第1の電極を形成すると共に、上記絶縁
基板の上記一面側又は他面側に各上記第1の電極とそれ
ぞれ対応させて上記第1の電極の電極間ピツチよりも拡
い電極間ピツチで第2の電極を形成し、かつ上記第1及
び第2の電極のうち対応するもの同士を導体接続する第
1の工程と、 上記絶縁基板を所定温度に加熱した状態で当該絶縁基板
の上記一面に上記半導体チツプに応じた所定形状の治具
を所定圧力及び所定時間押し当てることにより上記半導
体チツプを収納する凹部を形成する第2の工程とを具え
ることを特徴とする配線板の製造方法。
4. A plurality of first electrodes corresponding to each electrode of a semiconductor chip are formed on one surface of an insulating substrate formed using a transparent or translucent material, and the first surface of the insulating substrate is formed. A second electrode is formed on the side or the other side with an inter-electrode pitch wider than the inter-electrode pitch of the first electrode corresponding to each of the first electrodes, and the first and second electrodes are formed. A first step of electrically connecting corresponding ones of the electrodes to each other, and a jig having a predetermined shape corresponding to the semiconductor chip is applied to the one surface of the insulating substrate while heating the insulating substrate to a predetermined temperature under a predetermined pressure and pressure. Forming a recess for accommodating the semiconductor chip by pressing for a predetermined time.
【請求項5】配線板の一面側に半導体チツプが実装され
てなる半導体装置において、 上記配線板は、 透明又は半透明な材料を用いて形成された絶縁基板と、 上記配線板の上記一面を形成する上記絶縁基板の一面側
に上記半導体チツプの各電極にそれぞれ対応させて形成
された複数の第1の電極と、 上記絶縁基板の上記一面側又は他面側に各上記第1の電
極とそれぞれ対応させて上記第1の電極の電極間ピツチ
よりも拡い電極間ピツチで形成された第2の電極と、 上記第1及び第2の電極のうち対応するもの同士を導体
接続する導体接続手段とを具えることを特徴とする半導
体装置。
5. A semiconductor device in which a semiconductor chip is mounted on one surface side of a wiring board, wherein the wiring board includes an insulating substrate formed using a transparent or translucent material, and the one surface of the wiring board. A plurality of first electrodes formed on one surface of the insulating substrate to be formed so as to correspond to the respective electrodes of the semiconductor chip; and a plurality of first electrodes formed on the one surface or the other surface of the insulating substrate. A second electrode formed with an inter-electrode pitch wider than the inter-electrode pitch of the first electrode, and a conductor connection for electrically connecting corresponding ones of the first and second electrodes. A semiconductor device comprising:
【請求項6】上記絶縁基板を形成する上記透明又は半透
明な材料は、ガラス材でなることを特徴とする請求項5
に記載の半導体装置。
6. The transparent or semi-transparent material forming the insulating substrate is made of a glass material.
3. The semiconductor device according to claim 1.
【請求項7】上記絶縁基板は、上記一面側に上記半導体
チツプを収納できる大きさの凹部を有することを特徴と
する請求項5に記載の半導体装置。
7. The semiconductor device according to claim 5, wherein the insulating substrate has a concave portion on the one surface side, the concave portion being large enough to accommodate the semiconductor chip.
JP24323297A 1997-09-08 1997-09-08 Wiring board, manufacture thereof, and semiconductor device Pending JPH1187873A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP24323297A JPH1187873A (en) 1997-09-08 1997-09-08 Wiring board, manufacture thereof, and semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP24323297A JPH1187873A (en) 1997-09-08 1997-09-08 Wiring board, manufacture thereof, and semiconductor device

Publications (1)

Publication Number Publication Date
JPH1187873A true JPH1187873A (en) 1999-03-30

Family

ID=17100809

Family Applications (1)

Application Number Title Priority Date Filing Date
JP24323297A Pending JPH1187873A (en) 1997-09-08 1997-09-08 Wiring board, manufacture thereof, and semiconductor device

Country Status (1)

Country Link
JP (1) JPH1187873A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339197B1 (en) 1999-05-27 2002-01-15 Hoya Corporation Multilayer printed circuit board and the manufacturing method
WO2015151292A1 (en) * 2014-04-04 2015-10-08 三菱電機株式会社 Printed wire board unit

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6339197B1 (en) 1999-05-27 2002-01-15 Hoya Corporation Multilayer printed circuit board and the manufacturing method
US7470865B2 (en) 1999-05-27 2008-12-30 Hoya Corporation Multilayer printed wiring board and a process of producing same
WO2015151292A1 (en) * 2014-04-04 2015-10-08 三菱電機株式会社 Printed wire board unit

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