JP3019027B2 - Structure of IC package using rigid / flexible substrate - Google Patents
Structure of IC package using rigid / flexible substrateInfo
- Publication number
- JP3019027B2 JP3019027B2 JP14354897A JP14354897A JP3019027B2 JP 3019027 B2 JP3019027 B2 JP 3019027B2 JP 14354897 A JP14354897 A JP 14354897A JP 14354897 A JP14354897 A JP 14354897A JP 3019027 B2 JP3019027 B2 JP 3019027B2
- Authority
- JP
- Japan
- Prior art keywords
- rigid
- flexible substrate
- substrate
- board
- flexible
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32225—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Testing Or Measuring Of Semiconductors Or The Like (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
【０００１】[0001]
【発明の属する技術分野】本発明は、半導体集積回路装
置に関し、特にリジッド・フレキシブル基板を利用した
ＩＣパッケージの構造に関する。[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor integrated circuit device, and more particularly, to a structure of an IC package using a rigid flexible substrate.
【０００２】[0002]
【従来の技術】ＬＳＩの高集積化・高速化に伴い、ＬＳ
Ｉの多ピン化傾向は顕著である。この多ピン化に伴い、
従来のＱＦＰ（Ｑｕａｄ Ｆｌａｔ Ｐａｃｋａｇｅ）
ではパッケージ外周部の端子数を増加するために、端子
ピッチを狭めなくてはならず、これ以上ピッチを狭める
ことはＱＦＰリードの強度や半田付け性から不可能に近
く、多ピン化に対応できない。2. Description of the Related Art With the increase in integration and speed of LSI, LS
I has a remarkable tendency to increase the number of pins. With this increase in pins,
Conventional QFP (Quad Flat Package)
In order to increase the number of terminals on the outer peripheral part of the package, the terminal pitch must be reduced, and further narrowing the pitch is almost impossible due to the strength and solderability of the QFP lead, and it is not possible to cope with the increase in the number of pins. .
【０００３】そこで、基板底面からエリアアレイ状に入
出力端子を取るパッケージが開発され、特に近年注目を
集めているパッケージがＢＧＡ（Ｂａｌｌ Ｇｒｉｄ
Ａｒｒａｙ；ボールグリッドアレイ）である。ＢＧＡに
ついては刊行物（日経エレクトロニクス、１９９４．
２．１４、６０１号、第６１頁）等の記載が参照され
る。[0003] In view of this, a package has been developed in which input / output terminals are formed in an area array form from the bottom surface of the substrate.
Array; ball grid array). For BGA, see the publication (Nikkei Electronics, 1994.
2.14, 601, p. 61).
【０００４】ＢＧＡは、プリント基板にベアチップをワ
イヤボンディングで基板配線と接続し、スルーホールを
介して基板底面のエリアアレイ状に整列した入出力端子
である半田ボールに接続されるパッケージである。ＢＧ
Ａは、他の表面実装型部品とまとめて半田付けできるた
め、スルーホール挿入タイプのＰＧＡ（Ｐｉｎ Ｇｒｉ
ｄ Ａｒｒａｙ）に比べ製造性で優れている。The BGA is a package in which a bare chip is connected to a substrate wiring by wire bonding on a printed circuit board, and connected to solder balls as input / output terminals arranged in an area array on the bottom surface of the substrate via through holes. BG
A can be soldered together with other surface mount components, so through hole insertion type PGA (Pin Gri
d Array).
【０００５】図８（Ａ）は、従来のプラスチックＢＧＡ
の構造を示す断面図である。図８（Ａ）を参照して、小
さな両面プリント配線基板６０にＬＳＩのベアチップ６
１を搭載し、ワイヤボンディング６２で基板配線と接続
してある。両面基板の上面には、配線が中央から端部に
向かって走り、それからスルーホール６３を通じて基板
底面に移る。底面の端部から中央に向かって配線が走
り、端子（半田ボール）へ６４到る。ＬＳＩチップ６１
はモールド樹脂６５で封止される。FIG. 8A shows a conventional plastic BGA.
FIG. 3 is a cross-sectional view showing the structure of FIG. Referring to FIG. 8A, a bare chip 6 of an LSI is mounted on a small double-sided printed wiring board 60.
1 is mounted and connected to the substrate wiring by wire bonding 62. On the upper surface of the double-sided substrate, the wiring runs from the center to the end, and then moves to the substrate bottom surface through the through hole 63. The wiring runs from the end of the bottom surface to the center, and reaches 64 to the terminal (solder ball). LSI chip 61
Is sealed with a mold resin 65.
【０００６】また、プリント基板上に複数のベアチップ
を搭載してＭＣＭ（Ｍｕｌｔｉ Ｃｈｉｐ Ｍｏｄｕｌ
ｅ；マルチチップモジュール）化し、このＭＣＭの入出
力端子としてＢＧＡ構造を採用したパッケージも実用化
されている。例えば文献（回路実装学会誌Ｖｏｌ．１
１、Ｎｏ．５、ＡＵＧ．、１９９６）の記載が参照され
る。図８（Ｂ）は、上記文献に記載のＭＣＭの断面図を
示したものである。Further, a plurality of bare chips are mounted on a printed circuit board to form an MCM (Multi Chip Modul).
e; a multi-chip module), and a package adopting a BGA structure as an input / output terminal of the MCM has been put to practical use. For example, a document (Journal of the Circuit Packaging Society, Vol. 1)
1, No. 5, AUG. , 1996). FIG. 8B is a cross-sectional view of the MCM described in the above document.
【０００７】[0007]
【発明が解決しようとする課題】しかしながら、ＢＧＡ
を採用したパッケージにおいては、ＢＧＡをマザーボー
ドに実装した後に接続確認が容易に行えない、という問
題点を有している。このため、接続確認を行うには、Ｘ
線検査装置など専用の検査装置が必要になる。However, the BGA
Has a problem that the connection cannot be easily checked after the BGA is mounted on the motherboard. Therefore, to check the connection, X
A dedicated inspection device such as a line inspection device is required.
【０００８】ＢＧＡを採用したパッケージの第２の問題
点としては、検査に際して、ＢＧＡのインサーキットテ
ストもしくはバーインテストが容易でない、ということ
である。A second problem of the package using the BGA is that it is not easy to perform an in-circuit test or a burn-in test of the BGA at the time of inspection.
【０００９】その理由は、ＢＧＡを用いたパッケージは
入出力端子が基板底面にあるため、テスタのプローブピ
ンで触れることができない、からである。このため、専
用のテスト用のソケットが必要になる。The reason is that a package using a BGA cannot be touched by a probe pin of a tester because input / output terminals are provided on the bottom surface of the substrate. Therefore, a dedicated test socket is required.
【００１０】したがって、本発明は、上記した問題点に
鑑みてなされたものであって、その目的は、従来のＢＧ
Ａに代表される底面に端子を設けたパッケージよりも製
造検査、電気検査性を向上し、多ピンのＬＳＩパッケー
ジの製造検査と電気検査を容易に行うことを可能とした
ＬＳＩパッケージの構造を提供することにある。[0010] Accordingly, the present invention has been made in view of the above problems, and has as its object a conventional BG.
A LSI package structure that improves manufacturing inspection and electrical inspection performance compared to a package having terminals on the bottom surface represented by A, and enables easy manufacturing inspection and electrical inspection of a multi-pin LSI package. Is to do.
【００１１】また、本発明は、上記目的に加えて、複数
のチップを搭載することが可能としモジュール化を可能
として高集積化を図るマルチチップモジュールの構造を
提供することもその目的としている。Another object of the present invention is to provide a structure of a multi-chip module capable of mounting a plurality of chips, modularizing the module, and achieving high integration, in addition to the above objects.
【００１２】[0012]
【課題を解決するための手段】 前記目的を達成するた
め、本発明のＬＳＩパッケージの構造は、フレキシブル
基板と、該フレキシブル基板と一体形成される銅張積層
板よりなるリジッド基板とを有し、少なくとも内層に信
号層を一層以上有する、リジッド・フレキシブル基板に
おいて、前記銅張積層板はエポキシ系樹脂を含浸させた
ガラスクロスを用いて構成され、フレキシブル基板がリ
ジッド基板四辺の端面から出ている構造とされ、前記フ
レキシブル基板上に接続用のアウターリードが前記リジ
ッド基板から外へ向かう方向へ形成され、前記アウター
リードと直交するように前記フレキシブル基板に溝孔が
設けられ、前記溝孔を跨いだ前記アウターリードが矩形
の銅箔で終端されており、前記リジッド基板上に、一つ
のベアチップが実装される。Means for Solving the Problems In order to achieve the above object, an LSI package structure of the present invention has a flexible substrate and a rigid substrate made of a copper-clad laminate integrally formed with the flexible substrate, In a rigid / flexible substrate having at least one signal layer in the inner layer, the copper-clad laminate is impregnated with an epoxy resin.
The flexible substrate is constituted by using a glass cloth, and has a structure in which a flexible substrate protrudes from the four end faces of the rigid substrate. Outer leads for connection are formed on the flexible substrate in a direction outward from the rigid substrate, and the outer leads A groove is provided in the flexible substrate so as to be orthogonal to the above, and the outer lead straddling the groove is terminated with a rectangular copper foil, and one bare chip is mounted on the rigid substrate.
【００１３】 また、本発明のマルチチップモジュール
の構造は、フレキシブル基板と、該フレキシブル基板と
一体に形成される銅張積層板よりなるリジッド基板とを
有し、少なくとも内層に信号層を一層以上有する、リジ
ッド・フレキシブル基板において、前記銅張積層板はエ
ポキシ系樹脂を含浸させたガラスクロスを用いて構成さ
れ、前記フレキシブル基板が前記リジッド基板四辺の端
面から出ている構造とされ、前記フレキシブル基板上に
接続用のアウターリードが、前記リジッド基板から外へ
向かう方向へ形成され、前記アウターリードと直交する
ように前記フレキシブル基板に溝孔が設けられ、前記溝
孔を跨いだアウターリードが矩形の銅箔で終端されてお
り、前記リジッド基板上に、少なくとも一つのベアチッ
プと１又は複数のＬＳＩが実装されている。Further, the structure of the multichip module of the present invention has a flexible substrate and a rigid substrate made of a copper-clad laminate formed integrally with the flexible substrate, and has at least one signal layer in at least an inner layer. In a rigid / flexible substrate, the copper-clad laminate is
Constructed using glass cloth impregnated with oxy resin
The flexible substrate has a structure protruding from the end face of the four sides of the rigid substrate, and outer leads for connection are formed on the flexible substrate in a direction outward from the rigid substrate, and are orthogonal to the outer leads. As described above, a groove is provided in the flexible substrate, an outer lead straddling the groove is terminated with a rectangular copper foil, and at least one bare chip and one or more LSIs are mounted on the rigid substrate. ing.
【００１４】［発明の概要］上記のように構成されてな
る本発明のリジッド・フレキシブル基板を使ったＬＳＩ
パッケージは、製造検査性、電気検査性を改善したもの
である。すなわち、本発明においては、フレキシブル基
板にアウターリードを形成し、プリント基板外周からそ
のアウターリードが出ており、フレキシブル基板にアウ
ターリードと直交するアウターリードホールを有し、ア
ウターリードが検査用パッドで終端されていることを特
徴としたものである。[Summary of the Invention] An LSI using the rigid / flexible substrate of the present invention configured as described above.
The package has improved manufacturing testability and electrical testability. That is, in the present invention, the outer leads are formed on the flexible substrate, the outer leads protrude from the outer periphery of the printed circuit board, and the flexible substrate has outer lead holes orthogonal to the outer leads, and the outer leads are inspection pads. It is characterized by being terminated.
【００１５】パッケージの検査にはフレキシブル基板に
設けられたアウターリードを週端している検査用パッド
を用いる。Inspection of the package uses an inspection pad which is provided with an outer lead provided on a flexible substrate.
【００１６】マザーボードに実装する場合は、アウター
リードホールで切断し、マザーボード上に実装し、アウ
ターリードとパッドを半田接続する。このため接続確認
の外観検査が容易である。When mounting on a motherboard, the chip is cut at the outer lead hole, mounted on the motherboard, and the outer leads and the pads are connected by soldering. For this reason, the appearance inspection for connection confirmation is easy.
【００１７】[0017]
【発明の実施の形態】本発明の好ましい実施の形態につ
いて以下に図面を参照して説明する。図１（Ａ）は、本
発明の実施の形態の構成を示す斜視図である。また図１
（Ｂ）は、本発明の実施の形態の構成を示す上面図であ
る。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be described below with reference to the drawings. FIG. 1A is a perspective view illustrating a configuration of an embodiment of the present invention. FIG.
(B) is a top view which shows the structure of embodiment of this invention.
【００１８】図１を参照すると、本発明の実施の形態
は、配線層を内側に有し、フレキシブル基板２に形成し
たアウターリード４を基板外周から外方向へ出し、フレ
キシブル基板にアウターリード４と直交する向きに開口
したアウターリードホール６を設け、このホール６を跨
いだアウターリード２が検査用のパッド５で終端され、
リジッド基板３上に一つのベアチップが実装されてい
る。Referring to FIG. 1, in the embodiment of the present invention, an outer lead 4 formed on a flexible substrate 2 has a wiring layer on the inner side and extends outward from the outer periphery of the substrate, and the outer substrate 4 is connected to the flexible substrate. An outer lead hole 6 opened in an orthogonal direction is provided, and the outer lead 2 straddling this hole 6 is terminated by a pad 5 for inspection.
One bare chip is mounted on the rigid board 3.
【００１９】また、このＬＳＩパッケージはアウターリ
ード４を接続端子としてマザーボード上のパッドと半田
接続される。The LSI package is soldered to pads on the motherboard using the outer leads 4 as connection terminals.
【００２０】また、上記リジッド・フレキシブル基板上
に少なくとも一つ以上のベアチップと複数の封止された
ＩＣを実装し、マルチチップモジュールを構成する。At least one or more bare chips and a plurality of sealed ICs are mounted on the rigid / flexible substrate to form a multi-chip module.
【００２１】このマルチチップモジュールはアウターリ
ードを接続端子としてマザーボード上のパッドと半田接
続される。The multi-chip module is connected to pads on the motherboard by soldering using the outer leads as connection terminals.
【００２２】[0022]
【実施例】上記した実施の形態について更に詳細に説明
すべく、本発明の実施例について図面を参照して以下に
説明する。DESCRIPTION OF THE PREFERRED EMBODIMENTS In order to explain the above-mentioned embodiment in more detail, an embodiment of the present invention will be described below with reference to the drawings.
【００２３】図１を参照すると、本発明の一実施例は、
少なくとも内層に配線層を有するフレキシブル・リジッ
ド基板１において、一つ又は複数のＬＳＩ７が実装さ
れ、基板外周から入出力端子としてフレキシブル基板２
に形成されたアウターリード４が外方向に並置され、ア
ウターリード４はフレキシブル基板２に設けられたアウ
ターリードホール６と直交し、検査用パッド５で終端さ
れている。Referring to FIG. 1, one embodiment of the present invention is:
In a flexible rigid board 1 having a wiring layer at least in an inner layer, one or a plurality of LSIs 7 are mounted, and the flexible board 2
The outer leads 4 are arranged side by side in the outward direction. The outer leads 4 are orthogonal to the outer lead holes 6 provided in the flexible substrate 2 and are terminated by the test pads 5.
【００２４】フレキシブル・リジッド基板１は、両面に
導体がラミネートされたフレキシブル基板２と、リジッ
ド基板３を構成する少なくとも一層以上の銅張積層板１
０とをプリプレグ１１（図２参照）を介して積層したプ
リント基板である。The flexible rigid board 1 includes a flexible board 2 having conductors laminated on both sides thereof, and at least one or more copper-clad laminates 1 constituting the rigid board 3.
0 is a printed circuit board laminated with a prepreg 11 (see FIG. 2).
【００２５】本実施例では、フレキシブル基板２は、厚
さ５０μｍのポリイミドフィルムを用いている。ここで
使用されるフィルムは、耐熱性があり、寸法安定性が良
好で、導体との密着が必要とされる。このため他の材料
としては、フッ素系フィルムやエポキシ系フィルムが適
用できる。In this embodiment, the flexible substrate 2 uses a polyimide film having a thickness of 50 μm. The film used here has heat resistance, good dimensional stability, and requires close contact with the conductor. For this reason, as another material, a fluorine-based film or an epoxy-based film can be applied.
【００２６】このフレキシブル基板２のサイズは、積層
時に４０ｍｍ□のリジッド基板３の四辺からこのフィル
ムが均等に露出する大きさにする。本実施例ではフレキ
シブル基板２のサイズは６０ｍｍ□としている。The size of the flexible substrate 2 is set such that the film is uniformly exposed from the four sides of the rigid substrate 3 of 40 mm square during lamination. In this embodiment, the size of the flexible substrate 2 is 60 mm □.
【００２７】このフレキシブル基板２の両面には、厚さ
３５μｍの銅箔９（図２参照）がラミネートされてい
る。A copper foil 9 (see FIG. 2) having a thickness of 35 μm is laminated on both sides of the flexible substrate 2.
【００２８】リジッド基板３を構成する銅張積層板１０
との積層前に、このフレキシブル基板２に、あらかじめ
パターン形成しておき、１．５μｍのスズメッキ仕上げ
をする。Copper-clad laminate 10 constituting rigid substrate 3
Before lamination with the above, a pattern is formed on the flexible substrate 2 in advance, and a tin plating finish of 1.5 μm is performed.
【００２９】複数の銅張積層板１０を積層した後に、貫
通スルーホール１２を介してリジッド基板３の導体パタ
ーンと電気的に接続される。After the plurality of copper clad laminates 10 are laminated, they are electrically connected to the conductor pattern of the rigid board 3 through the through-holes 12.
【００３０】本実施例の銅張積層板は、エポキシ系の樹
脂を含浸させたガラスクロスを用いている。これはポリ
イミド樹脂でもよい。The copper-clad laminate of this embodiment uses a glass cloth impregnated with an epoxy resin. This may be a polyimide resin.
【００３１】基板四辺から外部端子として出すアウター
リード４は、フレキシブル基板２の導体９をパターニン
グして形成する。アウターリード４は５００μｍ幅で
１．２７ｍｍピッチで並ぶ。このアウターリード４の終
端は、途中アウターリードホール６を跨いで検査用のパ
ッド５に接続される。The outer leads 4 extending from the four sides of the substrate as external terminals are formed by patterning the conductor 9 of the flexible substrate 2. The outer leads 4 are arranged at a pitch of 1.27 mm with a width of 500 μm. The end of the outer lead 4 is connected to the inspection pad 5 across the outer lead hole 6 on the way.
【００３２】ＬＳＩチップ７は、この実施例では、１４
×１４ｍｍの形状で、５００の入出力端子を有し、フリ
ップチップ実装される。なお、ＬＳＩチップは半導体チ
ップの一例であり、ＩＣチップの他、半導体デバイスで
あればよい。In this embodiment, the LSI chip 7 has 14
It has a shape of × 14 mm, has 500 input / output terminals, and is flip-chip mounted. The LSI chip is an example of a semiconductor chip, and may be any semiconductor device other than the IC chip.
【００３３】次に本発明の実施例のパッケージの製造方
法並びに実装方法について図２及び図３を参照して詳細
に説明する。図２及び図３は、本発明の一実施例のリジ
ッド・フレキシブル基板の主要製造工程を工程順に示し
た断面図である。なお、図２及び図３は単に図面作成の
都合で分図されたものである。Next, a method of manufacturing and mounting a package according to an embodiment of the present invention will be described in detail with reference to FIGS. 2 and 3 are cross-sectional views showing main manufacturing steps of a rigid / flexible board according to an embodiment of the present invention in the order of steps. Note that FIGS. 2 and 3 are merely separated for convenience of drawing.
【００３４】フレキシブル基板２は、５０μｍ厚のポリ
イミドフィルム８の両面に３５μｍ厚の導体９がラミネ
ートされている（図２（Ａ）参照）。The flexible substrate 2 has a conductor 9 having a thickness of 35 μm laminated on both sides of a polyimide film 8 having a thickness of 50 μm (see FIG. 2A).
【００３５】その銅箔９の全面にドライフィルムレジス
トをラミネートし、アウターリードホール６領域の銅箔
をドライフィルムを露光・現像で露出させ、塩化第２銅
で露出した銅箔を除去する。ドライフィルムレジストは
例えば旭化成のＭＶＡシリーズが用いられる（図２
（Ｂ）参照）。A dry film resist is laminated on the entire surface of the copper foil 9, the copper foil in the outer lead hole 6 area is exposed by exposure and development, and the copper foil exposed by cupric chloride is removed. As the dry film resist, for example, MVA series of Asahi Kasei is used (FIG. 2).
(B)).
【００３６】次に銅箔９をマスクとして、アウターリー
ドホール６領域のポリイミドフィルム８をプラズマガス
で除去する。この場合プラズマガスの成分はＣＦ4とＯ2
の混合ガスである（図２（Ｃ）参照）。Next, using the copper foil 9 as a mask, the polyimide film 8 in the area of the outer lead hole 6 is removed with a plasma gas. In this case, the components of the plasma gas are CF 4 and O 2
(See FIG. 2C).
【００３７】図２（Ｂ）と同様に、湿式法によりパター
ン形成する。その後、リジッド基板３端面から出るアウ
ターリード４に選択的に１〜２μｍのスズメッキを行う
（図２（Ｄ）参照）。As in FIG. 2B, a pattern is formed by a wet method. Thereafter, tin plating of 1 to 2 μm is selectively performed on the outer leads 4 protruding from the end surface of the rigid substrate 3 (see FIG. 2D).
【００３８】パターン形成したフレキシブル基板２の上
下にプリプレグ１１を介して、同じく湿式法でパターン
形成した厚さ０．１ｍｍの銅張積層板１０を積層し、熱
プレスする。プリプレグ１１は例えば熱硬化性半硬化樹
脂含浸ガラスクロスである。A copper-clad laminate 10 having a thickness of 0.1 mm, also patterned by a wet method, is laminated above and below the patterned flexible substrate 2 via a prepreg 11 and hot-pressed. The prepreg 11 is, for example, a thermosetting semi-cured resin impregnated glass cloth.
【００３９】積層熱プレスは、温度１５０〜３００℃、
圧力１０〜４０ｋｇｆ／ｃｍの条件で行う（図３（Ｅ）
参照）。The laminated hot press has a temperature of 150 to 300 ° C.
This is performed under the conditions of a pressure of 10 to 40 kgf / cm (FIG. 3E).
reference).
【００４０】積層後に所定の穴位置にドリル加工等で貫
通スルーホール１２を形成する。スルーホール１２の径
は０．３５ｍｍである（図３（Ｆ）参照）。After lamination, a through-hole 12 is formed at a predetermined hole position by drilling or the like. The diameter of the through hole 12 is 0.35 mm (see FIG. 3 (F)).
【００４１】更にスルーホール１２内に銅メッキを施
し、内層と外層の電気的な導通を得る。この時アウター
リード４に銅メッキがされないようにアウターリード６
にマスキングテープを施す必要がある（図３（Ｇ）参
照）。Further, copper plating is applied to the inside of the through hole 12 to obtain electrical continuity between the inner layer and the outer layer. At this time, the outer leads 6 are not plated with copper.
(See FIG. 3 (G)).
【００４２】図４は、本発明の一実施例をなすリジッド
・フレキシブル基板１への部品実装工程を説明する断面
図である。図４を参照して、リジッド・フレキシブル基
板１への部品実装工程を説明する。FIG. 4 is a sectional view for explaining a process of mounting components on the rigid / flexible substrate 1 according to one embodiment of the present invention. With reference to FIG. 4, a process of mounting components on the rigid / flexible substrate 1 will be described.
【００４３】図２及び図３に示した製造工程により得ら
れたリジッド・フレキシブル基板１のリジッド基板３上
の搭載パッドにクリーム状の共晶半田を印刷により供給
し、フラックス塗布後ＬＳＩチップ７を所定の位置に位
置合わせして実装する。A creamy eutectic solder is supplied by printing to the mounting pads on the rigid board 3 of the rigid / flexible board 1 obtained by the manufacturing steps shown in FIGS. 2 and 3, and after applying the flux, the LSI chip 7 is mounted. It is mounted at a predetermined position.
【００４４】本実施例では、ＬＳＩチップ７の回路面に
エリアアレイ状の半田ボール１３を供給し、リジッド基
板３上にフリップチップ実装し、リフローする。リフロ
ー温度は２００〜２５０℃である。リフローした後フラ
ックスを洗浄除去する（図４（Ａ）参照）。In this embodiment, solder balls 13 in an area array are supplied to the circuit surface of the LSI chip 7, flip-chip mounted on the rigid board 3, and reflowed. The reflow temperature is 200-250 ° C. After the reflow, the flux is washed and removed (see FIG. 4A).
【００４５】次に接続が完全に行われているか、インサ
ーキットテストを行う。Next, an in-circuit test is performed to check whether the connection is completely established.
【００４６】本実施例では、プローブカード方式でプロ
ーブ１５をフレキシブル基板周囲にある検査用パッド５
に接触させて行う（図４（Ｂ）参照）。In this embodiment, the probe 15 is connected to the inspection pad 5 around the flexible substrate by the probe card method.
(See FIG. 4B).
【００４７】接合の確認をした後、チップ７とリジッド
基板３の間を有機樹脂１６で封止して、チップ７とリジ
ッド基板３の熱膨張係数の差による応力を吸収する。本
実施例では、封止樹脂はエポキシを用いた（図４（Ｃ）
参照）。After confirming the bonding, the space between the chip 7 and the rigid substrate 3 is sealed with an organic resin 16 to absorb the stress due to the difference in the coefficient of thermal expansion between the chip 7 and the rigid substrate 3. In this embodiment, epoxy was used as the sealing resin (FIG. 4C).
reference).
【００４８】図５乃至図７は、本発明の一実施例のマザ
ーボード基板への実装を説明するための図である。図５
乃至図７を参照して、マザーボードへの実装について以
下に説明する。FIGS. 5 to 7 are views for explaining mounting on a motherboard substrate according to one embodiment of the present invention. FIG.
With reference to FIG. 7 to FIG. 7, mounting on a motherboard will be described below.
【００４９】検査が終了し、完全良品と判定された、リ
ジッド・フレキシブル基板パッケージは、アウターリー
ドホール６端から所定の位置で切断し、同時にアウター
リード４の成型を行う（図５（Ａ）参照）。The rigid / flexible board package, which has been inspected and determined to be completely non-defective, is cut at a predetermined position from the end of the outer lead hole 6 and, at the same time, the outer lead 4 is molded (see FIG. 5A). ).
【００５０】マザーボード１８上の搭載パッド１７にク
リーム状の半田供給を印刷等で行い、フラックス塗布の
後チップ７を実装したリジッド・フレキシブル基板１パ
ッケージを実装する。２００℃から２５０℃の温度でリ
フローした後、洗浄する（図６（Ｂ）参照）。A creamy solder is supplied to the mounting pads 17 on the motherboard 18 by printing or the like, and after applying flux, the rigid / flexible substrate 1 package on which the chip 7 is mounted is mounted. After reflowing at a temperature of 200 ° C. to 250 ° C., cleaning is performed (see FIG. 6B).
【００５１】半田の接続確認を目視で行い、問題なけれ
ばアウターリード４の保護のため有機樹脂１９で封止す
る。本実施例では、有機樹脂１９はエポキシ樹脂を用い
た（図６（Ｃ）参照）。図７（Ｄ）は、有機樹脂１９で
アウターリード４を封止した状態の一例を示す断面図で
ある。The connection of the solder is visually confirmed, and if there is no problem, the outer lead 4 is sealed with an organic resin 19 for protection. In this embodiment, an epoxy resin was used as the organic resin 19 (see FIG. 6C). FIG. 7D is a cross-sectional view illustrating an example of a state where the outer leads 4 are sealed with the organic resin 19.
【００５２】上記実施例では、フレキシブル基板の製造
工程でポリイミドフィルムの除去をプラズマガスで行っ
たが、ＣＯ2エキシマレーザーでも可能である。In the above embodiment, the removal of the polyimide film was performed with the plasma gas in the manufacturing process of the flexible substrate. However, it is also possible to use a CO 2 excimer laser.
【００５３】上記実施例では、パッケージとマザーボー
ドの接続を共晶半田としたが、異方性導電シートによる
接着も可能である。In the above embodiment, the connection between the package and the motherboard is made of eutectic solder. However, it is also possible to use an anisotropic conductive sheet for bonding.
【００５４】[0054]
【発明の効果】以上説明したように、本発明によれば、
下記記載の効果を奏する。As described above, according to the present invention,
The following effects are obtained.
【００５５】（１）本発明の第１の効果は、マザーボー
ドへの実装後の接続確認が容易に行える、ということで
ある。(1) The first effect of the present invention is that the connection after mounting on the motherboard can be easily confirmed.
【００５６】その理由は、本発明においては、リジッド
・フレキシブル基板のフレキシブル基板にマザーボード
と接続する端子をパターンで設け、これにより、パッケ
ージの入出力端子が基板外周から取れるため、確認を行
いやすい、ためである。The reason for this is that, in the present invention, the terminals for connecting to the motherboard are provided in a pattern on the flexible substrate of the rigid flexible substrate, so that the input / output terminals of the package can be taken from the outer periphery of the substrate. That's why.
【００５７】（２）本発明の第２の効果は、専用の検査
用ソケットを用いずに多ピンのパッケージの検査が容易
に行える、ということである。(2) A second effect of the present invention is that a multi-pin package can be easily inspected without using a dedicated inspection socket.
【００５８】その理由は、本発明においては、リジッド
・フレキシブル基板のフレキシブル基板にマザーボード
と接続する端子をパターンで設け、これにより、フレキ
シブル基板に形成したアウターリードの延在した領域
に、検査用のパッドを設けることができるからである。The reason for this is that, in the present invention, terminals for connecting to the motherboard are provided in a pattern on the flexible board of the rigid flexible board, so that the area for extension of the outer leads formed on the flexible board is used for inspection. This is because pads can be provided.
【００５９】（３）本発明の第３の効果は、複数のＬＳ
Ｉを搭載可能とし、高集積化が可能となる、ということ
である。(3) The third effect of the present invention is that a plurality of LS
I can be mounted, and high integration can be achieved.
【００６０】その理由は、本発明においては、リジッド
・フレキシブル基板のフレキシブル基板に、マザーボー
ドと接続する端子をパターンで設けたことによる。The reason is that, in the present invention, the terminals for connecting to the motherboard are provided in a pattern on the flexible substrate of the rigid flexible substrate.
【図１】本発明の一実施例の構成を示す図であり、
（Ａ）は、リジッド・フレキシブル基板の斜視図、
（Ｂ）は、リジッド・フレキシブル基板の上面図であ
る。FIG. 1 is a diagram showing a configuration of an embodiment of the present invention;
(A) is a perspective view of a rigid flexible substrate,
(B) is a top view of the rigid / flexible substrate.
【図２】本発明の一実施例のリジッド・フレキシブル基
板の製造工程を工程順に示した断面図である。FIG. 2 is a cross-sectional view showing a manufacturing process of a rigid / flexible board according to an embodiment of the present invention in the order of steps.
【図３】本発明の一実施例のリジッド・フレキシブル基
板の製造工程を工程順に示した断面図である。FIG. 3 is a cross-sectional view showing a manufacturing process of a rigid / flexible substrate according to an embodiment of the present invention in the order of steps.
【図４】本発明の一実施例のリジッド・フレキシブル基
板へのＬＳＩ実装の様子を説明するための断面図であ
る。FIG. 4 is a cross-sectional view for explaining a state of mounting an LSI on a rigid / flexible board according to an embodiment of the present invention.
【図５】本発明の一実施例のマザーボードへの実装を模
式的に示した斜視図である。FIG. 5 is a perspective view schematically showing mounting on a motherboard according to one embodiment of the present invention.
【図６】（Ｂ）、（Ｃ）は本発明の一実施例のマザーボ
ードへの実装を示した斜視図である。FIGS. 6B and 6C are perspective views showing mounting on a motherboard according to one embodiment of the present invention.
【図７】（Ｄ）は本発明の一実施例のマザーボードへの
実装を示した部分断面図である。FIG. 7D is a partial cross-sectional view showing mounting on a motherboard according to one embodiment of the present invention.
【図８】従来技術を示す図であり、（Ａ）は従来のＢＧ
Ａの断面を示す図、（Ｂ）はＭＣＭを示す断面図であ
る。FIG. 8 is a diagram showing a conventional technology, in which (A) shows a conventional BG
FIG. 3A is a cross-sectional view illustrating an MCM. FIG.
１ リジッド・フレキシブル基板 ２ フレキシブル基板 ３ リジッド基板 ４ アウターリード ５ 検査用パッド ６ アウターリードホール ７ ＬＳＩ ８ ポリイミドフィルム ９ 銅箔 １０ 銅張積層板 １１ プリプレグ １２ 貫通スルーホール １３ 半田ボール １４ プローブカード １５ プローブ １６、１９ 封止樹脂 １７ 搭載パッド １８ マザーボード DESCRIPTION OF SYMBOLS 1 Rigid flexible board 2 Flexible board 3 Rigid board 4 Outer lead 5 Inspection pad 6 Outer lead hole 7 LSI 8 Polyimide film 9 Copper foil 10 Copper clad laminate 11 Prepreg 12 Through through hole 13 Solder ball 14 Probe card 15 Probe 16 , 19 sealing resin 17 mounting pad 18 motherboard
Claims (6)
積層板よりなるリジッド基板に半導体装置が搭載され、前記銅張積層板はエポキシ系樹脂を含浸させたガラスク
ロスを用いて構成され、 前記リジッド基板の外周端から外側に前記フレキシブル
基板が突設されており、 前記フレキシブル基板上には入出力端子であるアウター
リードがパターン形成され、 前記アウターリードは検査パッドで終端されていること
を特徴とする半導体パッケージの構造。1. A copper-clad integrally formed with a flexible substrate
A semiconductor device is mounted on a rigid substrate made of a laminate,The copper-clad laminate is made of glass resin impregnated with epoxy resin.
It is composed using Ross, The flexible board extends outward from the outer peripheral end of the rigid substrate.
A board is protruded, and an outer serving as an input / output terminal is provided on the flexible board.
The leads are patterned and the outer leads are terminated with test pads
The structure of a semiconductor package characterized by the above-mentioned.
板と一体形成される銅張積層板よりなるリジッド基板と
を有し、少なくとも内層に信号層を一層以上有する、リ
ジッド・フレキシブル基板において、前記銅張積層板はエポキシ系樹脂を含浸させたガラスク
ロスを用いて構成され、 前記フレキシブル基板が前記リジッド基板四辺の端面か
ら出ている構造とされ、 前記フレキシブル基板上に接続用のアウターリードが前
記リジッド基板から外へ向かう方向へ形成され、 前記アウターリードと直交するように前記フレキシブル
基板に溝孔が設けられ、 前記溝孔を跨いだ前記アウターリードが矩形の銅箔で終
端されており、 前記リジッド基板上に一つのベアチップが実装されたこ
とを特徴とするＬＳＩパッケージの構造。2. A flexible substrate and said flexible substrate
Rigid board consisting of a copper-clad laminate integrally formed with the board
Having at least one signal layer in the inner layer.
In a flexible board,The copper-clad laminate is made of glass resin impregnated with epoxy resin.
It is composed using Ross, Whether the flexible board is an end face of four sides of the rigid board
Outer leads for connection on the flexible substrate
The flexible substrate is formed in a direction outward from the rigid substrate and is orthogonal to the outer lead.
A groove is formed in the substrate, and the outer lead straddling the groove is terminated with a rectangular copper foil.
One bare chip is mounted on the rigid board.
And a structure of the LSI package.
と一体に形成される銅張積層板よりなるリジッド基板と
を有し、少なくとも内層に信号層を一層以上有する、リ
ジッド・フレキシブル基板において、前記銅張積層板はエポキシ系樹脂を含浸させたガラスク
ロスを用いて構成され、 前記フレキシブル基板が前記リジッド基板四辺の端面か
ら出ている構造とされ、 前記フレキシブル基板上に接続用のアウターリードが、
前記リジッド基板から外へ向かう方向へ形成され、 前記アウターリードと直交するように前記フレキシブル
基板に溝孔が設けられ、 前記溝孔を跨いだアウターリードが矩形の銅箔で終端さ
れており、 前記リジッド基板上に、少なくとも一つのベアチップと
１又は複数のＬＳＩが実装されたことを特徴とするマル
チチップモジュールの構造。3. A flexible substrate and the flexible substrate
Rigid board consisting of a copper-clad laminate integrally formed with
Having at least one signal layer in the inner layer.
In a flexible board,The copper-clad laminate is made of glass resin impregnated with epoxy resin.
It is composed using Ross, Whether the flexible board is an end face of four sides of the rigid board
Outer lead for connection on the flexible substrate,
The flexible substrate is formed in a direction outward from the rigid board, and is orthogonal to the outer lead.
A groove is formed in the substrate, and the outer lead straddling the groove is terminated with a rectangular copper foil.
And at least one bare chip on the rigid substrate.
One or more LSIs are mounted.
The structure of the chip module.
と一体形成される銅張積層板よりなるリジッド基板とを
有するリジッド・フレキシブル基板において、前記銅張積層板はエポキシ系樹脂を含浸させたガラスク
ロスを用いて構成され、 前記フレキシブル基板が前記リジッド基板の外周に突設
され、 前記突出したフレキシブル基板には、複数のアウターリ
ードが前記リジッド基板の辺に直交する方向に延在して
並置され、 前記アウターリードの長手方向と直交する方向に、前記
突設したフレキシブル基板に溝孔が設けられ、 前記アウターリードは前記溝孔を跨いで前記突設したフ
レキシブル基板の縁部に設けられた検査用パッドで終端
し、 前記リジッド基板上に搭載した少なくとも一つの半導体
装置のパッドと前記アウターリードとが電気的に接続さ
れていることを特徴とする半導体パッケージの構造。4. A flexible substrate and said flexible substrate
And a rigid board made of a copper-clad laminate integrally formed
In the rigid flexible substrate havingThe copper-clad laminate is made of glass resin impregnated with epoxy resin.
It is composed using Ross, The flexible substrate protrudes from the periphery of the rigid substrate
The protruding flexible substrate has a plurality of outer
The board extends in a direction perpendicular to the side of the rigid substrate.
Juxtaposed, the direction perpendicular to the longitudinal direction of the outer lead,
A groove is provided in the protruding flexible substrate, and the outer lead straddles the groove so as to extend over the groove.
Terminating at the test pad provided on the edge of the flexible board
And at least one semiconductor mounted on the rigid substrate
The pads of the device and the outer leads are electrically connected.
The structure of a semiconductor package, which is characterized in that:
ーリード端部から所定の位置で、好ましくは前記溝孔部
で切断され、且つ前記アウターリードが成型され、前記
アウターリードの端部が前記マザーボードの搭載パッド
と接合される、ことを特徴とする請求項４記載の半導体
パッケージの構造。5. At the time of mounting on a motherboard, the outer lead is cut at a predetermined position from the end of the outer lead, preferably at the slot, and the outer lead is molded. 5. The structure of a semiconductor package according to claim 4, wherein the structure is joined to a mounting pad.
体パッケージの構造において、前記リジッド基板が前記
フレキシブル基板に熱プレスで一体に形成されてなる半
導体パッケージの構造。6. The semiconductor package structure according to claim 1, wherein said rigid substrate is formed integrally with said flexible substrate by hot pressing.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14354897A JP3019027B2 (en) | 1997-05-16 | 1997-05-16 | Structure of IC package using rigid / flexible substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14354897A JP3019027B2 (en) | 1997-05-16 | 1997-05-16 | Structure of IC package using rigid / flexible substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10321760A JPH10321760A (en) | 1998-12-04 |
| JP3019027B2 true JP3019027B2 (en) | 2000-03-13 |
Family
ID=15341314
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14354897A Expired - Fee Related JP3019027B2 (en) | 1997-05-16 | 1997-05-16 | Structure of IC package using rigid / flexible substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3019027B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007183164A (en) | 2006-01-06 | 2007-07-19 | Fujitsu Ltd | Semiconductor integrated circuit device and its test method |
| CN102356703B (en) | 2009-03-19 | 2015-05-13 | 株式会社村田制作所 | Circuit board and mother laminated body |
-
1997
- 1997-05-16 JP JP14354897A patent/JP3019027B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH10321760A (en) | 1998-12-04 |
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