JPH11142872A - Liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a liquid crystal display device capable of reducing the number of parts, simplifying processes and surely fixing a frame and a printed circuit board and having automatizable fixed structure. SOLUTION: In the case of fixing a liquid crystal panel PNL constituted of holding a liquid crystal layer between a pair of opposed transparent substrateds SUB1, SUB2 at least one of which has a pixel selecting electrode, a pair of polarizing plates POL1, POL2 arranged through the panel PNL, a printed circuit board PCP3 fitted to the peripheral edge of the panel PNL, connected to the electrode of the panel PNL through a tape carrier pad TCP3 and loading electronic parts for impressing various signal voltages for display, and a back light arranged on the back of the panel PNL by the use of a frame SHD, the electronic parts EP loaded on the board PCB3 is provided with a spacer function for filling a gap between the frame SHD and the board PCB3 and fixing them.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device, which does not require a frame for forming a housing of the liquid crystal display device and a spacer for fixing a circuit board accommodated in the housing, thereby reducing the number of parts. The present invention relates to a liquid crystal display device in which the manufacturing process is reduced and the manufacturing process is simplified.

[0002]

2. Description of the Related Art A high-definition and color displayable liquid crystal display device for a notebook computer or a computer monitor includes a liquid crystal panel, an upper polarizing plate and a lower polarizing plate disposed with the liquid crystal panel interposed therebetween, and the liquid crystal display. A printed circuit board mounted on the periphery of the panel and mounted with electronic components for applying various signal voltages for display by connecting between the electrodes of the liquid crystal panel using a tape carrier pad, and a back surface of the liquid crystal panel The backlight installed in the camera is fixed by upper and lower frames and integrated.

This type of liquid crystal display device basically forms a so-called liquid crystal panel in which a liquid crystal layer is sandwiched between two substrates at least one of which is made of transparent glass or the like, and is formed on the substrate of the liquid crystal panel. A type in which predetermined voltages are selectively applied to the various electrodes for pixel formation to turn on and off predetermined pixels (simple matrix), the various electrodes and active elements for pixel selection are formed, and the active elements are selected. Accordingly, it is broadly classified into a form (active matrix) for turning on and off a predetermined pixel.

The latter active matrix type liquid crystal display device has become the mainstream of the liquid crystal display device because of its contrast performance, high-speed display performance and the like. A conventional active matrix type liquid crystal display device employs a so-called vertical electric field method in which an electric field for changing the orientation direction of a liquid crystal layer is applied between an electrode formed on one substrate and an electrode formed on the other substrate. I was

In recent years, a so-called in-plane switching (IPS) liquid crystal display device has been realized in which the direction of an electric field applied to a liquid crystal layer is substantially parallel to the substrate surface. As this in-plane switching type liquid crystal display device, a device in which a very wide viewing angle is obtained by using a comb electrode on one of two substrates is known (Japanese Patent Publication No. 63-21907, US Patent No. 4345249).

FIG. 16 is an exploded perspective view for explaining an overall configuration example of the liquid crystal display device.
This is to explain a specific structure of a liquid crystal display device (module: MDL) in which a backlight and other components are integrated.

SHD is an upper frame (also referred to as a shield case or metal frame) made of a metal plate, WD is a display window, INS1 to 3 are insulating sheets, PCB1 to 3 are circuit boards (PCB1 is a drain side circuit board: video signal line). Driving circuit board, PCB2 is gate side circuit board, PCB3 is interface circuit board), JN1-3 are circuit boards PC
Joiner for electrically connecting B1 to B1, TCP1,
TCP2 is a tape carrier package, PNL is a liquid crystal display panel, POL is an upper polarizing plate, GC is a rubber cushion,
ILS is a light shielding spacer, PRS is a prism sheet, SP
S is a diffusion sheet, GLB is a light guide plate, RFS is a reflection sheet, MCA is a lower frame (lower case: mold frame) formed by integral molding, MO is an opening of MCA, and BAT is a double-sided adhesive tape. The liquid crystal display module MDL is assembled by stacking the diffusion plate members in the above arrangement. The illustration of the light source lamp is omitted.

This liquid crystal display device (liquid crystal display module MDL) has two frames, a lower frame MCA and an upper frame SHD.
Having a housing made of various kinds of storage and holding members, and an insulating sheet I
NS1-3, circuit boards PCB1-3, liquid crystal display panel P
NL is stored and fixed, and the lower frame MCA storing the backlight composed of the light guide plate GLB and the like is attached to the upper frame SH.
D.

An electronic component such as an integrated circuit chip for driving each pixel of the liquid crystal display panel PNL is mounted on the video signal line driving circuit board PCB1, and an interface circuit board PCB3 is provided with an image signal from an external host. An integrated circuit chip for receiving and receiving a control signal such as a timing signal, a timing converter (TCON) for processing a timing to generate a clock signal, and other electronic components such as a capacitor and a resistor are mounted.

The clock signal generated by the timing converter is supplied to an integrated circuit chip mounted on the video signal line driving circuit board PCB1.

The interface circuit board PCB3 and the video signal line driving circuit board PCB1 are multilayer wiring boards, and the clock signal line CLL is connected to the interface circuit board PCB3 and the video signal line driving circuit board PC
It is formed as an inner wiring of B1.

The liquid crystal display panel PNL has a drain-side circuit board PCB1, a gate-side circuit board PCB2, and an interface circuit board PC for driving TFTs.
B3 is connected by tape carrier packages TCP1 and TCP2, and the circuit boards are connected by joiners JN1, JN2, JN3.

[0013]

An antistatic film laminated on the surface of the liquid crystal panel PNL is provided between the upper frame SHD and the drain-side circuit board PCB1, the gate-side circuit board PCB2, and the interface circuit board PCB3. A partly conductive spacer SPC for grounding is interposed with a double-sided adhesive tape, and these circuit boards and the upper frame SHD are fixed.

FIG. 17 is a sectional view of a principal part for explaining a fixed portion between the circuit board and the upper frame.
SUB2 is an upper substrate, POL1 is a lower deflection plate, POL2 is an upper deflection plate, EP is an electronic component, CT is an interface connector, TP / SPC is a spacer with an adhesive tape, and CHI is a semiconductor chip.

The interface circuit board PCB3 is connected to one substrate SUB1 of the liquid crystal panel PNL by a tape carrier pad (TCP) on which an IC chip CHI is mounted.
3 and is fixed to the upper frame SHD by a spacer TP / SPC with an adhesive tape.

In particular, the interface circuit board PC
B3 is provided with an interface connector CT for inputting a display signal from a host computer.

FIGS. 18A and 18B are explanatory diagrams of a configuration example of an interface circuit board. FIG. 18A shows a state in which only a hybrid integrated circuit is mounted, and FIG. 18A shows a connector CT, a signal integrated circuit TCON, a power supply circuit, a capacitor and a resistor. 5 shows a state in which electronic components EP and the like are mounted. JP31 and JP32 are joiner connection parts.

The signal integrated circuit TCON performs data processing on image information sent from the host to convert the image information into a driving signal for the liquid crystal panel and generates a timing pulse, so that the drain-side circuit board PCB1 and the gate-side circuit board PCB2 are processed. Display is performed by driving control.

After assembling the liquid crystal display device, display signals and the like are supplied by inserting a connection line extending from the host side into the interface connector CT. Mechanical stress is applied to the circuit board PCB3 and the TCP when the connection line extending from the host side to the CT is inserted and removed.

This mechanical stress may cause a disconnection in the TCP, resulting in display failure.

Conventionally, as described above, a P is provided between each circuit board including the interface circuit board and the upper frame.
A spacer such as ET (polyethylene terephthalate resin) is interposed and fixed together with an adhesive tape.

However, with such means, the man-hours for attaching the spacer are increased, and the positioning accuracy is poor due to the manual sticking operation, and the spacer may fall off during the operation.

Further, it is difficult to automate such attachment of the spacer and the adhesive tape.

An object of the present invention is to provide a liquid crystal display device having a fixing structure capable of reliably fixing a circuit board, especially an interface circuit board, and solving the problem by solving the above-mentioned conventional problems.

[0025]

The above object is achieved, in particular, by fixing the interface circuit board and the upper frame by providing the electronic component itself mounted on the circuit board with a spacer function.

That is, according to the present invention, there is provided a liquid crystal panel having a liquid crystal layer sandwiched between a pair of transparent substrates having an electrode for selecting a pixel on at least one of them facing each other, and is arranged with the liquid crystal panel interposed therebetween. An electronic component for applying various signal voltages for display by connecting the upper polarizing plate and the lower polarizing plate and the electrodes of the liquid crystal panel attached to the periphery of the liquid crystal panel using a tape carrier pad. In a liquid crystal display device in which a mounted circuit board and a backlight installed on the back surface of the liquid crystal panel are fixed by upper and lower frames, an electronic component mounted on the circuit board is provided between the frame and the circuit board. Spacer function for filling and fixing the gap.

By interposing an adhesive or an adhesive tape between the electronic component and the upper frame, both can be securely fixed.

The present invention relates to a drain-side circuit board PC
The present invention is not limited to a so-called active matrix type liquid crystal display device having B1 and a gate side circuit board PCB2, but can be similarly applied to a simple matrix type and other liquid crystal display devices having TCP.

According to this configuration, the disconnection of the TCP due to the insertion / removal of the interface connector can be prevented, the number of parts can be reduced, the assembling work can be simplified, and the mounting of the electronic parts can be automated, so that the work process can be made more efficient. A highly reliable liquid crystal display device can be obtained.

[0030]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described below in detail with reference to examples.

FIG. 1 is a schematic plan view for explaining the overall structure of one embodiment of a liquid crystal display device according to the present invention, wherein SHD indicates an upper frame, PNL indicates a liquid crystal panel, CT indicates an interface connector, and LPC indicates a lamp code. .

The liquid crystal panel 2 is sandwiched and fixed between the upper and lower frames together with the backlight and other components.

An interface circuit board is housed inside the left side of the figure, and an interface connector CT is mounted on the interface circuit board.

FIG. 2 is a sectional view taken along the line AA in FIG. 1, and the same reference numerals as those in FIG. 17 correspond to the same functional parts.

In this embodiment, the liquid crystal panel PML has a TC
Interface circuit board PCB3 connected via P
An adhesive tape TP was attached to the top surface of the electronic component EP mounted on the device and was fixed to the back surface of the upper frame SHD.

According to this configuration, since the conventional spacer is not provided between the electronic component EP of the interface circuit board PCB3 and the upper frame SHD, the positioning of the spacer in the assembling process is unnecessary, and the operation is not performed. Since the spacers do not fall off, the workability is extremely good.

Further, as another embodiment of the present invention, an adhesive may be applied instead of the adhesive tape TP to directly fix the electronic component EP and the upper frame SHD.

According to each of the above-described embodiments, since the electronic component which can be handled by the automatic component mounting machine is used as a member for filling the gap between the interface circuit board PCB3 and the upper frame and fixing them, the work process Is simplified,
It is possible to provide a liquid crystal display device which can be securely fixed at low cost and has high reliability.

The present invention is not limited to the above-described fixing of the interface circuit board PCB3 to the upper frame, but can be similarly applied to the fixing of another circuit board to the upper frame. Also, in a liquid crystal display device in which a circuit board is disposed on the back surface of a liquid crystal panel, electronic components mounted on the circuit board are fixed to a lower frame (a lower case or an intermediate case in a case using a lower case or an intermediate case) as spacers. Can be configured.

As described above, according to the embodiment of the present invention, since the electronic parts to be soldered to the interface circuit board and other circuit boards are used as spacers for fixing to the frame, the insertion and removal of the interface connector are performed. Alternatively, it is possible to avoid a disconnection of the TCP when handling such that a mechanical stress is applied to the TCP during an assembling operation or the like, and to simplify the assembling process to obtain a highly reliable liquid crystal display device.

Next, the details of the liquid crystal display device of the present invention are shown in FIG.
This will be described with reference to FIG.

FIG. 3 is a plan view showing one pixel of an active matrix type color liquid crystal display device which is an example of the liquid crystal display device of the present invention, a light-shielding region of the black matrix BM, and its periphery.

As shown in FIG. 3, each pixel has a scanning signal line (gate signal line or horizontal signal line) GL, a counter voltage signal line (counter electrode line) CL, and two adjacent video signal lines (drain). The signal line or the vertical signal line) is arranged in an intersecting region with the DL (in a region surrounded by four signal lines).

Each pixel includes a thin film transistor TFT, a storage capacitor Cstg, a pixel electrode PX, and a counter electrode CT. The scanning signal lines GL and the counter voltage signal lines CL extend in the left-right direction in FIG. The video signal lines DL extend in the up-down direction, and a plurality of video signal lines DL are arranged in the left-right direction. The pixel electrode PX is connected to the thin film transistor TFT, and the counter electrode CT is integrated with the counter voltage signal line CL.

The pixel electrode PX and the counter electrode CT are opposed to each other, and the orientation of the liquid crystal LC is controlled by an electric field between each pixel electrode PX and the counter electrode CT, and the transmitted light is modulated to control the display. The pixel electrode PX and the counter electrode CT are formed in a comb-like shape, and each is an electrode that is elongated in the vertical direction in FIG.

The number O (number of comb teeth) of the counter electrode CT in one pixel is equal to the number P (number of comb teeth) of the pixel electrode PX and O =
It is configured to always have the relationship of P + 1 (O = 2, P = 1 in this embodiment). This is because the counter electrode CT and the pixel electrode PX are alternately arranged, and the counter electrode CT is always adjacent to the video signal line DL.

Thus, the counter electrode CT and the pixel electrode PX are
The electric field lines from the video signal line DL can be shielded by the counter electrode CT so that the electric field between them is not affected by the electric field generated from the video signal line DL.

Since the potential of the counter electrode CT is always supplied from the outside by the counter voltage signal line CL, the potential is stable. Therefore, there is almost no change in potential even adjacent to the video signal line DL. In addition, since the geometric position of the pixel electrode PX from the video signal line DL becomes farther,
The parasitic capacitance between the pixel electrode PX and the video signal line DL is greatly reduced, and the fluctuation of the pixel electrode potential Vs due to the video signal voltage can be controlled.

As a result, crosstalk (defective image quality called vertical smear) occurring in the vertical direction can be suppressed.

The electrode width W between the pixel electrode PX and the counter electrode CT
Each of p and Wc is set to 6 μm, which is set sufficiently larger than 4.5 μm which exceeds the maximum set thickness of the liquid crystal layer described later.
It is preferable to have a margin of 20% or more in consideration of processing variations in manufacturing. Therefore, it is preferable that the margin be sufficiently larger than 5.4 μm.

As a result, the electric field component applied to the liquid crystal layer parallel to the substrate surface becomes larger than the electric field component in the direction perpendicular to the substrate surface, so that an increase in the voltage for driving the liquid crystal can be suppressed. The maximum value of the electrode width Wp, Wc of each electrode is
It is preferable that the distance be smaller than the distance L between the pixel electrode PX and the counter electrode CT.

This is because if the distance between the electrodes is too small, the curvature of the lines of electric force becomes severe, and the region where the electric field component perpendicular to the substrate surface is larger than the electric field component parallel to the substrate surface increases. This is because an electric field component parallel to the above cannot be efficiently applied to the liquid crystal layer. Therefore, the pixel electrode PX and the counter electrode C
The interval L between T needs to be larger than 7.2 μm if the margin is 20%. In this embodiment, the diagonal is about 1
Since the pixel pitch is about 60 μm because the resolution is 4.5 cm (5.7 inches) and the resolution is 640 × 480 dots, the distance L> 7.2 μm by dividing the pixel into two.
Was realized.

The electrode width of the video signal line DL is set to 8 μm, which is slightly wider than the pixel electrode PX and the counter electrode CT in order to prevent disconnection, and the interval between the video signal line DL and the counter electrode CT is short-circuited. In order to prevent this, an interval of about 1 μm is provided, a video signal line DL is formed on the upper side of the gate insulating film, and a counter electrode CT is formed on the lower side.

On the other hand, the electrode interval between the pixel electrode PX and the counter electrode CT changes depending on the liquid crystal material used. this is,
Since the electric field strength that achieves the maximum transmittance varies depending on the liquid crystal material, the electrode spacing is set according to the liquid crystal material, and within the range of the maximum amplitude of the signal voltage set by the withstand voltage of the video signal driving circuit (signal side driver) used. , So that the maximum transmittance can be obtained. When a liquid crystal material described later is used, the electrode interval is about 15 μm.

In this configuration example, a black matrix BM is formed on the gate line GL, the counter voltage signal line CL, the thin film transistor TFT, the drain line DL, and between the drain line DL and the counter electrode CT in plan view.

<< Cross-Sectional Structure of Matrix (Pixel) >> FIG. 4 shows a thin film transistor TF taken along the line 4-4 in FIG.
5, FIG. 5 is a cross-sectional view of the storage capacitor Cstg taken along the line 5-5 in FIG. 3, and FIG. It is sectional drawing of a part.

As shown in FIG. 6, a thin film transistor TFT, a storage capacitor Cstg (not shown) and an electrode group C are provided on the lower transparent glass substrate SUB1 side with respect to the liquid crystal layer LC.
T, PX are formed, and a color filter FIL and a black matrix B for shading are formed on the upper transparent glass substrate SUB2 side.
An M pattern is formed. Although not publicly known,
As proposed in Japanese Patent Application No. 7-198349 by the same applicant, it is also possible to form the pattern of the light-shielding black matrix BM on the lower transparent glass substrate SUB1 side.

On the inner surface (on the liquid crystal LC side) of each of the transparent glass substrates SUB1 and SUB2, alignment films ORI11 and ORI12 for controlling the initial alignment of the liquid crystal are provided. Polarizing plates POL1 and POL2 whose polarization axes are orthogonally arranged (crossed Nicol arrangement) are provided on the outer surfaces of each.

Next, the lower transparent glass substrate SUB1 side (T
The configuration of the FT substrate will be described in detail.

TFT Substrate << Thin Film Transistor >> The thin film transistor TFT operates so that the channel resistance between the source and the drain decreases when a positive bias is applied to the gate electrode GT, and the channel resistance increases when the bias is zero.

As shown in FIG. 4, the thin-film transistor TFT has a gate electrode GT, a gate insulating film GI, and an i-type (intrinsic, which is not doped with a conductivity type determining impurity) amorphous silicon (Si). Type semiconductor layer AS, a pair of source electrode SD1, drain electrode SD
2

It should be understood that the source and the drain are originally determined by the bias polarity between them, and in the circuit of this liquid crystal display device, the polarity is inverted during the operation, so that the source and the drain are interchanged during the operation. However, in the following description, one is fixed and the other is fixed as a drain for convenience.

<< Gate Electrode GT >> The gate electrode GT is formed continuously with the scanning signal line GL, and a part of the scanning signal line GL is configured as the gate electrode GT. The gate electrode GT is a portion exceeding the active region of the thin film transistor TFT, and is formed larger than that so as to completely cover the i-type semiconductor layer AS (as viewed from below).

Thus, in addition to the role of the gate electrode GT itself, the gate electrode GT is designed so that external light and backlight do not hit the i-type semiconductor layer AS. In this example, the gate electrode GT is formed of a single-layer conductive film g1. As the conductive film g1, for example, an aluminum (Al) film formed by sputtering is used, and an anodic oxide film AOF of Al is provided thereon.

<< Scanning Signal Line GL >> The scanning signal line GL is formed of the conductive film g1. The conductive film g1 of the scanning signal line GL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, and is integrally formed. Through this scanning signal line GL, a gate voltage Vg is supplied from an external circuit to the gate electrode GT.

An anodic oxide film AOF of Al is also provided on the scanning signal line GL. The portion that intersects with the video signal line DL is made thin to reduce the probability of short-circuit with the video signal line DL, and is made bifurcated so that even if it is short-circuited, it can be separated by laser trimming.

<< Counter Electrode CT >> The counter electrode CT is formed of the same conductive film g1 as the gate electrode GT and the scanning signal line GL. Also, an anodic oxide film A of Al is formed on the counter electrode CT.
An OF is provided. The counter electrode CT has an anodic oxide film A
Since they are completely covered with the OF, even if they are brought as close as possible to the video signal lines, they will not be short-circuited.

Further, they may be configured to cross each other. The counter electrode CT is configured to apply a counter voltage Vcom. In this embodiment, the counter voltage Vc
om is a potential lower than an intermediate DC potential between the minimum level drive voltage Vdmin and the maximum level drive voltage Vdmax applied to the video signal line DL by a feedthrough voltage ΔVs generated when the thin film transistor element TFT is turned off. However, if you want to reduce the power supply voltage of the integrated circuit used in the video signal drive circuit to about half,
An AC voltage may be applied.

<< Counter Voltage Signal Line CL >> Counter Voltage Signal Line C
L is composed of the conductive film g1. The conductive film g1 of the counter voltage signal line CL is formed in the same manufacturing process as the conductive film g1 of the gate electrode GT, the scanning signal line GL, and the counter electrode CT, and is formed integrally with the counter electrode CT.

The counter voltage Vcom is supplied from an external circuit to the counter electrode CT through the counter voltage signal line CL. or,
An anodic oxide film AOF of Al is also provided on the counter voltage signal line CL. Note that the portion that intersects with the video signal line DL is
Like the scanning signal line GL, it may be made thinner to reduce the probability of short-circuiting with the video signal line DL, or it may be split into two parts so that even if it is short-circuited, it can be separated by laser trimming.

<< Insulating Film GI >> The insulating film GI is used as a gate insulating film for applying an electric field to the semiconductor layer AS together with the gate electrode GT in the thin film transistor TFT. The insulating film GI is formed above the gate electrode GT and the scanning signal line GL.

As the insulating film GI, for example, plasma CVD
The silicon nitride film formed by
It is formed to a thickness of nm (240 nm in this embodiment).

The gate insulating film GI is formed in the matrix portion A
R is formed so as to surround the entirety of R, and the peripheral portion is removed so as to expose the external connection terminals DTM and GTM. Also,
The insulating film GI also contributes to electrical insulation between the scanning signal lines GL and the counter voltage signal lines CL and the video signal lines DL.

<< i-type semiconductor layer AS >>
Is amorphous silicon and is formed with a thickness of 20 to 220 nm (about 200 nm in this embodiment). Layer d
Numeral 0 denotes an N (+)-type amorphous silicon semiconductor layer doped with phosphorus (P) for ohmic contact. An i-type semiconductor layer AS is present on the lower side, and a conductive film d1 (d2) is present on the upper side. It is left only in places.

The i-type semiconductor layer AS is also provided between the scanning signal line GL and the intersection of the opposing signal line CL and the video signal line DL. The i-type semiconductor layer AS at the intersection reduces a short circuit between the scanning signal line GL and the opposing signal line CL and the video signal line DL at the intersection.

<< Source electrode SDI, Drain electrode SD
2 >> Each of the source electrode SDI and the drain electrode SD2 is composed of a conductive film d1 in contact with the N (+) type semiconductor layer d0 and a conductive film d2 formed thereon.

The conductive film d1 is formed with a thickness of 50 to 100 nm (about 60 nm in this embodiment) using a chromium (Cr) film formed by sputtering. Since the stress increases when the Cr film is formed to have a large thickness, the Cr film has a thickness of 200 nm.
It is formed in a range that does not exceed a certain thickness. Cr film is N
To improve the adhesion to the (+) type semiconductor layer d0,
2 is used for the purpose of a so-called barrier layer that prevents Al from diffusing into the N (+) type semiconductor layer d0.

As the conductive film d1, a refractory metal (Mo, Ti, Ta, W) film or a refractory metal silicide (MoSi ₂ , TiSi ₂ , TaSi ₂ , WSi ₂ ) film may be used in addition to the Cr film. .

The conductive film d2 has a thickness of 30
It is formed to a thickness of 0 to 500 nm (about 400 nm in this embodiment). The Al film has a smaller stress than the Cr film and can be formed to have a large thickness.
It has functions of reducing the resistance values of D1, the drain electrode SD2, and the video signal line DL, and ensuring the step over caused by the gate electrode GT and the i-type semiconductor layer AS (to improve the step coverage).

After patterning the conductive films d1 and d2 with the same mask pattern, the N (+) type semiconductor layer d0 is removed using the same mask or using the conductive films d1 and d2 as a mask. That is, the i-type semiconductor layer AS
The remaining N (+) type semiconductor layer d0 is a conductive film d1,
Portions other than the conductive film d2 are removed by self-alignment.
At this time, since the N (+)-type semiconductor layer d0 is etched so as to completely remove its thickness, the i-type semiconductor layer A is removed.
Although the surface portion of S is also slightly etched, its degree may be controlled by the etching time.

<< Video Signal Line DL >> The video signal line DL is composed of the second conductive film d2 and the third conductive film d3 in the same layer as the source electrode SD1 and the drain electrode SD2. The video signal line DL is formed integrally with the drain electrode SD2.

<< Pixel Electrode PX >> The pixel electrode PX is the second conductive film d of the same layer as the source electrode SD1 and the drain electrode SD2.
2, the third conductive film d3. Also, the pixel electrode P
X is formed integrally with the source electrode SD1.

<< Storage Capacitor Cstg >> The pixel electrode PX is formed so as to overlap the counter voltage signal line CL at the end opposite to the end connected to the thin film transistor TFT. This superposition is, as is clear from FIG.
A storage capacitor (capacitance element) Cstg is formed in which the pixel electrode PX is one electrode PL2 and the counter voltage signal line CL is the other electrode PL1. The dielectric film of the storage capacitor Cstg includes an insulating film GI used as a gate insulating film of the thin film transistor TFT and an anodic oxide film AOF.

As shown in FIG. 3, the storage capacitor Cstg is formed in the conductive film g1 of the counter voltage signal line CL in plan view.

In this case, the storage capacitor Cstg is made of Al because the material of the electrode positioned below the insulating film GI is formed of Al and the surface thereof is anodized. It is possible to obtain a storage capacitor which is less likely to cause adverse effects due to a point defect (short-circuit with an electrode positioned on the upper side) caused by a so-called hillock or the like.

<< Protective Film PSV1 >> Thin Film Transistor TF
On T, a protective film PSV1 is provided. Protective film PS
V1 is formed mainly to protect the thin film transistor TFT from moisture and the like, and uses a material having high transparency and good moisture resistance. The protective film PSV1 is formed of, for example, a silicon oxide film or a silicon nitride film formed by a plasma CVD apparatus, and has a thickness of about 500 nm.

The protective film PSV1 is formed so as to surround the entire matrix portion AR, and the peripheral portion is connected to the external connection terminal DT.
M and GTM have been removed to expose. Regarding the thickness relationship between the protective film PSV1 and the gate insulating film GI, the former is made thicker in consideration of the protective effect, and the latter is made thinner in consideration of the transconductance gm of the transistor.

Color Filter Substrate Next, the structure of the upper transparent glass substrate SUB2 (color filter substrate) will be described in detail with reference to FIGS.

<< Light-shielding film BM >> Upper transparent glass substrate SUB
On the second side, an unnecessary gap (pixel electrode PX and counter electrode CT)
Transmitted light from the gap other than the gap between
A light-shielding film BM (a so-called black matrix) is formed so as not to lower the contrast ratio and the like. Light shielding film BM
Also serves to prevent external light or backlight light from entering the i-type semiconductor layer AS. That is, the i-type semiconductor layer AS of the thin film transistor TFT is sandwiched between the upper and lower light-shielding films BM and the large gate electrode GT, so that external natural light or backlight does not shine.

The closed rectangular outline of the light-shielding film BM shown in FIG. 3 indicates an opening on the inside of which no light-shielding film BM is formed. This contour pattern is an example.

In a horizontal electric field type liquid crystal display device, a black matrix having the highest possible resistance is suitable.
Generally, a resin composition is used. For this resistance standard,
Although it is not publicly known, Japanese Patent Application No. 7-1919 filed by the same applicant
No. 94. That is, if the specific resistance of the liquid crystal composition LC is described as 10 ^N as 10 ^N , then the specific resistance of the black matrix BM is 10 ^N Ω · cm or more, and the specific resistance of the black matrix BM is 10 M
When written as 10 ^M and 10 ^M Ω · cm or more and, N ≧
9, a relationship that satisfies M ≧ 6. Alternatively, N ≧ 13,
It is desirable that the relationship satisfy M ≧ 7.

It is also desirable to use a resin composition as the material for forming the black matrix from the viewpoint of reducing the surface reflection of the liquid crystal display device.

Further, as compared with the case where a metal film of Cr or the like is used for the black matrix, the step of etching the metal film is not required, so that the manufacturing process of the color filter substrate can be simplified. When a metal film is used, the manufacturing steps are: 1) metal film formation, 2) resist coating, 3) exposure, 4) development, 5)
Metal film etching, 6) resist stripping.

On the other hand, when a resin is used, the manufacturing process is as follows.
1) resin application, 2) exposure, and 3) development, and the process can be significantly shortened.

However, the resin composition has a lower light-shielding property than the metal film. Increasing the thickness of the resin improves the light-shielding properties, but increases the variation in the thickness of the black matrix. This means that, for example, when there is a thickness variation of ± 10%, when the thickness of the black matrix is 1.0 μm, ± 0.1 μm,
This is because when it is 2 μm, it becomes ± 0.2 μm.

When the thickness of the black matrix is increased, variation in the thickness of the color filter substrate increases, and it becomes difficult to improve the gap accuracy of the liquid crystal display substrate.
For the above reasons, it is desirable that the thickness of the resin is 2 μm or less.

In order to increase the OD value to about 4.0 or more at a film thickness of 1 μm, for example, when blackening is performed by increasing the carbon content, the specific resistance value of the black matrix BM is about 10 ⁶
Ω · cm or less and cannot be used at present. OD
The value can be defined as the value obtained by multiplying the extinction coefficient by the film thickness.

For this reason, in this example, as a material of the light-shielding film BM, a resin composition in which a black inorganic pigment is mixed into a resist material is used, and is formed with a thickness of about 1.3 ± 0.1 μm. . Examples of the inorganic pigment include palladium and electroless plated Ni. Furthermore, black matrix B
The specific resistance of M is about 10 ⁹ Ω · cm, and the OD value is about 2.0
And

The calculation results of the light transmission amount when this resin composition black matrix BM is used are shown below.

OD value = log (100 / Y) Y = ∫A (λ) · B (λ) · C (λ) dλ / ∫A (λ)
C (λ) dλ Here, A is the visibility, B is the transmittance, C is the light source spectrum, and λ is the wavelength of the incident light.

In the case where light is shielded by a film having an OD value of 2.0, Y = 1% is obtained from the above equation (1), and the incident light intensity is 4000 cd /
Assuming m ² , about 40 cd / m ² of light will be transmitted. This light intensity is sufficiently bright to be visually recognized by humans.

The light-shielding film BM is also formed in a frame shape in the peripheral portion, and its pattern is a pattern shown in FIG.
Are formed continuously with the pattern of the matrix section shown in FIG.

<< Color Filter FIL >> The color filter FIL is formed in a stripe shape by repeating red, green, and blue at a position facing the pixel. The color filter FIL is formed so as to overlap the edge portion of the light shielding film BM.

The color filter FIL can be formed, for example, as follows. First, the upper transparent glass substrate SU
A dye base such as an acrylic resin is formed on the surface of B2, and the dye base other than the red filter formation region is removed by photolithography. Thereafter, the dyed base material is dyed with a red dye and subjected to a fixing treatment to form a red filter R. Next, the green filter G,
Blue filters B are sequentially formed.

<< Overcoat Film OC >> The overcoat film OC is provided to prevent the dye of the color filter FIL from leaking to the liquid crystal LC, and to flatten the steps formed by the color filter FIL and the light shielding film BM. The overcoat film OC is formed of, for example, a transparent resin material such as an acrylic resin or an epoxy resin.

Liquid Crystal Layer and Polarizing Plate Next, the liquid crystal layer, the alignment film, the polarizing plate and the like will be described.

<< Liquid Crystal Layer >> As the liquid crystal material LC, the dielectric anisotropy Δ △ is positive and its value is 13.2, and the refractive index anisotropy Δn
Is 0.081 (589 nm, 20 ° C.), a dielectric anisotropy Δ △ is negative and the value is −7.3, and a refractive index anisotropy Δn is 0.053 (589 nm, 20 ° C.). The nematic liquid crystal of C) was used.

The thickness (gap) of the liquid crystal layer was more than 2.8 μm and less than 4.5 μm when the dielectric anisotropy Δε was positive.
This is because the retardation Δn · d exceeds 0.25 μm.
When it is less than 32 μm, a dielectric constant characteristic having almost no wavelength dependence within the visible light range is obtained, and most of the liquid crystal having a positive dielectric anisotropy Δ △ has a birefringence anisotropy Δn of 0. 0.07 or more
This is because it is less than 09.

On the other hand, when the dielectric anisotropy Δ △ was negative, the thickness (gap) of the liquid crystal layer was set to more than 4.2 μm and less than 8.0 μm. This is because, like the liquid crystal having a positive dielectric anisotropy Δε, the retardation Δn · d exceeds 0.25 μm by 0.32 μm.
Most of the liquid crystal having a negative dielectric anisotropy Δ △ has a birefringence anisotropy Δn of more than 0.04 to suppress the dielectric anisotropy Δ △ is negative.
This is because it is less than 6.

Further, the maximum transmittance can be obtained when the liquid crystal molecules are rotated by 45 ° from the rubbing direction to the electric field direction by a combination of an alignment film and a polarizing plate described later. The thickness (gap) of the liquid crystal layer is controlled by polymer beads.

Further, the liquid crystal material LC is not particularly limited as long as it is a nematic liquid crystal. Dielectric anisotropy △ ε
The larger the value, the lower the driving voltage, and the smaller the refractive index anisotropy Δn, the smaller the thickness (gap) of the liquid crystal layer.
Can be made thicker, the liquid crystal filling time can be shortened, and the gap variation can be reduced.

<< Orientation Film >> Polyimide is used as the orientation film ORI. The rubbing direction RDR is parallel to each other between the upper and lower substrates, and the angle φLC between the applied electric field direction EDR and the angle φLC.
Is 75 °. FIG. 7 shows the relationship.

The rubbing direction RDR and the applied electric field direction E
The angle with DR is 45 ° or more and less than 90 ° when the dielectric anisotropy △ ε of the liquid crystal material is positive, and is more than 0 ° and 45 ° or less when the dielectric anisotropy △ ε is negative. Is fine.

<< Polarizing Plate >> As the polarizing plate POL, G1220DU (trade name) manufactured by Nitto Denko Corporation was used, and as shown in FIG. 6, the polarization transmission axis MAX1 of the lower polarizing plate POL1 coincided with the rubbing direction RDR. And the upper polarizer POL2
Of the polarized light transmission axis MAX2 is made orthogonal to it.

As a result, it is possible to obtain a normally closed characteristic in which the transmittance increases as the voltage applied to the pixel of the present invention (the voltage between the pixel electrode PX and the counter electrode CT) increases.

Furthermore, in the liquid crystal display device referred to as the in-plane switching method disclosed in the present invention, display abnormalities occur when a high potential such as static electricity is applied from outside the surface on the upper substrate SUB2 side. . Therefore, a layer of a transparent conductive film having a sheet resistance of 1 × 10 ⁸ Ω / □ or less is formed further above or on the surface of the upper polarizing plate POL2, or a sheet resistance of 1 × is provided between the polarizing plate and the transparent substrate. I of 10 ⁸ Ω / □ or less
Forming a layer of a transparent conductive film such as TO, or mixing conductive particles such as ITO, SnO ₂ , and In ₂ O _{3 with} the adhesive layer of the polarizing plate to reduce the sheet resistance to 1 × 10 ⁸ Ω / □ or less. It becomes necessary. Regarding this measure, it is not publicly known, but in Japanese Patent Application No. 7-264443 filed by the same applicant,
There is a detailed description of the improvement of the shield function.

<< Configuration around Matrix >> FIG. 8 is a plan view of a main portion around the matrix (AR) of the display panel PNL including the upper and lower glass substrates SUB1 and SUB2. FIG.
FIG. 3 is a cross-sectional view near the external connection terminal GTM to which the scanning circuit is connected on the left side.

In the manufacture of this panel, if the size is small, a plurality of devices are processed at the same time on a single glass substrate to improve the throughput in order to improve the throughput. If the size is large, the manufacturing equipment is shared. For each type, a glass substrate of a standardized size is processed and then reduced to a size suitable for each type. In each case, the glass is cut after passing through a single process.

FIGS. 8 and 9 show the latter example. Both FIGS. 8 and 9 show the upper and lower substrates SUB1 and SUB2 after cutting, and LN shows the edge of both substrates before cutting. .
In any case, in the completed state, the external connection terminal groups Tg, Tg
The size of the upper substrate SUB2 is limited to the inside of the lower substrate SUB1 so that d and the terminal CTM are present (the upper side and the left side in the figure) so as to expose them.

The terminal groups Tg and Td are respectively a scanning circuit connection terminal GTM and a video signal circuit connection terminal DT described later.
M and their leading wiring portions are formed by a tape carrier package TCP (FIGS. 9 and 1) on which an integrated circuit chip CHI is mounted.
0) are collectively named.

The lead wiring from the matrix section of each group to the external connection terminal section is inclined as approaching both ends. This is because the display panel P is set in the arrangement pitch of the package TCP and the connection terminal pitch in each package TCP.
This is for adjusting to the terminals DTM and GTM of the NL.

The counter electrode terminal CTM is connected to the counter electrode CT.
Is a terminal for applying a counter voltage from the outside. The counter electrode signal line CL in the matrix portion is connected to a scanning circuit terminal GTM.
, And the common voltage signal lines are grouped together by a common bus line CB to form a common electrode terminal CT
M.

Between the transparent glass substrates SUB1 and SUB2, along the edge thereof, except for the liquid crystal filling opening INJ, the liquid crystal L
A seal pattern SL is formed so as to seal C.
The sealing material is made of, for example, an epoxy resin.

The layers of the orientation films ORI1 and ORI2 are formed inside the seal pattern SL. Polarizing plates POL1, P
OL2 is formed on the outer surfaces of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively.

The etching LC is sealed in a region partitioned by the seal pattern SL between the lower alignment film ORI1 and the upper alignment film ORI2 for setting the direction of the liquid crystal molecules.
The lower alignment film ORI1 is formed above the protective film PSV1 on the lower transparent glass substrate SUB1 side.

In this liquid crystal display device, various layers are separately stacked on the lower transparent glass substrate SUB1 side and the upper transparent glass substrate SUB2 side, and a seal pattern SL is formed on the substrate SUB2.
Side, the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2 are overlapped with each other to form a seal pattern SL
The liquid crystal LC is injected from the opening INJ, the inlet INJ is sealed with an epoxy resin or the like, and the upper and lower substrates are cut to be assembled.

<< Equivalent Circuit of Entire Display Device >> FIG. 11 is a schematic explanatory diagram of peripheral circuits of a liquid crystal display device according to the present invention.
As shown in the figure, the liquid crystal display substrate is constituted by a set of a plurality of pixels in which an image display unit is arranged in a matrix,
Each pixel is configured to independently control the modulation of transmitted light from a backlight disposed behind the liquid crystal display substrate.

An active pixel area is provided on an active matrix substrate SUB1, which is one of the components of the liquid crystal display substrate.
The gate signal line GL and the counter voltage signal line CL, which extend in the x direction (row direction) and are arranged in parallel in the y direction (column direction), extend in the y direction while being insulated from the AR, and extend in the x direction. The provided drain signal line DL is formed.

Here, a unit pixel is formed in a rectangular area surrounded by each of the gate signal line GL, the counter voltage signal line CL, and the drain signal line DL.

The liquid crystal display substrate is provided with a vertical scanning circuit V and a video signal driving circuit H as external circuits, and the vertical scanning circuit V sequentially supplies a scanning signal (voltage) to each of the gate signal lines GL. From the video signal drive circuit H to the drain signal line DL in accordance with the timing.
Is supplied with a video signal (voltage).

The vertical scanning circuit V and the video signal driving circuit H are supplied with power from the liquid crystal driving power supply circuit 3 and input image information from the CPU 1 after being divided into display data and control signals by the controller 2. It is supposed to be.

<< Driving Method >> FIG. 12 is a driving waveform diagram of the liquid crystal display device of the present invention. The opposite voltage is VCH and VCL.
Value AC rectangular wave and the scanning signal VG
(I-1) The non-selection voltage of VG (i) is changed by two values of VCH and VCL every scanning period. The amplitude width of the counter voltage and the amplitude value of the non-selection voltage are the same.

The video signal voltage is a voltage obtained by subtracting 振幅 of the amplitude of the counter voltage from the voltage to be applied to the liquid crystal layer.

The counter voltage may be DC, but by converting it to AC, the maximum amplitude of the video signal voltage can be reduced, and a video signal drive circuit (signal-side driver) having a low withstand voltage can be used.

<< Operation of Storage Capacitance Cstg >> Storage Capacitance Cs
tg is written to the pixel (thin film transistor TFT
Is provided for long storage of video information (after the power is turned off).

In the method of applying an electric field parallel to the substrate surface used in the present invention, unlike the method of applying the electric field perpendicular to the substrate surface, the capacitance (the so-called liquid crystal capacitance) formed by the pixel electrode and the counter electrode is different. Since there is almost no storage, the storage Cstg is an essential component.

The storage capacitor Cstg also functions to reduce the influence of the gate potential change ΔVg on the pixel electrode potential Vs when the thin film transistor TFT switches. This situation is represented by the following equation.

ΔVs = [Cgs / (Cgs + Cstg +
Cpix)] × ΔVg where Cgs is a parasitic capacitance formed between the gate electrode GT and the source electrode SDI of the thin film transistor TFT,
Cpix represents a capacitance formed between the pixel electrode PX and the counter electrode CT, and ΔVs represents a change in pixel electrode potential due to ΔVg, a so-called feedthrough voltage.

Although the change ΔVs causes a DC component applied to the liquid crystal LC, the value can be reduced as the storage capacitance Cstg is increased.

The reduction of the DC component applied to the liquid crystal LC is as follows.
It is possible to improve the life of the liquid crystal LC and reduce so-called burn-in in which a previous image remains when the liquid crystal display screen is switched.

As described above, since the gate electrode GT is made large so as to completely cover the i-type semiconductor layer AS, the area of overlap with the source electrode SDI and the drain electrode SD2 increases, and therefore the parasitic capacitance Cgs increases. The pixel electrode potential Vs has an adverse effect of being easily affected by the gate (scanning) signal Vg. However, the storage capacity Cs
By providing tg, this disadvantage is also eliminated.

<< Manufacturing Method >> Next, a method of manufacturing the above-described liquid crystal display device on the substrate SUB1 side will be described.

FIG. 13, FIG. 14, and FIG. 15 are explanatory views of the manufacturing process of the liquid crystal display device according to the present invention. In the same figure, the central characters are the abbreviations of the process names, and the left side in FIG. The right side of the thin film transistor TFT portion shown in the drawing shows the flow of processing viewed from the cross-sectional shape near the gate terminal.

The following photographic processing shows a series of operations from application of a photoresist, through selective exposure using a mask, to development thereof, and a repeated explanation is omitted. Description will be given below according to the divided steps.

Step A (FIG. 13) Al-Pd, Al-Pd having a thickness of 300 nm is formed on a lower transparent glass substrate SUB1 made of AN635 glass (trade name).
Conductive film g made of W, Al-Ta, Al-Ti-Ta, etc.
1 is provided by sputtering. After the photographic processing, the conductive film g1 is selectively etched with a mixed acid solution of phosphoric acid, acid and glacial acetic acid. Thereby, the gate electrode GT, the scanning signal line GL, the counter electrode CT, the counter voltage signal line CL, and the electrode PL
1, gate terminal GTM, first conductive layer of common bus line CB, first conductive layer of counter electrode terminal CTM, gate terminal GT
An anodizing bus line SHg (not shown) connecting M and an anodizing pad (not shown) connected to the anodizing bus line SHg are formed.

Step B (FIG. 13) After the formation of the anodic oxidation mask AO by direct writing, a solution in which 3% tartaric acid was adjusted to PH 6.25 ± 0.05 with ammonia and diluted 1: 9 with ethylene glycol solution was used. The substrate SUB1 is immersed in an anodic oxidizing solution to adjust the formation current density to 0.5 mA / cm ² (constant current formation).

Next, anodic oxidation is performed until the formation voltage 125 V necessary for obtaining a predetermined alumina (Al ₂ O ₃ ) film thickness is reached. Thereafter, it is desirable to maintain this state for several tens of minutes (constant voltage formation). This is a uniform Al ₂ O
_This is important for obtaining _three films. Thereby, the conductive film g1 is anodized, and the gate electrode GT and the scanning signal line G
L, counter electrode CT, counter voltage signal line CL and electrode PL1
An anodic oxide film AOF having a thickness of 180 bnm is formed thereon.

Step C (FIG. 13) A transparent conductive film g2 made of an ITO film having a thickness of 140 nm is provided by sputtering. After the photographic processing, the transparent conductive film g2 is selectively etched with a mixed acid solution of hydrochloric acid and nitric acid as an etchant, thereby forming the uppermost layer of the gate terminal GTM, the drain terminal DTM, and the second conductive film of the counter electrode terminal CTM. I do.

Step D (FIG. 14) An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to provide a 220-nm-thick Si nitride film, and a silane gas and a hydrogen gas are introduced into the plasma CVD apparatus to form a film. After an i-type amorphous Si film having a thickness of 200 nm is provided, a silane gas, a hydrogen gas, and a phosphine gas are introduced into a plasma CVD apparatus to form an N (+)-type amorphous Si film having a thickness of 30 nm.

Step E (FIG. 14) After the photographic processing, the N (+)-type amorphous Si film and the i-type amorphous Si film are selectively etched using SF6 as a dry etching gas, whereby i An island of the type semiconductor layer AS is formed.

Step F (FIG. 14) After the photographic processing, the Si nitride film is selectively etched using SF6 as a dry etching gas.

Step G (FIG. 15) A conductive film d1 made of Cr having a thickness of 60 nm is provided by sputtering, and an Al-P film having a thickness of 400 nm is further formed.
A conductive film d2 made of d, Al-Si, Al-Ta, Al-Ti-Ta, or the like is provided by sputtering. After the photographic processing, the conductive film d2 is etched with the same liquid as in Step A,
The conductive film d1 is etched with a ceric ammonium nitrate solution, and the video signal line DL, the source electrode SD1, the drain electrode SD2, the pixel electrode PX, the electrode PL2, the second conductive layer, the third conductive layer and the drain of the common bus line CB are formed. Terminal D
A bus line SHd (not shown) for short-circuiting TM is formed. Next, SF6 is introduced into the dry etching apparatus,
By etching the N (+) type amorphous Si film,
The N (+) type semiconductor layer d0 between the source and the drain is selectively removed.

Step H (FIG. 15) An ammonia gas, a silane gas, and a nitrogen gas are introduced into a plasma CVD apparatus to form a 500-nm-thick Si nitride film. After photographic processing, SF is used as the drain etching gas.
The protective film PSV1 is formed by selectively etching the Si nitride film by a photolithography technique using No. 6.

<< Connecting Structure of TCP >> FIG.
FIG. 19 is a diagram showing a cross-sectional structure of a tape carrier package in which an integrated circuit chip CHI constituting a scanning signal driving circuit V and a video signal driving circuit H is mounted on a flexible wiring board, and FIG. FIG. 3 is a cross-sectional view of a main part showing a pair connected to a scanning signal circuit terminal GTM.

In the figure, TTB is an input terminal / wiring portion of the integrated circuit CHI, and TTM is an output terminal / wiring portion of the integrated circuit CHI, which is made of, for example, Cu, and has an inner front end portion (commonly called an inner portion). The bonding pads PAD of the integrated circuit CHI are connected to the leads by a so-called face-down bonding method.

The outer ends (commonly called outer leads) of the terminals TTB and TTM are respectively connected to the semiconductor integrated circuit chip CH.
Corresponds to input and output of I, CRT /
Anisotropic conductive film AC for TFT conversion circuit / power supply circuit SUP
F connects to the liquid crystal display panel PNL.

The TCP is connected to the panel PNL so that the tip thereof covers the protective film PSV1 exposing the connection terminal GTM on the panel PNL side. Therefore, the outer connection terminal GTM (DTM) is connected to the protection film PSV1 or the package TC.
Since at least one of P is covered, it is strong against electric contact.

BF1 is a base film made of polyimide or the like, and SRS is a solder resist film for masking so that the solder does not stick to unnecessary portions during soldering. The gap between the upper and lower glass substrates outside the seal pattern SL is protected by an epoxy resin EPX or the like after cleaning, and the space between the package TCP and the upper substrate SUB2 is further filled with a silicon resin SIL to multiplex protection.

<< Drive Circuit Board PCB3 >> Drive Circuit Board P
Electronic components such as an IC (CHI), a capacitor, and a resistor are mounted on the CB3. The drive circuit board PCB2 includes a power supply circuit for obtaining a plurality of divided and stabilized voltage sources from one voltage source, and information for a CRT (cathode ray tube) from a host (upper processing unit). A circuit SUP including a circuit for converting information into information for a TFT liquid crystal display device is mounted.

It should be noted that the present invention is not limited to the above-described horizontal electric field type active matrix type liquid crystal display device, but is also applicable to a vertical electric field type or simple matrix type liquid crystal display device. It is possible.

[0161]

As described above, according to the present invention,
Since the electronic components mounted on the circuit board are used as the spacers in the fixing structure between the circuit board and the frame, the work of attaching the spacers is unnecessary, and mechanical stress due to insertion and removal of the interface connector and the like can cause disconnection of the TCP. A strong fixation that does not invite is obtained. Also, since there is no need to attach spacers,
The number of components can be reduced, the manufacturing process can be simplified, and a low-cost and highly reliable liquid crystal display device can be provided.

[Brief description of the drawings]

FIG. 1 is a schematic plan view illustrating an overall configuration of an embodiment of a liquid crystal display device according to the present invention.

FIG. 2 is a sectional view of an essential part taken along line AA in FIG. 1;

FIG. 3 is a plan view showing one pixel of an active matrix type color liquid crystal display device which is an example of the liquid crystal display device of the present invention, a light shielding region of a black matrix BM, and its periphery.

FIG. 4 is a cross-sectional view of the thin film transistor TFT taken along section line 4-4 in FIG. 3;

FIG. 5 shows a storage capacitance Cstg at a section line 5-5 in FIG. 3;
FIG.

FIG. 6 is a cross-sectional view of the vicinity of an electrode of one pixel and a cross-sectional view of a peripheral portion of the substrate in an image display area of a liquid crystal display substrate of a horizontal electric field type.

FIG. 7 is an explanatory diagram of an angle between a rubbing direction of an alignment film and an applied electric field direction EDR.

FIG. 8 is a plan view of a main part around a matrix of a display panel including upper and lower substrates.

FIG. 9 is a cross-sectional view near an external terminal connected to a scanning circuit on the left side.

FIG. 10 is an explanatory diagram of a sectional structure of an output side and an input side of a gate TCP.

FIG. 11 is a schematic explanatory diagram of a peripheral circuit of a liquid crystal display device according to the present invention.

FIG. 12 is a driving waveform diagram of the liquid crystal display device of the present invention.

FIG. 13 is an explanatory diagram of the manufacturing process of the liquid crystal display device according to the present invention.

FIG. 14 is a view showing a manufacturing process of the liquid crystal display device according to the present invention;
It is explanatory drawing following 3.

FIG. 15 is a view showing a manufacturing process of the liquid crystal display device according to the present invention.
It is explanatory drawing following 4.

FIG. 16 is an exploded perspective view illustrating an example of the overall configuration of a liquid crystal display device.

FIG. 17 is an essential part cross sectional view for explaining a fixed portion of the circuit board and the upper frame.

FIG. 18 is an explanatory diagram of a configuration example of an interface circuit board.

[Explanation of symbols]

SHD Upper frame made of a metal plate WD Display window INS1-3 Insulation sheet PCB1 Drain side circuit board PCB2 Gate side circuit board PCB3 Interface circuit board JN1-3 Joiner TCP1, TCP2, TCP3 for electrically connecting circuit boards PCB1-3 Tape carrier package (TCP) PNL Liquid crystal display panel POL1, POL2 Polarizer GC Rubber cushion ILS Light shielding spacer PRS Prism sheet SPS Diffusion sheet GLB Light guide plate RFS Reflection sheet MCA Lower frame (lower case) formed by integral molding MO MCA Opening CT interface connector LPC Lamp code EP Electronic parts.

Claims (1)

[Claims] 1. A liquid crystal panel having a liquid crystal layer sandwiched between a pair of transparent substrates having a pixel selection electrode on at least one of them opposed to each other, an upper polarizer disposed on both sides of the liquid crystal panel, and A circuit board mounted with electronic components for applying various signal voltages for display by connecting a lower polarizing plate and an electrode of the liquid crystal panel attached to the periphery of the liquid crystal panel using a tape carrier pad. And a backlight provided on the back of the liquid crystal panel fixed by upper and lower frames, wherein the electronic components mounted on the circuit board fill the gap between the frame and the circuit board. A liquid crystal display device having a spacer function for fixing the liquid crystal display.