JPH1092834A - Transistor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the withstanding voltage by placing a second collector region so as to make the min. distance between this region and field limiting ring region longer than that between the second collector region and base region. SOLUTION: A second collector region 14 having a higher impurity concn. than that of a first collector region 13 is not formed on the entire bottom face 20 of a semiconductor substrate 10 but on a region contained in a base region 11 in the plan view. The second region 14 is surrounded with a first collector region 13, except its exposed part at the bottom face 20 and not formed at the lower side of an FLR region 15. Hence the min. distance L2 between these regions 15, 14 is longer than that L1 between the base region 11 and collector region 14. This makes a depletion layer extending downward from the region 15 difficult to reach the second collector region 14, thus realizing a high withstanding voltage.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a transistor with improved withstand voltage.

[0002]

2. Description of the Related Art As shown in FIG. 1, a power transistor in which an emitter region 2 surrounded by a base region 1 is formed in a lattice or island shape is known. In the transistor of FIG. 1, in order to improve the breakdown voltage on the outer peripheral side of the PN junction 5 between the N-type collector region 3 adjacent to the N ⁺ -type collector region 4 and the P ⁺ -type base region 1, A field limiting ring or FL consisting of the same P ⁺ type semiconductor region as base region 1 so as to surround the outer periphery of base region 1.
An R (Field Limiting Ring) region 6 is formed. The FLR region 6 is sometimes called guarding, and contributes to the improvement of the breakdown voltage of the planar structure. Here, 7 is a base electrode, 8 is an emitter electrode, and 9 is a collector electrode.

[0003]

However, even if the FLR region 6 is simply formed as in the prior art, a sufficient withstand voltage improvement effect has not been obtained. The reason is that the depletion layer extending from the FLR region 6 reaches the N ⁺ type collector region 4 (reach through).
However, the extension of the depletion layer is limited, and the electric field relaxation effect by the depletion layer is not sufficiently exhibited.

Accordingly, an object of the present invention is to provide a transistor capable of improving the breakdown voltage.

[0005]

According to the present invention, there is provided a semiconductor device having a base region, an emitter region, a first collector region, and a higher impurity concentration than the first collector region in a semiconductor substrate. A second collector region and a field limiting ring region are provided, and a base electrode is connected to the base region and an emitter electrode is connected to the emitter region on one surface of the semiconductor substrate. The second collector region is connected to a collector electrode provided on the other main surface of the semiconductor substrate, and a bottom surface and side surfaces of the base region are surrounded by the first collector region; The bottom and side surfaces of the emitter region are surrounded by the base region, and the field limiting ring region annularly connects the base region through the first collector region. Unnecessarily formed, the Fi - the transistors bottom and side surfaces of the field-limiting ring region is surrounded by said first collector region, the second part or all of the base of the collector region -
And a shortest distance between the field limiting ring region and the second collector region is located between the base region and the second collector region. Wherein the second collector region is arranged so as to be longer than the shortest distance from the collector region. In addition,
As described in claim 2, a third collector region can be provided. The outermost peripheral edge of the second collector region is located between the outermost peripheral edge of the base electrode and the innermost peripheral edge of the field limiting ring region in a plan view. Is desirably located.

[0006]

According to the present invention, the shortest distance between the field limiting ring region and the second collector region is longer than the shortest distance in the conventional transistor. A depletion layer extending from the source region to the field limiting ring region;
Can be prevented from reaching the collector region, and an improvement in breakdown voltage is achieved. Further, when the second collector region is formed as in claim 3, the transistor operation, that is, the operation of flowing a current between the emitter electrode and the collector electrode can be kept good, and the withstand voltage can be improved.

[0007]

Next, a power transistor according to a first embodiment of the present invention will be described with reference to FIG. The transistor of FIG. 2 has a silicon semiconductor substrate 1 similar to FIG.
0, a base region 11 made of a P ⁺ type semiconductor region and N
Emitter region 12 composed of a ⁺ type semiconductor region, first collector region 13 composed of an N type semiconductor region, and second collector region 14 composed of an N ⁺ type semiconductor region having a higher impurity concentration than first collector region 13 And an FLR (field limiting ring) region 15 made of the same P ⁺ type semiconductor region as the base region 11. An insulating film 17 is provided on one main surface, that is, an upper surface 16, of the semiconductor substrate 10, a base electrode 18 is connected to the base region 11 through an opening 17a provided here, and an opening 17b is formed in the base region 11. An emitter electrode 19 is connected to the emitter region 12 through the emitter electrode 19. A collector electrode 20 is provided on the other main surface, that is, the lower surface 20 of the semiconductor substrate 10, and is connected to the first and second collector regions 13 and 14.

The base region 11 and the emitter region 12 are formed substantially the same as in FIG. 1, but the first and second collector regions 13, 14 and the FLR region 15 are different from FIG. Each part will be described in detail.
Are formed in the collector region 13 by impurity diffusion into an island shape, and the bottom and side surfaces thereof are surrounded by the first collector region 13 to form a PN junction 22 therebetween. The emitter region 12 is formed in a lattice shape in the base region 11 by impurity diffusion in a plan view. As a result, the base region 11 is exposed on the upper surface 16 of the semiconductor substrate 10 in an island shape. That is, the emitter region 12 and the base region 11 have a structure called a so-called mesh emitter or base island. FIG. 2 shows only four emitter regions 12 constituting a grating in principle, but the number of gratings is actually larger.

The first collector region 13 surrounds the base region 11 and the FLR region 15 as in FIG.
Below the LR region 15, it is formed so as to reach the collector electrode 21. Impurity concentration (5 × 10 ¹³ cm ^-3) higher impurity concentration than the first collector region 13 (1
Second collector region 14 having a thickness of about 5 × 10 ²⁰ cm ⁻³ )
Are not formed in the entire region of the lower surface 20 of the semiconductor substrate 10 but are formed in a range included in the base region 11 in plan view. That is, the second collector region 14 is
The first collector region 13 is surrounded except for a portion exposed to the first collector region 13. The second collector region 14 can be formed by diffusing impurities into the first collector region 13 from the lower surface 20 side. Second collector region 1
4 is not formed below the FLR region 15. This second collector region 14
The outermost peripheral edge of the FLR region 15 is disposed between the outermost peripheral edge of the portion where the base electrode 18 is in contact with the base region 11 and the innermost peripheral edge of the FLR region 15 in plan view. Therefore, F
Shortest distance L between LR region 15 and second collector region 14
2 is longer than the shortest distance L1 between the base region 11 and the second collector region 14.

The two FLR regions 15 correspond to the base region 11
Is formed in an annular shape when viewed in plan so as to surround the outer periphery of the device at a distance. The FLR region 15 is surrounded by the first collector region 13 except for the surface, and the surface is covered with an insulating film 17. FLR formed by diffusion
The impurity concentration of the region 15 is lower than that of the base region 11 (1 × 10 ¹⁷ cm ⁻³ ) and is 5 × 10 ¹⁶ cm ⁻³ . The diffusion depth of the FLR region 15 is the same as that of the base region 1.
It is deeper than that of 1. In addition, P ⁺ type FLR
PN between the region 15 and the N-type first collector region 13
A junction 23 has occurred.

When a voltage is applied in a direction to reverse bias a PN junction 22 formed between the base region 11 and the first collector region 13 of the transistor in FIG.
The depletion layer expands from 2. This depletion layer is formed in the base region 11.
Since the impurity concentration of the first collector region 13 is lower than that of the first collector region 13, the first collector region 13 mainly spreads to the first collector region 13 side.
As in the case of the transistor of FIG. 1, when the applied voltage increases, the depletion layer spreads from the PN junction 23 formed between the FLR region 15 and the first collector region 13. However, since the second collector region 14 is not formed under the FLR region 15 and the shortest distance between the FLR region 15 and the second collector region 14 is longer than before,
It is difficult for the depletion layer extending downward from the FLR region 15 to reach the second collector region 14. Therefore, the extension of the depletion layer on the surface of the semiconductor substrate 10 is not limited, and a high breakdown voltage is satisfactorily achieved. Further, since the depletion layer from the FLR region 15 does not easily reach the second collector region 14, the impurity concentration of the FLR region 15 can be reduced as compared with the transistor of FIG. 11 lower than that. Therefore, the spreading of the depletion layer from the FLR region 15 is good. Therefore, the main PN
The cover of the junction 20 is relaxed, the electric field concentration at this portion is favorably relaxed, and the withstand voltage is sufficiently improved. The second collector region 14 has a base electrode 18 as viewed in plan.
1 is provided up to the outermost peripheral edge of the portion in contact with the transistor region 11, so that normal transistor operation occurs substantially the same as the conventional transistor of FIG.

[0012]

Second Embodiment Next, a transistor according to a second embodiment will be described with reference to FIG. However, in FIG. 3, substantially the same parts as those in FIG. 2 are denoted by the same reference numerals, and description thereof will be omitted. The transistor of FIG. 3 has substantially the same configuration as that of FIG. 2 except that a third collector region 24 is added to the transistor of FIG. Third collector region 24 of FIG.
Is an impurity containing, for example, antimony having a low diffusion constant and having an impurity concentration of about 1 to 3 × 10 ¹⁸ cm ^−3.
Semiconductor region, which is a substrate region for epitaxial growth. Therefore, the entire lower surface of the third collector region 24 is the lower surface 20 of the semiconductor substrate 10. The second collector region 14 is formed so as to be sandwiched between the first and third collector regions 13 and 24, that is, in a buried state. At least a part or all of the second collector region 14 faces the base region 11. Are located in The collector region 14 is an N ⁺ -type semiconductor region obtained by diffusing, for example, phosphorus with an impurity whose diffusion constant is higher than that of the third collector region 24, and is higher than the first and third collector regions 13 and 24. It has a high impurity concentration of about 1 × 10 ¹⁹ cm ⁻³ . Note that the second collector region 14 is the third collector region 24
For example, phosphorus is selectively diffused, and an epitaxial growth layer of an N ^- type semiconductor is formed thereon, followed by heat treatment. The impurity concentration of the first collector region 13 in FIG. 3 is, for example, 5 × 10 ¹³ cm ⁻³ . In the transistor of FIG. 3, the relationship between the second collector region 14 and the FLR region 15 is the same as that of the transistor of FIG. 2, so that the second embodiment has the same effect as the first embodiment.

[0013]

[Modifications] The present invention is not limited to the above-described embodiment, and for example, the following modifications are possible. (1) In the embodiment, the impurity concentration and the diffusion depth of the FLR region 15 are different from those of the base region 11. However, the FLR region 15 is formed simultaneously with the base region 11 in the same diffusion step. The effect of the present invention can be obtained even if the impurity concentration and the diffusion depth are substantially the same. In this case, FL
The formation of the R region 15 is facilitated. Also, the FLR region 15
Can be one, or three or more. (2) As shown by a chain line in FIG. 2, a thin second collector region 14 may be provided also in an outer peripheral region (a region including below the FLR region 15) of the lower surface 20 of the semiconductor substrate 10. In addition,
The impurity concentration of the entire lower surface of the semiconductor substrate 10 including the region indicated by the chain line can be higher than the impurity concentration of the surface of the second collector region 14 indicated by the solid line in FIG. In this case, the entire lower surface region including the region indicated by the chain line can be referred to as a third collector region.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a conventional transistor.

FIG. 2 is a cross-sectional view showing a transistor according to a first example of the present invention.

FIG. 3 is a sectional view showing a transistor according to a second embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 11 base region 12 emitter region 13 first collector region 14 second collector region 15 FLR region

Claims (3)

[Claims] 1. A semiconductor device comprising a base region, an emitter region, a first collector region, a second collector region having a higher impurity concentration than the first collector region, and a field limiting ring region in a semiconductor substrate. A base electrode is connected to the base region on one surface of the semiconductor substrate, an emitter electrode is connected to the emitter region, and a collector provided on the other main surface of the semiconductor substrate. The second collector region is connected to an electrode,
The bottom and side surfaces of the base region are surrounded by the first collector region, the bottom surface and side surfaces of the emitter region are surrounded by the base region, and the field limiting ring region is surrounded by the base region. A transistor formed so as to annularly surround a source region through the first collector region, and a bottom surface and a side surface of the field limiting ring region are surrounded by the first collector region. Part or all of the second collector region is disposed between the base region and the other main surface of the semiconductor substrate, and the field limiting ring region and the second collector The second collector region is arranged so that the shortest distance to the region is longer than the shortest distance between the base region and the second collector region. Register. 2. A method according to claim 1, further comprising a third collector region,
The third collector region has an impurity concentration higher than that of the first collector region, and is disposed between the first and second collector regions and the other main surface of the semiconductor substrate. The transistor according to claim 1, wherein 3. An outermost peripheral portion of a portion where the base electrode is connected to the base region and the surface when viewed in a plan view.
The second collector region is formed such that an outermost peripheral edge of the second collector region is located between the innermost peripheral edge of the field limiting ring region and the innermost peripheral edge of the second limiting region. 2. The transistor according to 2.