JPH1091433A - Registerselection controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce and avoid the processing of the data saving/restoration of general-purpose registers, to share the general-purpsoe registers and to avoid the processing speed of a program from lowering. SOLUTION: '1' is set to the respective bit of the selection bits 31, 33, 35 and 37 of the selected general-purpose registers 1, 3, 15 and 17 in a flag register 30. A register selection control part 20 validates only access signal lines 21, 23, 25 and 27 and selects the general-purpose registers 1, 3, 15 and 17 corresponding to the respective bits of the flag register 30. The register selection control part 20 selects the general-purpose register so that it corresponds to the general- purpose register designating the program and the flag register 30 selects it based on input to an address decoding part 7. Thus, it is not necessary to change the value of the flag register 30 and to once save data of the general-purpose register even if the number of variables on the program exceeds the number of the general-purpose registers and the processing can continuously be executed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a register selection control device for controlling a general-purpose register used at the time of an operation of a microcomputer.

[0002]

2. Description of the Related Art A conventional register selection control device of this kind is configured as shown in FIG. In FIG. 2, 1 to 4 are general registers, 5 is a data bus, 6 is an operation unit, 7 is an address decoding unit for selecting general registers 1 to 4, 8 is a memory, and 11 to 14 are general registers 1 to 4.
Access permission signal line.

In the prior art, the general-purpose registers 1 to 4 are connected to an operation unit 6 via a data bus 5 and an access permission signal line 11 to 11 is transmitted from an address decoding unit 7 to select the general-purpose registers 1 to 4. 14 are connected. The access permission signal lines 11, 12, 13, and 14 correspond to the general-purpose registers 1, 2, 3, and 4, respectively. Further, the memory 8 is connected to the arithmetic unit 6 via the data bus 5.

The operation of the conventional register selection control device configured as described above will be described below. First, when the number of variables to be handled exceeds the number of general-purpose registers when performing an operation by a program, the general-purpose registers 1 to 4
From the access permission signal lines 11 to
14 general access registers 1 to 4
4 is temporarily saved in the memory 8 via the data bus 5. The general-purpose registers 1 to 4 required for the next operation are selected by the access permission signal of the address decoding unit 7, and new data required for the next operation are stored in the general-purpose registers 1 to 4 via the data bus 5. After that, the calculation is completed,
When the data once saved in the memory 8 is used, it is necessary to restore the data from the memory 8 to the general-purpose registers 1 to 4 via the data bus 5.

When the microcomputer processes a plurality of programs, since each program uses the general-purpose registers in common, the access permission signal lines 11 to 14 from the address decode unit 7 are switched when the programs are switched. The general-purpose registers 1 to 4 are selected by a signal, the data of the general-purpose registers 1 to 4 used by one program is temporarily saved in the memory 8, and the other program is executed. When one of the programs is to be executed again, it is necessary to restore the data saved from the memory 8 to the general-purpose registers 1 to 4.

[0006]

However, the register selection control device having such a configuration has a problem of increasing the number of variables to be handled when performing an operation by a program. At the time of program switching at the time of processing, it is necessary to save the data of general-purpose registers to memory for each program. Therefore, there is a problem that the number of processes for saving and restoring data between the general-purpose register and the memory is increased and the processing speed is reduced.

The present invention solves the above-mentioned problem of the prior art. Even if the number of variables to be handled increases, the data save / restore processing of the general-purpose register is reduced. It is an object of the present invention to provide a register selection control device capable of avoiding a reduction in processing speed due to data saving / restoring processing and sharing a general-purpose register between different programs.

[0008]

In order to achieve the above object, a register control device according to the present invention temporarily stores data and has a microprocessor or microcomputer having a plurality of general-purpose registers used for operations. Means for arbitrarily specifying a plurality of general-purpose registers to be used by a program among general-purpose registers, and means for associating a general-purpose register specified during processing with a general-purpose register specified by a program as the same general-purpose register. Is provided.

According to the above configuration, while increasing the number of general-purpose registers for temporarily storing data, the number of general-purpose registers specified by a processing instruction can be increased without increasing the number of general-purpose registers specified by a program. This allows a plurality of general-purpose registers to be specified more than the number of general-purpose registers that can be specified by a program, and the general-purpose registers can be arbitrarily rearranged.

[0010]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a register selection control device according to an embodiment of the present invention. Here, components corresponding to the components described in FIG. 2 showing the conventional example are denoted by the same reference numerals. In FIG. 1, 1-4, 15-18 are general-purpose registers, 5 is a data bus, 6 is an operation unit, 7 is an address decoding unit, 8 is a memory, 11-14 are access permission signal lines, and 20 is a register selection control unit. , 21 to 28 are access signal lines, 30 is a flag register, 31 to 38 are general-purpose registers 1 to 4, 15 to 18
Is a selection bit of the flag register 30 corresponding to.

In the example of this embodiment, the number of general-purpose registers arbitrarily specified by a program is four at maximum. further,
The flag register 30 in the register selection control unit 20 has a bit number corresponding to the number of general-purpose registers (eight in the present embodiment) for temporarily storing data.
Consists of bits. The selection bits 31 to 38 of the flag register 30 are "selected" when the bit value is "1" and "not selected" when the bit value is "0".

Next, the operation of this embodiment will be described. First, the general-purpose registers 1 to 1 selected by the flag register 30
Reference numerals 4, 15 to 18 denote access signal lines 21 to 28 connected to the general register 1 by the register selection control unit 20 in order from the general register 1 so as to correspond to the register numbers designated in the program.
Outputs an access signal. For example, select bit 31 of general register 1 of flag register 30 and general register 3
When the selection bit 33 of the general register 15, the selection bit 35 of the general register 15, and the selection bit 37 of the general register 17 are set to "1", the register selection control unit 20 sets the general registers 1, 3, 1
Only the access signal lines 21, 23, 25, 27 corresponding to 5, 17 are made valid, and the general-purpose registers 1, 3, 15, 17 corresponding to each bit are selected.

The flag register 30 performs general-purpose register selection based on the input to the address decoding unit 7 so that the register selection control unit 20 corresponds to the general-purpose register specified by the program. In the present embodiment, the flag register 30 is used as the general-purpose registers 1, 3, 15, 17 as in the setting example.
Is selected (Table 1).

[0014]

[Table 1]

This makes it possible to arbitrarily select from among the eight general-purpose registers, four general-purpose registers used by the hardware during processing, and to correspond to the register numbers specified by the program. Can be selected. If the number of variables in the program exceeds the number of general-purpose registers, it is necessary to temporarily save the data in the general-purpose registers by changing the value of the flag register 30 so that unused general-purpose registers are used. And the processing can be performed continuously.

Next, the operation in the case of program switching will be described. As an example, a case will be described in which general-purpose registers are allocated so that program A uses general-purpose registers 1 to 4 and program B uses general-purpose registers 15 to 18.

When the program A is executed as the setting of the flag register 30, the selection bit 31 of the general-purpose register 1 of the flag register 30, the selection bit 32 of the general-purpose register 2, the selection bit 33 of the general-purpose register 3, and the selection of the general-purpose register 4 are selected. "1" is set to each bit of bit 34. Further, when executing the program A, the register selection control unit 20 makes only the access signal lines 21 to 24 corresponding to the general registers 1 to 4 valid, and the general register 1 corresponding to each bit.
4 are selected.

Therefore, the register selection control unit 20 corresponds to the general-purpose registers 1 to 4 specified by the program A,
The flag register 30 selects a general-purpose register based on an input to the address decoding unit 7. That is, (Table 2) is obtained.

[0019]

[Table 2]

Further, when executing the program B,
The selection bit 35 of the general register 15 of the flag register 30, the selection bit 36 of the general register 16, the selection bit 37 of the general register 17, and the selection bit 38 of the general register 18 are set to "1". In the execution of the program B, the register selection control unit 20 enables only the access signal lines 25 to 28 corresponding to the general registers 15 to 18, and selects the general registers 15 to 18 corresponding to the respective bits.

Therefore, the register selection control section 20 corresponds to the general-purpose registers 15 to 18 specified by the program B,
The flag register 30 selects a general-purpose register based on an input to the address decoding unit 7. That is, (Table 3) is obtained.

[0022]

[Table 3]

Thus, four general-purpose registers used by hardware can be arbitrarily selected from the eight general-purpose registers, and the general-purpose registers on the hardware can be selected according to the register numbers specified by each program. It is possible to make a selection, and it is not necessary to temporarily save the data of the general-purpose register at the time of program switching, and the processing can be performed continuously.

Next, the operation of transferring data of the general-purpose register between different programs will be described. As an example,
The case where the general-purpose registers are allocated so that the general-purpose registers 1 to 4 are used in the program C and the general-purpose registers 4, 15, 16 and 17 are used in the program D will be described.

As the setting of the flag register 30, when executing the program C, the selection bit 31 of the general-purpose register 1 of the flag register 30, the selection bit 32 of the general-purpose register 2, the selection bit 33 of the general-purpose register 3, and the selection of the general-purpose register 4 "1" is set to each bit of bit 34. When executing the program C, the register selection control unit 20 makes only the access signals 21 to 24 corresponding to the general registers 1 to 4 valid,
The general registers 1 to 4 corresponding to each bit are selected.

Therefore, the register selection control unit 20 corresponds to the general-purpose registers 1 to 4 specified by the program C,
The flag register 30 selects a general-purpose register based on an input to the address decoding unit 7. That is, (Table 4) is obtained.

[0027]

[Table 4]

Further, when the program D is executed,
The selection bit 34 of the general-purpose register 4 of the flag register 30, the selection bit 35 of the general-purpose register 15, the selection bit 36 of the general-purpose register 16, and the selection bit 37 of the general-purpose register 17 are set to "1". In the execution of the program D, the register selection control unit 20 makes only the access signals 24, 25, 26, and 27 corresponding to the general registers 4, 15, 16, and 17 effective, and the general registers 4, 15, and 27 corresponding to the respective bits. 16, 17 are selected.

Therefore, the register selection control unit 20 corresponds to the general purpose registers 4, 15, 16, and 17 specified by the program D, and the flag register 30 selects the general purpose register based on the input to the address decoding unit 7. carry out. That is, (Table 5) is obtained.

[0030]

[Table 5]

The assignments in the program the required variables delivery of data between the program C and program D to program a general-purpose register 4 In C, by assigning on a program in a general register 1, the program D, generic on hardware Assign to register 4 . As a result, the general-purpose register 4 on the hardware is commonly used in the program C and the program D, and the data transfer operation is performed without saving and restoring the data between the general-purpose register and the memory. be able to.

[0032]

As described above, according to the present invention,
Even if the number of variables handled when performing calculations by a program exceeds the number of general-purpose registers, data saving and restoration processing between general-purpose registers and memory does not occur, and when switching programs in multiple program processing , The process of saving the value in the general-purpose register to the memory can be avoided,
Further, the transfer of the common data between different programs can be realized without saving the value in the general-purpose register to the memory, so that the processing speed of the program can be prevented from being reduced by the data save / restore processing. Play.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a register selection control device according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a configuration of a conventional register selection control device.

[Explanation of symbols]

1-4,15-18 ... General purpose register, 5 ... Data bus,
6 arithmetic unit, 7 address decode unit, 8 memory, 11-14 access permission signal line, 20 register selection control unit, 21-28 access signal line, 30 flag register, 31-38 selection bit .

Claims (1)

[Claims] 1. A microprocessor or microcomputer having a plurality of general-purpose registers for temporarily storing data and used for operations, wherein a plurality of general-purpose registers to be used among the general-purpose registers are arbitrarily designated by a program. And a means for associating a general-purpose register specified during processing with a general-purpose register specified by the program as the same general-purpose register, thereby reducing a reduction in processing speed. .