JPH1079394A - Bipolar transistor and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To eliminate the energy barrier on an interface between collector-base to reduce the base resistance by a method wherein a low concentration n-type collector layer and a p-type true base layer are successively deposited in aperture parts to provide p-type outer base layers in contact with both base leading out electrodes and the p-type true base layer. SOLUTION: Collector.base separation insulating film 5, base leading out electrodes 6 made of polycrystalline silicon, aperture parts of emitter-base separation films 7 and emitter-base separation insulating films 7a on the sidewalls of the leading out electrodes 6 are formed. Next, low concentration n-type collector layer 8 made of single crystalline silicon-germanium, a p-type true base layer 9 also made of the single crystalline silicon-germanium, p-type outer base layers 10 made of the same polycrystalline silicon-germanium, a low concentration p-type cap layer 11 made of single crystalline silicon and low concentration p-type polycrystalline silicon layers 12 are successively formed in the aperture parts. Finally, the true base layer 9 and the leading out electrodes 6 are connected by the outer bases 10.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bipolar transistor and a method for manufacturing the same, and more particularly, to a single crystal silicon transistor.
The present invention relates to a bipolar transistor using germanium as an intrinsic base layer and a method for manufacturing the same.

[0002]

2. Description of the Related Art A conventional bipolar transistor using single crystal silicon / germanium as an intrinsic base layer,
For example, IEICE Technical Report SD of 1991
M91-124, pages 19 to 24. FIG. 2 shows a cross-sectional structure of this conventional bipolar transistor.

Hereinafter, a method of manufacturing the conventional bipolar transistor will be briefly described with reference to FIG.
In FIG. 2, reference numeral 21 denotes a silicon substrate, and after a low-concentration n-type silicon layer 23 serving as a collector layer is epitaxially grown on a high-concentration n-type buried layer 22 formed on the silicon substrate 21, a selection is performed. An element isolation insulating film 24 is formed by oxidation. Further, a low concentration n serving as a collector layer
Base / collector isolation insulating film 25 on
Then, a base lead electrode 26 and an emitter / base separation insulating film 27 made of polycrystalline silicon are formed, and the emitter / base separation insulating film 27 and the base lead electrode 26 are etched to form an opening. After covering the side wall of the base lead electrode 26 with an insulating film 27a, an intrinsic base layer 28 is formed by epitaxially growing single crystal silicon / germanium. At the same time as the epitaxial growth of single crystal silicon / germanium, an external base 29 made of polycrystalline silicon / germanium is deposited from the bottom surface of the protrusion of the base extraction electrode 26. By continuing the growth, the intrinsic base layer 28 and the base extraction electrode 26 Are connected via the external base 29. In order to prevent conduction between the external base 29 and the emitter, an emitter / base isolation insulating film 30 is further formed thereafter. An emitter layer 32 is formed by depositing n-type polycrystalline silicon 31 doped with arsenic at a high concentration in the opening and performing annealing to diffuse arsenic into the intrinsic base layer 28. Insulating film 3
After the formation of the electrode 3, the electrode 35 is formed. Reference numeral 34 denotes a high-concentration n-type collector lead-out layer.

[0004]

FIG. 3 shows a profile of germanium and impurities in a conventional bipolar transistor using the above-mentioned conventional single crystal silicon / germanium for the intrinsic base layer. FIG. 3A shows a profile of a germanium composition ratio, and FIG. 3B shows an impurity concentration profile. In the figure, j _EB and j _BC indicated by broken lines represent the interface between the emitter and the base and the interface between the base and the collector, respectively.

As can be seen from FIG. 1A, in order to perform doping during the growth of single crystal silicon / germanium, an intrinsic base layer of single crystal silicon / germanium is directly formed on the collector region of single crystal silicon. Have been. FIG. 4 shows the energy band structure of the bipolar transistor having this profile. base·
Single crystal silicon and single crystal silicon to the collector interface j _BC ·
There is a problem that an energy barrier is generated due to the band gap difference of germanium, and the traveling time of carriers injected from the emitter is prolonged.

On the other hand, Japanese Patent Application Laid-Open No. 3-125476 discloses that a base layer and a low impurity concentration collector layer are formed in order to prevent an energy barrier against a collector current from being generated between the base layer and the low impurity concentration collector layer. A hetero-bipolar transistor structure in which both are formed of a mixed crystal of silicon and germanium is disclosed. When this is applied to the above-described bipolar transistor structure in which the base electrode is taken out in a self-aligned manner, for example, a single-crystal silicon-germanium layer is formed between the intrinsic base layer 28 and the low concentration collector layer 23 in FIG. When formed in
A low concentration of polycrystalline silicon / germanium is deposited under the base extraction electrode 26 made of polycrystalline silicon. For this reason, an external base having high resistance is formed between the base extraction electrode 26 and the intrinsic base layer 28, which causes a problem that the base resistance is increased and the circuit operation is slowed down.

Further, in order to diffuse a p-type impurity from the high-concentration polycrystalline silicon 31 serving as an emitter electrode into the single-crystal silicon-germanium layer 28 formed while doping, as shown in FIG. The impurity concentration at the emitter-base junction increases. Therefore, there is a problem that a tunnel effect occurs at the interface between the emitter and the base, and a leak current in the base region increases.

Similarly, Japanese Unexamined Patent Publication No. Hei 7-147287 discloses a bipolar transistor in which the occurrence of a parasitic energy barrier in a base-collector junction region is prevented and a decrease in cutoff frequency is suppressed. This includes G in the base layer of a bipolar transistor in which the base layer and the collector layer are made of a single crystal silicon layer containing germanium.
The concentration of e is low on the emitter layer side and high on the collector layer side, and the Ge concentration in the collector layer is high on the base layer side and low on the n-type high concentration buried layer side inside the collector layer. A bipolar transistor is described in which the Ge concentration rapidly decreases on the base layer side and gradually decreases on the buried layer side. However, even if the structure between the base and the collector can be applied to the structure in which the base electrode is taken out in a self-aligned manner as shown in FIG. Due to the deposition of polycrystalline silicon germanium at a low concentration, the problem that the base resistance is increased and the circuit operation is slowed still remains.

Japanese Patent Laid-Open No. Hei 5-206151 discloses a bipolar transistor in which the position of an emitter region is formed in a self-aligned manner with respect to an external base region and polycrystalline silicon for a base electrode. Intrinsic base layer of single crystal silicon-germanium layer and the p ⁺ base electrode polysilicon are connected via an external base region formed by impurity diffusion from the p ⁺ base electrode polysilicon. According to this structure, the junction capacitance between the diffusion layer in the external base region and the collector is smaller than that in the case where the base electrode shown in FIG. 2 is taken out in a self-aligned manner through the polycrystalline silicon layer directly connected to the intrinsic base layer. There is a drawback that becomes large.

Accordingly, an object of the present invention is to enable a high-speed operation in a bipolar transistor using a single crystal silicon / germanium layer as an intrinsic base layer.
An object of the present invention is to provide a bipolar transistor having no energy barrier at the collector-base interface, a small base resistance, a small emitter-base capacitance and a small collector-base capacitance, and a method of manufacturing the same.

[0011]

A bipolar transistor according to the present invention comprises a first conductivity type single crystal silicon layer, for example, a low concentration n-type collector layer 3 serving as a first collector region in FIG. A first insulating film having an opening provided on the surface of the first-conductivity-type single-crystal silicon layer (that is, a collector / base isolation insulating film 5); and a second-conductivity-type polycrystal of a conductivity type opposite to the first-conductivity type A multi-layered film including a layer (that is, a base lead electrode 6 made of p-type polycrystalline silicon) and a second insulating film (that is, an emitter-base separating insulating film 7), and a first conductive type single film provided in the opening. A crystalline silicon-germanium layer (ie, a low-concentration n-type collector layer 8 made of single-crystal silicon-germanium) and a second conductive type single-crystal silicon layer provided on the first conductive type single-crystal silicon-germanium layer A con-germanium layer (that is, a p-type intrinsic base layer 9 made of single-crystal silicon-germanium) and a second-conductivity-type single-crystal silicon-germanium layer and the second-conductivity-type polycrystalline layer were provided in contact with each other. And a second conductivity type polycrystalline silicon-germanium layer (that is, a p-type external base layer 10 made of polycrystalline silicon-germanium).

In the bipolar transistor, the second conductivity type polycrystalline layer may be a polycrystalline silicon layer or a polycrystalline silicon / germanium layer.

Further, if the thickness of the first conductivity type single crystal silicon-germanium layer, that is, the low concentration n-type collector layer 8 serving as the second collector layer in FIG. 1 is at least 5 nm, It is suitable.

The second conductivity type single-crystal silicon / germanium layer is provided on the second conductivity type single-crystal silicon / germanium layer.
If a second second conductivity type single crystal layer having an impurity concentration lower than that of the germanium layer is further provided, that is, as shown in FIG. 1, the intrinsic base region 9 and the base extraction electrode 6 are doped with the external base 10 to be doped. It is preferable to further provide a low-concentration cap layer 11 made of a single crystal in the joined structure. In this case, the second second conductivity type single crystal layer may be a single crystal silicon layer or a single crystal silicon / germanium layer.

In addition, a second first conductivity type single crystal layer provided on the second conductivity type single crystal silicon-germanium layer, ie, a single crystal serving as an emitter layer formed on the intrinsic base by epitaxial growth It is preferred if further layers are provided. In this case, the second first conductivity type single crystal layer may be a single crystal silicon layer or a single crystal silicon / germanium layer.

In any of the above bipolar transistors, the profile in which the composition ratio of germanium in the second conductivity type single crystal silicon-germanium layer decreases from the first conductivity type single crystal silicon layer side toward the surface, ie, As shown in FIG. 15, it is preferable that the germanium composition ratio in the base layer has a profile that decreases from the collector side toward the emitter side.

Alternatively, the second conductivity type single crystal silicon
A germanium layer and the first conductivity type single crystal silicon;
The composition ratio of germanium in the germanium layer is the first ratio.
As shown in FIG. 17, the profile that decreases from the conductivity type single crystal silicon layer toward the surface, that is, the profile of the germanium composition ratio including the low-concentration collector layer also decreases from the collector side toward the emitter side. Good.

The composition ratio of germanium in the second conductivity type single crystal silicon-germanium layer and the first conductivity type single crystal silicon-germanium layer is from the first conductivity type single crystal silicon layer toward the surface. And the inclination thereof is different between the second conductivity type single crystal silicon-germanium layer and the first conductivity type single crystal silicon-germanium layer, that is, as shown in FIG. The gradient of the germanium composition ratio profile may be different in the concentration n-type collector layer.

Further, the second conductivity type single crystal silicon
The composition ratio of germanium in the germanium layer is the first ratio.
It decreases from the conductivity type single crystal silicon layer side toward the surface, and the composition ratio of germanium in the first conductivity type single crystal silicon / germanium layer decreases from the surface toward the first conductivity type single crystal silicon layer side. Profile,
That is, as shown in FIG. 21, the germanium composition ratio decreases from the collector side to the emitter side in the intrinsic base, and the germanium composition ratio decreases from the base side to the collector side in the low-concentration n-type collector layer. You can also.

According to the method of manufacturing a bipolar transistor of the present invention, a first insulating film having an opening on the surface of a first conductivity type single crystal silicon layer, a second conductivity type opposite to the first conductivity type are provided. A step of forming a multilayer film including a polycrystalline layer and a second insulating film; a step of forming a first conductivity type single crystal silicon / germanium layer in the opening; A second-conductivity-type single-crystal silicon-germanium layer on the germanium layer; and a second-conductivity-type polycrystalline silicon-germanium layer in contact with both the second-conductivity-type single-crystal silicon-germanium layer and the second-conductivity-type polycrystal layer. Forming at least one of the following: a step of forming the first conductivity type single crystal silicon-germanium layer; and a step of forming the second conductivity type. The step of forming the crystalline silicon / germanium layer is a step of forming each layer by epitaxial growth, and the epitaxial growth is performed under the conditions that the growth temperature is 500 ° C. to 700 ° C. and the growth pressure does not exceed 100 Pa. It is characterized by performing.

Further, the optical receiving system according to the present invention comprises a light receiving element for receiving an optical signal and outputting an electric signal, a first amplifier circuit for receiving the electric signal from the light receiving element, and a first amplifier circuit for receiving the electric signal. An optical receiving system comprising: a second amplifier circuit receiving an output; and an identifier for converting an output of the second amplifier circuit into a digital signal in synchronization with a predetermined clock signal, wherein the first amplifier circuit A first bipolar transistor whose base is connected to the light receiving element, and a second bipolar transistor whose base is connected to the collector of the first bipolar transistor and whose collector is connected to the input of the second amplifier circuit. And at least one of the first and second bipolar transistors is constituted by the bipolar transistor according to any of the above. And it is characterized in and. Also,
In the optical receiving system, each of the first and second bipolar transistors may be configured by any of the bipolar transistors described above. Further, it is preferable that the first and second bipolar transistors are formed on a single semiconductor chip, and that the semiconductor chip and the light receiving element are mounted on a single substrate.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS In a preferred embodiment of the bipolar transistor according to the present invention, a low-concentration single-electrode is formed only on an opening of a first insulating film formed in a first collector region on a silicon substrate. A second collector layer made of crystalline silicon / germanium is provided, and a base extraction electrode made of polycrystalline silicon; and a single crystal silicon provided on the second collector layer and doped with impurities. It has a structure in which an intrinsic base region made of germanium contacts through an external base made of polycrystalline silicon-germanium doped with impurities.

As described above, since the second collector layer made of single-crystal silicon / germanium is provided between the first collector layer and the intrinsic base made of single-crystal silicon / germanium, the second collector layer is formed between the collector and the base. Since an energy barrier cannot be formed, the traveling time of carriers injected from the emitter can be reduced. In addition, the base resistance can be reduced by the structure in which the intrinsic base and the base extraction electrode are connected only by the doped low resistance external base. Further, since the emitter, the base and the collector are formed in a self-aligned manner, the capacitance between the emitter and the base and between the collector and the base can be reduced. Therefore, the bipolar transistor according to the present invention can operate at high speed.

In a preferred embodiment of the method for manufacturing a bipolar transistor according to the present invention, the method for manufacturing a bipolar transistor according to the present invention includes the steps of:
The temperature at which germanium is formed by epitaxial growth is 500 ° C. or more and 700 ° C. or less, and the pressure at which germanium is formed does not exceed 100 Pa.

By performing such epitaxial growth conditions, even if single-crystal silicon / germanium is grown on single-crystal silicon, depending on the composition ratio of germanium and the grown film thickness, poly-silicon / germanium may be formed on the polycrystalline silicon.
Germanium can be prevented from depositing. Therefore, when the second low concentration collector layer is formed, the growth of the low concentration polycrystalline silicon / germanium from the bottom surface of the protruding portion of the base extraction electrode made of the polycrystalline layer can be suppressed. On the other hand, when forming a high-concentration intrinsic base, by growing under these growth conditions, a high-concentration polycrystalline layer grows from the bottom surface of the protruding portion of the base extraction electrode, and an external base layer is formed. The intrinsic base and the base lead-out electrode are connected by the external base when the sum of the thicknesses of the base and the external base becomes equal to the difference between the thickness of the collector / base isolation insulating film and the thickness of the second low concentration collector layer. It can be.

[0026]

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a perspective view showing a bipolar transistor according to a first embodiment of the present invention;

<Embodiment 1> FIG. 1 is a sectional structural view showing a first embodiment of a bipolar transistor according to the present invention. Hereinafter, a method for manufacturing the bipolar transistor having the structure shown in FIG. 1 will be described. First, a low-concentration n-type collector layer 3 is epitaxially grown on the entire surface of a p-type silicon substrate 1 having a high-concentration n-type buried layer 2 formed in an emitter and a collector region, and an element isolation insulating film 4 is formed in a portion excluding the emitter region. I do.

Next, the collector / base isolation insulating film 5
A base lead electrode 6 made of polycrystalline silicon, an opening of the emitter / base separation insulating film 7, and an emitter / base separation insulating film 7a on the side wall of the base lead electrode 6 are formed.

In the opening, a low-concentration n-type collector layer 8 made of single-crystal silicon / germanium, a p-type intrinsic base layer 9 made of single-crystal silicon / germanium, a p-type external base layer 10 made of polycrystalline silicon / germanium, A low-concentration p-type cap layer 11 and a low-concentration p-type polycrystalline silicon layer 12 made of single-crystal silicon are formed.

After covering the external base with the emitter / base isolation insulating film 13, an emitter electrode 14 made of high-concentration n-type polycrystalline silicon is deposited and annealed to form the emitter region 15 in the low-concentration cap layer 11. Form.

After depositing the insulating film 16, the insulating films 5, 7,.
An opening is formed in the collector portion of the substrate 16 and a high-concentration n-type collector lead-out layer 17 is formed in the opening. Thereafter, using the resist as a mask, openings are formed in the emitter and base portions of the insulating films 5, 7, and 16, and finally, the electrodes 18 are formed in the openings of the emitter, base, and collector.

In the above bipolar transistor, polycrystalline silicon / germanium may be used for the base extraction electrode 6 and single crystal silicon / germanium may be used for the low-concentration cap layer 11. Alternatively, a low concentration silicon / germanium layer may be used. The same applies to these layers in the following examples.

Here, the germanium composition ratio and the impurity concentration profile of the bipolar transistor of the present embodiment formed as described above are shown in FIG. 5, and the energy band structure is shown in FIG. 6, respectively. As can be seen from FIG.
Germanium is contained not only in the base layer but also in the collector region. As a result, as shown in FIG. 6, the energy barrier due to the difference in the band gap between silicon and silicon germanium is included in the depletion layer between the collector and the base, and the carriers injected from the emitter are accelerated by the electric field. ing. Therefore, the injected carriers can reach the collector without being affected by the barrier. Further, as shown in FIG. 5B, since the low-concentration cap layer 11 is provided on the intrinsic base 9, the impurity concentration at the emitter-base junction is reduced as shown in FIG.
It is lower than the conventional example shown in FIG. As a result, tunnel current at the emitter-base junction can be reduced. In FIG. 5B, the emitter region shows the impurity concentration of phosphorus (P), the base region shows the impurity concentration of boron (B), and the collector region has a low concentration of n.
There are type layer 8 and 3, these n-type layer 8,3 is 10 ¹⁶ c
Since the impurity concentration is m ⁻³ or less, only the impurity profile of the high-concentration n-type buried layer 2 containing arsenic (As) as an impurity is shown.

FIGS. 7 and 8 are flow charts showing a method of manufacturing an active region which is a main part of the bipolar transistor of this embodiment. On a low concentration n-type collector layer 3 made of single crystal silicon, a collector / base separation insulating film 5, a base lead electrode 6 made of polycrystalline silicon (or polycrystalline silicon / germanium), and an emitter / base separation insulating film 7 is formed, and openings of the emitter / base separation insulating film 7 and the base lead-out electrode 6 are formed by etching. After forming the emitter / base separation insulating film 7a also on the side wall of the base extraction electrode 6, the collector / base separation insulation film 5 around the opening below the base extraction electrode 6 is etched to form the base extraction electrode protrusion 6a. (See FIG. 7A).

Next, a second low-concentration collector layer 8 made of single-crystal silicon / germanium is formed on the low-concentration n-type collector layer 3 by epitaxial growth so that no energy barrier is formed at the base-collector interface. At this time, utilizing the difference between the growth start time of single crystal silicon / germanium on single crystal silicon and the growth start time of polycrystalline silicon / germanium on polycrystalline silicon, a polycrystal is formed on the bottom surface of the base extraction electrode protrusion 6a. The growth is performed under conditions where silicon germanium is not deposited.

For example, when the epitaxial growth temperature is 575
° C., and when the growth pressure is 1 Pa, the thickness of single-crystal silicon-germanium which grows on single-crystal silicon until the start of deposition of polycrystalline silicon-germanium on polycrystal silicon, that is, the critical thickness of selective growth, FIG. 9 shows the relationship with the composition ratio of germanium contained in single-crystal silicon-germanium. As shown in FIG. 9, even when only silicon is used (Ge composition ratio = 0%), if the thickness of the single crystal silicon grown on the single crystal silicon is 5 nm or less, the polycrystal silicon is not deposited on the polycrystal silicon.

In the case of silicon-germanium, this film thickness increases as the composition ratio of germanium increases, and when the composition ratio is 15%, about 20 nm is formed on single crystal silicon.
Polycrystalline silicon germanium does not deposit on the polycrystalline silicon even if the single crystal silicon germanium grows. Therefore, even if a low-concentration collector layer having a thickness equal to or less than the critical film thickness is selectively grown, a low-concentration polycrystalline silicon / germanium layer is not deposited on the bottom surface of the protruding base 6a (see FIG. 7B).

In order to perform such growth, a gas source MBE (Molecular Beam Epitaxy) method or a CVD (Chemical
(Chemical Vapor Deposition) method can be used, but the CVD method is more preferable because of good control of selectivity. Further, the temperature range is 500 ° C. or higher where the selectivity between polycrystalline silicon and single crystal silicon and the selectivity between an insulator and single crystal silicon can be favorably obtained. It is. The condition of the growth pressure may be 100 Pa or less, which is the pressure at which the polycrystalline silicon-germanium layer starts growing from the bottom surface of the protrusion 6a of the base extraction electrode within this temperature range.

An intrinsic base layer 9 made of single crystal silicon / germanium doped with impurities at a high concentration.
Is formed, the total thickness of the low-concentration collector layer 8 and the intrinsic base layer 9 is made to be equal to or more than the critical thickness for selective growth, and the growth of the base extraction electrode 6 and the bottom of the base extraction electrode 6a together with the growth of single crystal silicon / germanium. The outer base 10 is formed by depositing crystalline silicon / germanium, and the total thickness of the intrinsic base layer 9 and the outer base 10 is equal to the difference in thickness between the collector / base isolation insulating film 5 and the low concentration collector layer 8. At this point, the intrinsic base layer 9 and the base extraction electrode 6 are connected (see FIG. 7C).

After the intrinsic base layer 9 and the base lead-out electrode 6 are connected by the external base 10, a low-concentration cap made of single-crystal silicon (or single-crystal silicon / germanium) for suppressing a tunnel current at the emitter-base junction. The layer 11 is formed (see FIG. 8A). At this time, low-concentration polycrystalline silicon (or low-concentration polycrystalline silicon / germanium) 12 is deposited on the side wall of the external base 10 together with the low-concentration cap layer, but the intrinsic base layer 9 is formed.
And the base lead electrode 6 are connected via the external base 10, so that the base resistance does not increase.

After a second emitter / base isolation insulating film 13 is formed so as to cover the external base 10 and the polycrystalline silicon (or polycrystalline silicon / germanium) 12, a high-concentration impurity serving as a diffusion source of the emitter and an emitter electrode is formed. The n-type impurity is diffused into the low concentration cap layer 11 by depositing the n-type polycrystalline silicon 14 and performing annealing,
An emitter region 15 is formed (see FIG. 8B).

Thereafter, an insulating film 16 is deposited, and an emitter,
When an opening is formed in each region of the base and the collector to form the electrode 18, the cross-sectional structure shown in FIG. 1 is obtained.

According to this embodiment, the base resistor and the emitter
The effect of the energy barrier generated at the collector-base interface due to the band gap between silicon and silicon-germanium can be reduced without increasing the capacitance at the base interface and the collector-base interface. In addition, since the leak current in the base region can be reduced, the cutoff frequency f _T and the maximum frequency f _max are each 10 GHz.
A high-speed bipolar transistor of z or more can be realized. Therefore, by using this transistor,
Higher speed and higher performance of the circuit can be achieved.

<Embodiment 2> FIG. 10 is a sectional structural view showing a second embodiment of the bipolar transistor according to the present invention. The manufacturing method of the bipolar transistor having the structure of the present embodiment is as follows. As in the first embodiment, a high-concentration n-type buried layer 2, a low-concentration n-type collector layer 3, an element isolation insulating film 4, a collector / base isolation insulating film 5, a base lead electrode 6, an emitter / A base isolation insulating film 7 is formed. Next, the emitter / base isolation insulating film 7, the base extraction electrode 6, and the collector / base isolation insulating film 5 are etched to form openings, and then the low-concentration n
A type collector layer 8, a p-type intrinsic base layer 9, a p-type external base layer 10, a low concentration cap layer 11, and a low concentration polycrystalline silicon (or polycrystalline silicon / germanium) 12 are formed.

Thereafter, the emitter / base isolation insulating film 13
Then, an emitter electrode 14 made of high-concentration n-type polycrystalline silicon is deposited, and annealing is performed to form an emitter region 15 in the low-concentration cap layer 11.

Finally, an insulating film 16 is deposited in the same manner as in the first embodiment, openings are formed in the collector portions of the insulating films 5, 7, and 16 to form a high-concentration n-type collector lead-out layer 17, and then the insulating film is formed. Openings are also formed in the emitter and base portions of 5, 7, 16 to form electrodes 18.

At this time, the germanium composition ratio and the impurity concentration profile of the bipolar transistor are the same as the profiles shown in FIG. 5 of the first embodiment, and the same effects can be obtained.

The difference from the first embodiment shown in FIG. 1 is that the thickness of the collector / base isolation insulating film 5 is almost the same as the thickness of the low-concentration n-type collector layer 8, and the collector / base is formed by etching.
That is, the amount of etching when forming the opening of the base isolation insulating film 5 can be reduced. Accordingly, the protrusion 6a of the base extraction electrode becomes unnecessary, so that the capacitance between the collector and the base can be reduced, and the variation in the size of the opening can be suppressed. Thus, the operating characteristics of a circuit using the transistor are improved, and variations in the characteristics are suppressed. Further, since the amount of etching of the collector / base separation insulating film 5 is small, it is possible to inspect the shape of the external base 10 and the connection between the intrinsic base and the external base from above the wafer after the formation of the intrinsic base layer 9.

FIGS. 11 and 12 are flow charts showing a method of manufacturing an active region which is a main part of the bipolar transistor of this embodiment. First, a low concentration n made of single crystal silicon
A collector / base isolation insulating film 5, a base extraction electrode 6 made of polycrystalline silicon (or polycrystalline silicon / germanium), and an emitter / base isolation insulating film 7 are formed on the mold collector 3, and an opening is formed by etching. Is formed (see FIG. 11A).

Next, a second low-concentration collector layer 8 made of single-crystal silicon / germanium is formed by epitaxial growth between the intrinsic base layer 9 and the low-concentration collector region 3 so that there is no energy barrier at the base-collector interface. . At this time, as in the first embodiment, the growth is performed under the condition that the polycrystalline silicon / germanium is not deposited on the side wall of the base extraction electrode 6 (see FIG. 11B).

Thereafter, an intrinsic base layer 9 made of single crystal silicon / germanium doped with impurities at a high concentration.
At the same time, the intrinsic base layer 9 and the base extraction electrode 6 are connected by depositing polycrystalline silicon / germanium on the side walls of the base extraction electrode 6 (see FIG. 11C).

Next, after the intrinsic base layer 9 and the base extraction electrode 6 are connected by the external base 10, a low-level single-crystal silicon (or single-crystal silicon / germanium) layer is used to suppress the tunnel current at the emitter-base junction. A concentration cap layer 11 is formed (see FIG. 12A). At this time, low-concentration polycrystalline silicon (or low-concentration polycrystalline silicon / germanium) 12 is deposited on the external base 10 together with the low-concentration cap layer 11, but the intrinsic base layer 9 and the base lead-out electrode 6 form the external base 10. The base resistance does not increase because the connection is made through the connection.

Further, after forming the second emitter / base isolation insulating film 13 so as to cover the external base 10 and the polycrystalline silicon (or polycrystalline silicon / germanium) 12, it becomes an emitter diffusion source and an emitter electrode. High-concentration n-type polycrystalline silicon 14 is deposited, and annealing is performed to diffuse n-type carriers into the low-concentration cap layer 11 to form an emitter region 15 (FIG. 12B).
Thereafter, an insulating film 16 is deposited, openings are formed in the collector portions of the insulating films 5, 7, and 16, and a high-concentration n-type collector lead layer 17 is formed. Then, the emitter and base portions of the insulating films 5, 7, and 16 are formed. 1 is formed in each of the openings of the emitter, the base and the collector.
0 is obtained.

<Embodiment 3> FIG. 13 is a sectional structural view showing a third embodiment of the bipolar transistor according to the present invention. The manufacturing method of the bipolar transistor having the structure of the present embodiment is as follows.

An emitter opening, a low-concentration n-type collector layer 8, a p-type intrinsic base layer 9, and a p-type external base layer 10 are formed in the same manner as in the first embodiment. The second emitter / base isolation insulating film 1 is formed so as to cover the external base layer 10.
After forming 3, the emitter layer 19 is formed by epitaxial growth.

Next, after depositing a high-concentration n-type polysilicon 14 serving as an emitter electrode and an insulating film 16, the insulating films 5, 7, and
An opening is formed in the collector portion 16 and a high-concentration n-type collector lead layer 17 is formed. Then, the insulating film 5,
When openings are formed in the emitter and base portions 7 and 16 and electrodes 18 are formed in the opening portions of the emitter, base and collector, the cross-sectional structure shown in FIG. 13 is obtained.

In this embodiment, the impurity concentration in the emitter layer 19 is reduced at the emitter-base interface,
The leak current in the base region can be reduced, and the same effect as in the first embodiment can be obtained. In addition, since the emitter layer 19 is formed by epitaxial growth, the controllability of the impurity concentration and the film thickness in the emitter layer 19 is improved, and the variation in transistor performance can be reduced.

Furthermore, since the area of the interface between the emitter and the base can be reduced, the capacitance between the emitter and the base can be reduced, and the characteristics of a circuit using this transistor can be improved.

<Embodiment 4> FIG. 14 is a sectional structural view showing a fourth embodiment of the bipolar transistor according to the present invention. Collector / base isolation insulating film 5 as in the second embodiment
Is about the same as the thickness of the low-concentration n-type collector layer 8, and the etching amount when forming the opening of the collector / base isolation insulating film 5 by etching is reduced. Then, an emitter opening, a low-concentration n-type collector layer 8, a p-type intrinsic base layer 9, and a p-type external base layer 10 are formed in the same manner as in the second embodiment. Thereafter, the emitter layer 19 is formed by epitaxial growth in the same manner as in the third embodiment, whereby the controllability of the impurity concentration and the film thickness in the emitter layer 19 is improved, and the performance variation of the transistor can be reduced. Therefore, similarly to the third embodiment, the characteristics of the circuit using the transistor of this embodiment can be improved.

<Embodiment 5> FIGS. 15A and 15B show a fifth embodiment of a bipolar transistor according to the present invention. FIG. 15A shows the germanium composition ratio of the transistor, and FIG. 15B shows the impurity concentration. FIG. 4 is a characteristic diagram showing profiles. The structure of the transistor is shown in FIGS.
3 and FIG. 14 are all applicable. Although a cross-sectional structure diagram is omitted in this embodiment, reference numerals in the following description may refer to, for example, the cross-sectional structure diagram in FIG. The same applies to Examples 6 to 8 to be described later.

As shown in FIG. 15A, the germanium composition ratio in the intrinsic base layer 9 of the transistor of this embodiment is reduced from the collector side to the emitter side. The energy band structure at this time is shown in FIG.
6 is shown. As can be seen from FIG. 16, in the base layer, the energy band can be inclined in accordance with the germanium composition ratio. Thus, the carriers injected from the emitter are accelerated in the base layer by the electric field caused by the inclined energy band, so that the transistor can operate at higher speed. As a result, by using this transistor, in addition to the effects described in the first, second, third, and fourth embodiments,
Further, the characteristics of the circuit can be improved. FIG.
As shown in the impurity concentration profile of FIG. 5B, the impurity concentration at the emitter-base junction _jEB interface of this embodiment is also lower than that of the conventional example shown in FIG. Therefore, tunnel current at the emitter-base junction can be reduced.

<Embodiment 6> FIGS. 17A and 17B show a sixth embodiment of a bipolar transistor according to the present invention. FIG. 17A shows a germanium composition ratio of the transistor, and FIG. 17B shows an impurity concentration. FIG. 4 is a characteristic diagram showing profiles. The structure of the transistor is shown in FIGS.
3 and FIG. 14 are all applicable. Therefore, in the present embodiment, the sectional structural view is omitted as in the fifth embodiment.

As shown in FIG. 17A, in the transistor of this embodiment, the profile of the germanium composition ratio including not only the intrinsic base layer 9 but also the low-concentration n-type collector layer 8 goes from the collector side to the emitter side. According to the size. FIG. 18 shows the energy band structure at this time. As can be seen from FIG. 18, the energy band can be inclined in the depletion layer between the collector and the base in addition to the inclination of the energy band in the base layer. As a result, the carriers injected from the emitter are accelerated not only in the base layer and the depletion layer at the collector-base interface, but also in the low-concentration n-type collector layer 8, so that the transistor can operate at higher speed. Become. As a result, by using this transistor, the fifth embodiment
In addition to the effect described above, the characteristics of the circuit can be further improved.

<Embodiment 7> FIGS. 19A and 19B are views showing a seventh embodiment of a bipolar transistor according to the present invention. FIG. 19A shows a germanium composition ratio of the transistor, and FIG. 19B shows an impurity concentration. FIG. 4 is a characteristic diagram showing profiles. The structure of the transistor is shown in FIGS.
3 and FIG. 14 are all applicable, and a cross-sectional structural view is omitted as in the fifth embodiment.

The bipolar transistor of this embodiment is characterized in that the profile of the germanium composition ratio including not only the intrinsic base layer 9 but also the low-concentration n-type collector layer 8 decreases from the collector side toward the emitter side. This is the same as the transistor of the sixth embodiment. However, in the bipolar transistor of the present embodiment, the inclination of the profile differs between the intrinsic base layer 9 and the low-concentration n-type collector layer 8. That is, the transistor is different from the transistor of the sixth embodiment in that the germanium composition ratio on the collector side is equal to or less than the maximum amount that does not cause a defect caused by strain in the low-concentration n-type collector layer 8 and the intrinsic base layer 9.

FIG. 20 shows the energy band structure of the transistor of this embodiment. In addition to the inclination of the energy band in the base layer, the energy band can be inclined in the depletion layer between the collector and the base, and the leakage current due to crystal defects can be reduced. As a result, by using this transistor, the embodiment 6
In addition to the effect described above, the characteristics of the circuit can be further improved.

<Eighth Embodiment> FIGS. 21A and 21B show an eighth embodiment of a bipolar transistor according to the present invention. FIG. 21A shows the composition ratio of germanium in the transistor, and FIG. 21B shows the impurity concentration. FIG. 4 is a characteristic diagram showing profiles. The structure of the transistor is shown in FIGS.
3 and FIG. 14 are all applicable. Therefore, in the present embodiment, as in the fifth embodiment, the sectional structural view is omitted.

In the intrinsic base layer 9 of the bipolar transistor of this embodiment, the germanium composition ratio is reduced from the collector side to the emitter side, and in the low concentration n-type collector layer 8, the germanium composition ratio is reversed toward the collector side. And make it smaller. FIG. 22 shows the energy band structure at this time. As shown in FIG. 22, in this embodiment, there is no energy barrier at the interface between the first low-concentration n-type collector layer 3 and the second low-concentration n-type collector layer 8. For this reason, the carriers accelerated by the inclination of the energy band in the intrinsic base layer 9 reach the collector without being affected by the energy barrier at all. As a result, the transistor can operate at higher speed. By using this transistor, in addition to the effects of the first, second, third, and fourth embodiments, the speed of the circuit can be further improved.

<Embodiment 9> FIG. 23 is a diagram showing a ninth embodiment of a bipolar transistor according to the present invention, and is a circuit diagram of a preamplifier circuit used in an optical transmission system.
As is well known, an optical transmission system requires high-speed transmission of several tens of Gb / s, and its preamplifier circuit particularly requires high-speed operation. Therefore, by employing the transistor according to the present invention as a transistor constituting the amplifier circuit, the performance of the entire amplifier circuit can be significantly improved.

In FIG. 23, reference numeral 300 indicates a semiconductor integrated circuit constituting a preamplifier circuit formed on a single semiconductor substrate. A photodiode PD is externally connected to an input terminal IN of the semiconductor integrated circuit 300, and a decoupling capacitor 3 is connected between a power supply terminal 301 and a ground terminal 302.
03 is externally attached. The photodiode PD is a light receiving element that receives an optical signal transmitted through an optical transmission cable, and the decoupling capacitor 303 is a capacitor for short-circuiting an AC component between a power supply line and a ground line.

The bipolar transistors Q1 and Q2 are
It is a bipolar transistor constituting an amplifier circuit, and any of the bipolar transistors according to the present invention having the structure described in Embodiments 1 to 8 can be suitably used. The diode D1 is a diode for level shift, and may be formed by short-circuiting between the base and the collector of the bipolar transistor according to the present invention. Further, it is also possible to apply a plurality of diodes connected in series as needed. Reference symbols R1, R2 and R3 are resistors, O
UT is an output terminal. Also, if necessary, output terminal O
An output buffer circuit is inserted between the UT and the emitter of the transistor Q2.

The semiconductor integrated circuit 300 constituting the preamplifier circuit for an optical transmission system according to the present embodiment converts an optical signal transmitted through an optical transmission cable, which is converted by a photodiode PD, into an input terminal IN. As input
The input electric signal operates so as to be amplified by the amplifying transistors Q1 and Q2 and output from the output terminal OUT. By using any of the bipolar transistors according to the present invention described in the first to eighth embodiments, the preamplifier circuit of the present embodiment can realize a band characteristic of 40 GHz or more.

The performance of the preamplifier circuit for the 40 Gb / s optical transmission system is as follows.
The bandwidth of the dB drop must be 40 Gb / s.
For this purpose, the performance of the bipolar transistor
Cutoff frequency f _T ≧ 100 GHz, base resistance r _bb ′ ≦ 10
0Ω and collector junction capacitance C _TC ≦ 2fF are required. To satisfy such performance, for example, in terms of the bipolar transistor structure of Figure 1, the emitter width W _E 0.
30 nm 2 [mu] m, 2 [mu] m the emitter length L _E, the carrier concentration in the base N _B to 1 × 10 ¹⁹ cm ^-3, the base width W _B,
The doping amount of the high-concentration n-type polycrystalline silicon 14 for the emitter diffusion source may be 2 × 10 ²⁰ cm ^−3, and the conditions of the emitter annealing may be about 900 ° C. and about 30 seconds.

FIG. 24 is a cross-sectional view of a front-end module of an optical transmission system in which a photodiode PD and a preamplifier circuit are integrated on a mounting substrate. FIG.
1, reference numeral 401 denotes an optical fiber, 402 denotes a lens, 403 denotes a photodiode, and 404 denotes a semiconductor integrated circuit on which a preamplifier is formed.

Photodiode 403 and preamplifier I
C404 is mounted on the substrate 407. The photodiode 403 and the preamplifier IC 404 are connected to the output terminal 40 via a wiring 405 for connecting the diode and the amplifier.
6 is connected. The substrate 407 is housed in a hermetically sealed package 408 such as a metal case. Although not shown, the capacitor 303 shown in FIG. 23 is also mounted on the substrate 407. As described above, by configuring the photodiode and the preamplifier constituting the front end in the same module, the signal path can be shortened, noise is less likely to occur, and the parasitic L component (inductor component) and C component ( Capacitance component) can also be kept small.

In the front module shown in FIG. 24, the optical signal input from the optical fiber 401
The light is condensed by an optical signal 02 and converted into an electric signal by a photodiode 403. This electric signal is amplified by the preamplifier IC 404 through the wiring 405 on the substrate 407 and output from the output terminal 406.

FIGS. 25 and 26 show FIGS. 23 and 24, respectively.
2 is a system configuration diagram of an optical transmission system using the preamplifier circuit and the front-end module shown in FIG. FIG.
Reference numeral 5 denotes a transmission module 500 of the optical transmission system. The electric signal 501 to be transmitted is a multiplexer MU.
X is multiplexed, for example, in a ratio of 4: 1, and the output signal is transmitted to the driver 502. The semiconductor laser LD always outputs light of a constant intensity. The output light of the semiconductor laser LD is transmitted to the optical fiber 504 via an external modulator 503 that absorbs or does not absorb light according to the output of the driver 502. The transmission module shown in FIG. 25 is a so-called external modulation type. Alternatively, it is possible to employ a direct modulation type that directly controls the light emission of the semiconductor laser LD,
In general, transmission using the external modulation type has no spread of spectrum oscillation due to chirp, and is suitable for high-speed, long-distance transmission.

FIG. 26 shows an optical receiving module 510 of the optical transmission system. In FIG. 26, reference numeral 520 indicates a front-end module unit. The front-end module unit 520 receives a light signal transmitted through the optical fiber 544, converts the light signal into an electric signal, and outputs the electric signal. And a preamplifier 522 for amplifying the output of the light receiver. The electric signal amplified by the preamplifier 522 is input to the main amplifier unit 530 and amplified. The main amplifier 530 uses an automatic gain adjuster (AG) in order to keep the output constant while avoiding variations due to optical transmission distance and manufacturing deviation.
C) It is configured to be fed back to 531. In addition,
The main amplifier unit 530 may employ a limit amplifier for limiting the output amplitude, in addition to the configuration for adjusting the gain. Reference numeral 580 denotes a power supply for the light receiver 521.

The discriminator 540 is configured to perform 1-bit analog-to-digital conversion in synchronization with a predetermined clock, and digitizes the output of the main amplifier section 530. This digital signal is separated into, for example, 1: 4 by a separator DMUX, and the digital signal processing circuit 5 at the subsequent stage
The data is input to the device 60 and a predetermined process is performed.

The clock extracting section 550 is for forming a clock for controlling the operation timing of the discriminator 540 and the separator DMUX from the converted electric signal. The clock extraction unit 550 includes a main amplifier 53
The output of 0 is rectified by a full-wave rectifier 551 and filtered by a narrow-band filter 552 to extract a signal to be a clock signal. The output of the filter 552 is input to the phase shifter 553. The phase shifter 553 is a phase shifter for matching the phase of the filter output with the phase of the analog signal, and delays the filter output based on a predetermined delay amount. The output of the phase shifter 553 is
Are input to the discriminator 540 and the DMUX 570 via the.

In the optical communication system described here,
A circuit can be formed at each location using the bipolar transistor according to the present invention having the structure described in the first to eighth embodiments. Similarly, the circuit constituting the main amplifier 532 can also be constituted by the circuit shown in FIG.

The bipolar transistor according to the present invention manufactured according to the above-described embodiment can operate at a high speed of 100 GHz with a cutoff frequency f _T and a maximum cutoff frequency f _max of 100 GHz. Can be sent and received. Conventionally, for a circuit requiring such a high-speed operation, it is necessary to use a GaAs transistor whose operation speed is higher than that of a silicon bipolar transistor. However, for such a circuit,
Since the inexpensive silicon bipolar transistor according to the present invention can be used, the cost of the entire optical transmission system can be reduced.

<Embodiment 10> FIG. 27 is a diagram showing a tenth embodiment of a bipolar transistor according to the present invention.
1 is a block diagram of a mobile wireless portable device to which a bipolar transistor according to the present invention is applied. In this embodiment, the bipolar transistor according to the present invention described in the first to eighth embodiments is replaced with a low-noise amplifier 603 and a synthesizer 60.
6. PLL (Phase Locked Loop)
This is an example in which the present invention is applied to a circuit constituting each block of a mobile wireless portable device such as a loop 611.

The mobile radio portable device of this embodiment shown in FIG. 27 operates as follows. An input signal from the antenna 601 is amplified by the low noise amplifier 603. Oscillator 605 oscillates at the frequency synthesized by synthesizer 606, and down-converts the signal from low noise amplifier 603 to a lower frequency using down-mixer 604 using the signal oscillated by oscillator 605.

Further, the oscillator 610 oscillates at the frequency generated by the PLL 611, and the signal from the down mixer 604 is demodulated by the demodulator 609 using the signal oscillated from the oscillator 610. The demodulated signal is subjected to signal processing in a baseband unit 613 that handles lower frequencies.

The signal emitted from baseband unit 613 is modulated by modulator 612 using the signal from PLL 611. The modulated signal is further applied to up-mixer 608 by synthesizer 606.
Is up-converted to a high frequency using the signal oscillated by the oscillator 605 based on the signal synthesized in step (1). This high frequency signal is amplified by the power amplifier 607 and
Sent from 1.

Here, the switch 602 is a switch for switching between transmission and reception of signals, and receives and transmits a control signal (not shown) from the baseband unit 613 to control transmission and reception. Further, the baseband unit 613
Are connected to a speaker, a microphone, and the like (not shown) so that audio signals can be input and output.

The respective blocks shown in FIG. 27 constituting the mobile radio portable device of the present embodiment, in particular, the blocks of the low noise amplifier 603, the synthesizer 606 and the PLL 611 according to the present invention described in the first to eighth embodiments. Each circuit can be configured by applying any of the bipolar transistors. The transistor according to the present invention can reduce the base resistance and the base-collector capacitance, so that the low noise amplifier 603, the synthesizer 606, and the PLL 611 can achieve low noise and low power consumption. This makes it possible to realize a mobile wireless portable device that can be used for a long time with low noise as a whole system.

<Embodiment 11> FIG. 28 is a diagram showing an eleventh embodiment of a bipolar transistor according to the present invention.
FIG. 2 is a circuit diagram of a prescaler D flip-flop of a PLL of a mobile wireless portable device to which the bipolar transistor according to the present invention is applied. This embodiment is an example in which the bipolar transistors according to the present invention described in the above embodiments 1 to 8 are used as the transistors 701 to 712 on the circuit shown in FIG.

The input signal, clock signal, and output signal of this D flip-flop circuit have only two states, a high potential and a low potential. An input signal and an inverted input signal are input to terminals 719 and 720, respectively, and a clock signal and an inverted clock signal are input to terminals 721 and 722, respectively.
An output signal and an inverted output signal are obtained from the terminals 723 and 724.

The current paths flowing through the current sources 718 and 719 are switched to one of the transistors 709 and 710 and 711 and 712, respectively, according to the clock signal. Further, the on / off of the transistors 701 to 706 is determined by the input signal, the clock signal, and the potential at the lower end of the resistor caused by the current flowing through the resistors 713 and 714. In this circuit, the output signal outputs an input value when the clock signal changes from a low potential to a high potential, and otherwise holds the previous input value.

Each circuit can be configured by applying any of the bipolar transistors according to the present invention described in the first to eighth embodiments. The transistor according to the present invention can reduce the base resistance and the base-collector capacitance, so that the power consumption of the PLL of the mobile wireless portable device can be reduced.

The preferred embodiment of the present invention has been described above. However, the present invention is not limited to the above-described embodiment, and various design changes can be made without departing from the spirit of the present invention. It is.

[0094]

As described above, according to the present invention, since there is no energy barrier at the collector-base interface, the transit time of carriers injected from the emitter is reduced, and the transistor can operate at high speed. Further, since the intrinsic base and the base lead-out electrode are connected by the doped external base and the base resistance can be reduced, high-speed operation of the circuit using the bipolar transistor becomes possible. Further, since the emitter-base-collector is formed in a self-aligned manner, the capacitance between the emitter-base and the collector-base can be reduced, and the circuit using the bipolar transistor can operate at high speed.

That is, according to the bipolar transistor and the method of manufacturing the same according to the present invention, it is possible to reduce the emitter-base capacitance, the base-collector capacitance, and the base resistance, and operate at high speed and high frequency. It is possible to configure a possible bipolar transistor. Therefore, by using the bipolar transistor according to the present invention for a circuit or a system that requires a high-speed operation, the performance of the entire circuit and the system can be improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a first embodiment of a bipolar transistor according to the present invention.

FIG. 2 is a cross-sectional view showing a conventional bipolar transistor using single crystal silicon / germanium as an intrinsic base.

3 is a characteristic diagram showing a germanium composition ratio and an impurity concentration profile of the bipolar transistor shown in FIG.

4 is a diagram schematically showing an energy band structure of a conventional bipolar transistor having the profile shown in FIG.

5 is a characteristic diagram showing a germanium composition ratio and an impurity concentration profile of the bipolar transistor according to the present invention shown in FIG.

6 is a diagram schematically showing an energy band structure of the bipolar transistor according to the present invention having the profile shown in FIG.

FIG. 7 is a partially enlarged cross-sectional view showing a method of manufacturing the active region of the bipolar transistor according to the present invention shown in FIG. 1 in the order of steps.

FIG. 8 is a partially enlarged cross-sectional view showing steps subsequent to FIG. 7 in order;

FIG. 9 is a characteristic diagram showing a relationship between a maximum thickness of single crystal silicon-germanium which can be selectively grown on single crystal silicon with respect to polycrystalline silicon and a germanium composition ratio.

FIG. 10 shows a second example of the bipolar transistor according to the present invention.
It is sectional drawing which shows Example of (a).

11 is a partial enlarged cross-sectional view showing a method of manufacturing the active region of the bipolar transistor according to the present invention shown in FIG. 10 in the order of steps.

FIG. 12 is a partially enlarged cross-sectional view sequentially showing the steps subsequent to FIG. 11;

FIG. 13 shows a third example of the bipolar transistor according to the present invention.
It is sectional drawing which shows Example of (a).

FIG. 14 shows a fourth example of the bipolar transistor according to the present invention.
It is sectional drawing which shows Example of (a).

FIG. 15 shows a fifth example of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing the example of FIG.

16 is a diagram schematically showing an energy band structure of the bipolar transistor according to the present invention having the profile shown in FIG.

FIG. 17 shows a sixth embodiment of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing the example of FIG.

18 is a diagram schematically showing an energy band structure of the bipolar transistor according to the present invention having the profile shown in FIG.

FIG. 19 shows a seventh embodiment of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing the example of FIG.

20 is a diagram schematically showing the energy band structure of the bipolar transistor according to the present invention having the profile shown in FIG.

FIG. 21 shows an eighth embodiment of the bipolar transistor according to the present invention.
FIG. 5 is a characteristic diagram showing germanium composition ratios and impurity concentration profiles showing the example of FIG.

22 is a diagram schematically showing an energy band structure of the bipolar transistor according to the present invention having the profile shown in FIG.

FIG. 23 is a ninth embodiment of the bipolar transistor according to the present invention;
FIG. 3 is a diagram illustrating an example of the present invention, and is a circuit diagram of a preamplifier circuit used in an optical transmission system.

24 is a sectional view of a front-end module of an optical transmission system in which the preamplifier circuit shown in FIG. 23 is integrated on a mounting board.

FIG. 25 is a block diagram of a transmission-side module of an optical transmission system using the circuits and modules shown in FIGS. 23 and 24.

FIG. 26 is a block diagram of an optical receiving module of an optical transmission system using the circuits and modules shown in FIGS. 23 and 24.

FIG. 27 shows a first example of a bipolar transistor according to the present invention.
FIG. 10 is a diagram illustrating an example of a mobile wireless portable device to which the bipolar transistor according to the present invention is applied according to an embodiment of the present invention.

FIG. 28 shows a first example of a bipolar transistor according to the present invention.
FIG. 2 is a diagram showing an example of the first embodiment, and is a circuit diagram of a D flip-flop for a prescaler of a PLL of a mobile wireless portable device to which a bipolar transistor according to the present invention is applied.

[Explanation of symbols]

1, 21: silicon substrate; 2, 22: high-concentration n-type buried layer; 3, 23: low-concentration n-type collector layer (single-crystal silicon); 4, 24: element isolation insulating film; Base isolation insulating film, 6, 26... Base extraction electrode (polycrystalline silicon or polycrystalline silicon / germanium), 7, 7a, 13, 16, 27, 27a, 30, 3
3: Emitter / base isolation insulating film, 8: Low concentration n-type collector layer (single crystal silicon / germanium), 9, 28 ...
p-type intrinsic base layer (single-crystal silicon / germanium),
10, 29: p-type external base layer (polycrystalline silicon / germanium), 11: low concentration cap layer (single crystal silicon or single crystal silicon / germanium), 12: low concentration polycrystalline silicon (or low concentration polycrystalline silicon) Germanium), 14, 31 ... emitter electrode (high-concentration n-type polycrystalline silicon), 15, 32 ... emitter region, 16 ...
Insulating film, 17, 34 ... high-concentration n-type collector lead-out layer,
18, 35 ... electrodes, 19 ... emitter layers (single-crystal silicon or single-crystal silicon-germanium).

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Katsuyoshi Washio 1-280 Higashi Koigakubo, Kokubunji-shi, Tokyo Inside Central Research Laboratory, Hitachi, Ltd.

Claims (15)

[Claims] A first conductivity type single crystal silicon layer, a first insulating film having an opening provided on a surface of the first conductivity type single crystal silicon layer, and a first conductivity type opposite to the first conductivity type. A multilayer film comprising a second conductivity type polycrystalline layer and a second insulating film; a first conductivity type single crystal silicon / germanium layer provided in the opening; and a first conductivity type single crystal silicon / germanium layer A second conductivity type single crystal silicon-germanium layer provided thereon, and a second conductivity type provided in contact with both the second conductivity type single crystal silicon-germanium layer and the second conductivity type polycrystalline layer And a polycrystalline silicon-germanium layer. 2. The bipolar transistor according to claim 1, wherein said second conductivity type polycrystalline layer is a polycrystalline silicon layer or a polycrystalline silicon / germanium layer. 3. The bipolar transistor according to claim 1, wherein the thickness of the first conductivity type single crystal silicon-germanium layer is at least 5 nm. 4. A second conductivity type single crystal silicon layer provided on the second conductivity type single crystal silicon germanium layer.
4. The semiconductor device according to claim 1, further comprising a second second conductivity type single crystal layer having a lower impurity concentration than the germanium layer.
13. The bipolar transistor according to item 9. 5. The bipolar transistor according to claim 4, wherein said second second conductivity type single crystal layer is a single crystal silicon layer or a single crystal silicon / germanium layer. 6. The bipolar device according to claim 1, further comprising a second first conductivity type single crystal layer provided on the second conductivity type single crystal silicon / germanium layer. Transistor. 7. The bipolar transistor according to claim 6, wherein said second first conductivity type single crystal layer is a single crystal silicon layer or a single crystal silicon / germanium layer. 8. The method according to claim 1, wherein the composition ratio of germanium in said second conductivity type single crystal silicon-germanium layer decreases from said first conductivity type single crystal silicon layer side toward the surface. 2. The bipolar transistor according to claim 1. 9. The composition ratio of germanium in the second conductivity type single crystal silicon-germanium layer and the first conductivity type single crystal silicon-germanium layer is from the first conductivity type single crystal silicon layer to the surface. The bipolar transistor according to any one of claims 1 to 7, wherein the bipolar transistor decreases in accordance with the following equation. 10. The composition ratio of germanium in the second conductivity type single crystal silicon / germanium layer and the first conductivity type single crystal silicon / germanium layer is from the first conductivity type single crystal silicon layer to the surface. The bipolar transistor according to any one of claims 1 to 7, wherein the inclination decreases in the second conductivity type single crystal silicon-germanium layer and in the first conductivity type single crystal silicon-germanium layer. . 11. The first conductivity type single crystal silicon, wherein a composition ratio of germanium in the second conductivity type single crystal silicon / germanium layer decreases from the first conductivity type single crystal silicon layer side toward the surface. 8. The bipolar transistor according to claim 1, wherein a composition ratio of germanium in the germanium layer decreases from a surface toward the first conductivity type single crystal silicon layer. 9. 12. A first insulating film having an opening on a surface of a first conductivity type single crystal silicon layer, a second conductivity type polycrystalline layer having a conductivity type opposite to the first conductivity type, and a second insulation film. Forming a multilayer film composed of a film, forming a first conductivity type single crystal silicon-germanium layer in the opening,
A second conductivity type single crystal silicon / germanium layer on the conductivity type single crystal silicon / germanium layer, and a second conductivity type contacting both the second conductivity type single crystal silicon / germanium layer and the second conductivity type polycrystalline layer A method of manufacturing a bipolar transistor having at least a step of simultaneously forming a polycrystalline silicon-germanium layer, wherein the step of forming the first conductivity type single-crystal silicon-germanium layer and the second conductivity type single-crystal The step of forming a silicon-germanium layer is a step of forming each layer by epitaxial growth, and the epitaxial growth is performed under the conditions that the temperature during growth is 500 ° C. to 700 ° C. and the pressure during growth does not exceed 100 Pa. A method for manufacturing a bipolar transistor. 13. A light-receiving element for receiving an optical signal and outputting an electric signal, a first amplifier circuit for receiving an electric signal from the light-receiving element, and a second amplifier circuit for receiving an output of the first amplifier circuit. An optical discriminator that converts an output of the second amplifier circuit into a digital signal in synchronization with a predetermined clock signal, wherein the first amplifier circuit has a base on the light receiving element. A first bipolar transistor connected, a second bipolar transistor having a base connected to a collector of the first bipolar transistor and a collector connected to an input of the second amplifier circuit, 12. An optical receiver, wherein at least one of the first and second bipolar transistors is constituted by the bipolar transistor according to claim 1. system. 14. An optical receiving system according to claim 13, wherein each of said first and second bipolar transistors comprises the bipolar transistor according to any one of claims 1 to 11. 15. The semiconductor device according to claim 13, wherein said first and second bipolar transistors are formed on a single semiconductor chip, and said semiconductor chip and said light receiving element are mounted on a single substrate. The optical receiving system according to claim 14.