JPH1064820A - Manufacture of semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To manufacture a thin film semiconductor element having excellent characteristics with a high yield. SOLUTION: After a base film is formed by using a glass substrate of Corning 7059, etc., as a substrate 101, the substrate 101 is annealed at a temperature higher than the strain temperature (strain point) of the substrate 101 and gradually cooled to a temperature lower than the strain point. Thereafter, a thin film semiconductor element, such as the TFT, etc., is manufactured by forming a silicon film 104. When the substrate 101 is annealed at the temperature higher than the strain point and gradually cooled after annealing, the substrate 101 does not shrink much during the course of the succeeding heat treatment. Therefore, the yield of the semiconductor element is improved, because mask alignment can be performed easily and the occurrence of defects, etc., caused by deviated masks is reduced. In addition, the TFT characteristics of the semiconductor element are improved, because the interfacial characteristic of the base film is improved by the annealing.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to an insulating substrate made of glass or the like,
Alternatively, a semiconductor device formed on various substrates, for example,
Thin film transistor (TFT) and thin film diode (TF
D) or a method of manufacturing a thin film integrated circuit using the same, particularly a thin film integrated circuit for an active liquid crystal display device (liquid crystal display).

[0002]

2. Description of the Related Art In recent years, semiconductor devices having TFTs on an insulating substrate such as glass, for example, active type liquid crystal display devices and image sensors using TFTs for driving pixels have been developed. As a glass substrate, Corning 7 is used because of problems such as precipitation of impurities from the glass substrate and price.
059 glass is commonly used. The transition point temperature of this 7059 glass is 628 ° C., and the strain point is 593 ° C. Other practical glass materials having a strain point of 550 to 650 ° C. shown in Table 1 are known.

[0003]

[Table 1]

[0004] Thin film silicon semiconductors are generally used for TFTs used in these devices. Thin-film silicon semiconductors are roughly classified into two types: those made of an amorphous silicon semiconductor (a-Si) and those made of a crystalline silicon semiconductor. Amorphous silicon semiconductors are most commonly used because they have a low manufacturing temperature, can be manufactured relatively easily by a gas phase method, and have high mass productivity. Since it is inferior to a silicon semiconductor having
In order to obtain higher-speed characteristics in the future, it has been strongly required to establish a method for manufacturing a TFT made of a crystalline silicon semiconductor. Note that as the silicon semiconductor having crystallinity, polycrystalline silicon, microcrystalline silicon, amorphous silicon containing a crystal component, semi-amorphous silicon having an intermediate state between crystalline and amorphous, and the like are known. .

As a method of obtaining a silicon semiconductor in the form of a thin film having crystallinity, an amorphous semiconductor film is formed, and thermal energy is applied (thermal annealing) for a long time to obtain a crystalline silicon semiconductor. There is a known method. However, it is necessary to set the heating temperature to a high temperature of 600 ° C. or higher, which causes a problem that the substrate shrinks irreversibly. In particular, it has been impossible to perform such high-temperature processing after the patterning step. In addition, since the heating time required for crystallization is several tens of hours or more, it is necessary to shorten the heating time.

[0006] Regarding such a problem, recently, by adding a certain metal element having an effect as a catalyst for promoting crystallization, the crystallization temperature is lowered, and
It has been found that the crystallization time can be reduced. Metal elements (catalytic metal elements) that promote crystallization used for such purposes include Fe, Co, Ni, Ru, Rh, and P.
d, Os, Ir, Pt, Sc, Ti, V, Cr, Mn,
The effects of Cu, Zn, Au, and Ag have been confirmed.

These elements are formed over the entire surface of the silicon film.
When introduced evenly, crystal growth occurs perpendicular to the film, that is, in the direction of the film thickness. On the other hand, when crystal is introduced into a specific portion of the silicon film and crystallization is performed, the introduced portion is used as a starting point. Has the property of expanding the crystallization region (lateral growth property), and the silicon film crystallized in this manner has a higher field-effect mobility than that in which the catalytic metal element is uniformly introduced. .

However, in order to selectively introduce the catalytic metal element in this manner, patterning must be performed before the thermal annealing step of crystallization, and the introduction of the catalytic metal element due to the contraction of the substrate described above. In some cases may significantly deviate from the patterns of other elements and circuits. FIG. 4 shows an example in which a TFT is manufactured using such a means. Area 4 written by a dotted line in FIG.
Numerals 02 and 403 indicate ones where the active layer (silicon film) and the gate electrode should be originally patterned. A rectangular area 401 shown by a solid line is a pattern into which a catalytic metal element is introduced.

In this step, when thermal annealing is performed after the introduction of the catalytic metal element, the region 404 indicated by the ellipse in FIG. 4B is crystallized. That is, the area 404
Is a lateral crystal region. The size of the ellipse depends on the concentration of the catalytic metal element and the time and temperature of the thermal annealing. FIG.
As shown in (B), when the gate electrode and the active layer were formed at the positions where they should be, there was no problem because the channel formation region of the TFT was formed in the lateral crystal region.
However, since the substrate is actually shrunk by the thermal annealing step, the gate electrode and the active layer are each 40
5, 406, the region 404 does not overlap with the channel forming region. That is, in the channel formation region, the region indicated by the shaded portion 407 remains amorphous. As a matter of course, the characteristics of the TFT significantly deteriorate.

As described above, it is extremely difficult to perform patterning before processing at a high temperature due to shrinkage of the substrate. The high temperature in this case varies depending on the type of the substrate, but is relatively higher than 500 ° C. in the case of glass No. 7059 manufactured by Corning, which is often used.

[0011]

SUMMARY OF THE INVENTION The present invention provides means for solving the above problems. More specifically, the present invention discloses a means for suppressing the shrinkage of the substrate and a means for obtaining a semiconductor circuit / element having a higher yield and good characteristics.

[0012]

According to the present invention, a silicon oxide film, a silicon nitride film, an aluminum nitride or a multilayer film in which two or more of these are laminated is formed as a base film on a glass substrate by a plasma CVD method. The substrate is thermally annealed at a temperature equal to or higher than its strain point (strain temperature), preferably equal to or higher than the glass transition point, and then equal to or lower than 2 ° C./min, preferably equal to or lower than 0.5 ° C./min, and more preferably equal to or lower than 0.3 ° C. By gradually cooling the glass substrate to a temperature equal to or lower than the strain point at a speed equal to or lower than / minute, the shrinkage of the glass substrate itself in the subsequent heat treatment is suppressed. The cooling rate varies depending on the type of the substrate. In general, the lower the cooling rate, the better the characteristics are obtained. However, if the cooling rate is reduced, the processing time becomes longer and the mass productivity is reduced. Therefore, in selecting the temperature lowering rate, the processing time and the required characteristics must be considered. This heat treatment is preferably performed in an oxidizing or nitriding atmosphere.

For example, if a nitriding gas such as nitrogen, ammonia, or dinitrogen monoxide is used, the vicinity of the surface of the base film can be nitrided by these gases. Then, it is possible to prevent boron, barium, sodium, and the like, which are glass impurities, from being precipitated in a semiconductor formed in a later step, which is effective in forming a highly reliable semiconductor device.

When the glass substrate shrinks by heating, particularly when cooled slowly after the heating is completed, the glass substrate shrinks significantly and at the same time, local stress in the glass substrate is relieved. As a result, the larger the shrinkage, the smaller the shrinkage of the substrate in the subsequent heating step. In addition, the higher the heating temperature, the greater the effect. Therefore, even if the heat treatment is performed again thereafter, since the stress of the glass substrate is relaxed, there is little room for further shrinking or warping. Furthermore, in a heat treatment step after crystallization annealing or the like, when the temperature is rapidly cooled from the heating temperature,
It has been found that the glass substrate subjected to the thermal annealing treatment of the present invention hardly shrinks.

For example, for a Corning 7059 substrate (strain point 593 ° C., glass transition point 628 ° C.), 640 ° C., 4 ° C.
550 ° C at a rate of 0.2 ° C / min after thermal annealing for hours
The substrate taken out after being slowly cooled down shrinks by 1900 ppm before and after this thermal annealing and slow cooling, but hardly shrinks thereafter, for example, 20 ppm even after heat treatment at 550 ° C. for 8 hours. Only shrinkage occurred, and only 70 ppm shrunk even by heat treatment at 600 ° C. for 4 hours. At a temperature not exceeding the initial thermal annealing temperature (in this case, 640 ° C.), there was no shrinkage that would hinder use in the range where the heat treatment was performed thereafter.
Preferably, it is used at a temperature below the strain point. That is, it is preferable to perform a heat treatment (crystallization annealing or the like) at a temperature of 593 ° C. or lower for the Corning 7059 substrate. Further, the temperature of the thermal annealing is preferably performed at a temperature of ± 30 ° C. of the crystallization temperature of the silicon film.

For a substrate on which no processing was performed, 55
It shrank by 1000 ppm or more in a heat treatment at 0 ° C. for 8 hours, and if there was a patterning step before and after the heat treatment, mask alignment became impossible. Further, the shrinkage of the substrate due to the difference in the cooling rate after the heat treatment at 600 ° C. for 4 hours is as shown in Table 2, and it was possible to suppress the shrinkage to a practical degree by rapidly cooling at a speed higher than the normal cooling.

[0017]

[Table 2]

In order to perform such thermal annealing, the following method may be used. FIG. 9 shows an example of a heating furnace used in the present invention, in which a reaction tube 11 made of quartz, a substrate holding means (substrate holder) 12, and a substrate 13 arranged horizontally are shown. Although not shown in the figure, the apparatus is provided with a heater for heating the reaction tube 11 from outside. Also provided are means for supplying a predetermined gas into the reaction tube and means for moving the substrate holding means from the reaction tube to the outside.

FIG. 9 shows a state in which the glass substrate 13 is horizontally held by the substrate holding portion 12. Here, when the glass substrate is held horizontally, the substrate is bent, which is effective in preventing the planarity from being impaired. Such a configuration is useful when a step of applying a temperature higher than the strain point to the glass substrate is required. In the subsequent thermal annealing step such as crystallization and activation of the silicon film, the above configuration may be adopted.

In addition, a film formed after the above pre-heat treatment,
In the heat treatment necessary for crystal growth, oxidation, activation, etc., it is important to rapidly cool at a rate of 10 ° C./min to 300 ° C./min after heating. Especially ± 1 around the strain point of glass material
At 00 ° C., the rapid expansion and contraction of the glass material could suppress the expansion and contraction of the glass material. For example, Corning 7
In a process requiring a processing temperature of 493 to 693 ° C. for 059 glass, at least quenching up to 493 ° C. is effective in suppressing further shrinkage (elongation in some cases) to 30 ppm or less.

[0021]

As described above, the glass substrate is subjected to a thermal annealing process at a temperature equal to or higher than the strain point and then to a gradual cooling process.
Substrate shrinkage and the like rarely occur even in the subsequent heat treatment step (such as crystallization thermal annealing), which is convenient when patterning is necessary before and after the heat treatment step. Further, in order to form a semiconductor circuit or the like having a better yield and excellent characteristics, it is preferable to form the base film before the above-described thermal annealing and slow cooling of the substrate.
For example, when a catalytic metal element (such as nickel) is selectively introduced into a silicon film and lateral growth is performed, the stress of the underlying film is relaxed during thermal annealing at a temperature higher than the strain point as described above. It was found that the compound had an effect of promoting crystal growth.

Further, the silicon oxide film is formed on the uppermost layer (ie,
When used as a base film (on which a silicon film is formed), by performing thermal annealing at a high temperature as described above, characteristics similar to those of a thermal oxide film can be obtained, and characteristics can be improved. Was. Usually, a silicon film is formed in close contact with the underlying film, but many interface states are generated at the interface between the silicon film and the underlying film. This is remarkable especially when the film is formed by the plasma CVD method. This is because the quality of the underlying film itself is not good. Thermal annealing at a high temperature is preferable for improving the film quality, but thermal annealing at a temperature exceeding 600 ° C. has not been conventionally performed, and therefore, almost no improvement in the film quality was observed. However, in the present invention, since the annealing is performed at a temperature higher than the strain point of the substrate, the film quality is improved, and the characteristics of the semiconductor element are also improved. Further, the etching rate of the film also decreases. Decreasing the etching rate of the film is also indispensable for manufacturing a semiconductor device with good yield.

Conventionally, an obstacle to increasing the yield of semiconductor devices such as TFTs has been the problem of over-etching of the underlying film. Conventionally, in order to obtain an element such as a TFT, it has been general to pattern a silicon film and measure separation between the elements. FIG. 5 shows a conventional method. A base film 52 is formed on a substrate 51 with a material such as silicon oxide,
A silicon film 53 is deposited thereon. Then, a protective film 54 of a material such as silicon oxide or silicon nitride is formed thereon by a physical vapor deposition method (PVD method, for example, sputtering method) or a chemical vapor deposition method (CVD method, for example, plasma CVD method, optical CVD method, or the like. Law)
Formed by

Then, a coating of a photoresist material is further applied and patterned by a known photolithography method, and the photoresist 55 is selectively left. (FIG. 2A) The reason that the protective film 54 is provided is that, in this photolithography step, the silicon film and the photoresist film are directly
This is to prevent contact. That is, the silicon film existing under the photoresist is used later for the purpose of requiring extremely low contamination, such as an active layer of a TFT. However, these PVD
The insulating film formed by the CVD method or the CVD method has many pinholes, and therefore requires a thickness of several hundred degrees or more.

Then, the protection film 54 and the silicon film 53 are etched by dry etching or wet etching to form an island-shaped silicon film 56. A protective film 57 is in close contact with the upper surface of the island-shaped silicon film. The etching of the protective film is usually performed by wet etching, and the etching of the silicon film is usually performed by dry etching. Dry etching is used for etching the silicon film in order to prevent over-etching as much as possible. (Figure 2
(B))

Then, the photoresist 55 is peeled off by a known peeling means to obtain a state shown in FIG.
Thereafter, the protection film 27 remaining in the shape of the island-like silicon film is etched. In this case, the underlying film is also etched at the same time. In particular, in the case of isotropic etching such as wet etching, holes 5 as shown in FIG.
8 are formed. The degree x of this etching is determined by the difference in etching rate and the difference in thickness between the base film and the protective film.

For example, if both have the same etching rate, the underlying film is etched by at least the thickness of the protective film. Actually, since the etching is performed with a margin, the size of x becomes larger than the thickness of the protective film. In order to reduce x, it is necessary that the etching rate of the protective film is higher than that of the base film. However, in consideration of mass productivity, it is desirable to use silicon oxide formed by a plasma CVD method in both cases. It was difficult to make the etching rate of the underlying film lower than that of the protective film.

The under film is over-etched, and the holes 58 are formed.
Therefore, the step coverage of the gate insulating film 59 and the gate electrode 60 formed thereon is not good. For this reason, the insulation between the gate electrode and the active layer is insufficient, and a leak current occurs. In particular, in the gate electrode patterned in a stripe shape, the holes 58 remain without being filled by the formation of the gate insulating film, and during wet etching, an etchant enters and is etched from the lower surface of the gate electrode film. As a result, there is a problem that the gate electrode is disconnected. Similarly, in the case of a TFT that anodizes the gate electrode (for example, Japanese Patent Application Laid-Open No. 5-152335), the anodization proceeds not only from the upper surface but also from the lower surface of the gate electrode, and there is a problem that the disconnection still occurs. Met.

However, the problem of the etching rate was solved by the substrate thermal annealing step of the present invention. For example, TEOS (tetraethoxysilane, Si (OC
With respect to a silicon oxide film formed by a plasma CVD method using ₂ H ₅ ) ₄ ) as a source gas, 550 to 600
Although the etching rate was about 930 ° / min even after annealing at 4 ° C. for 4 hours, it was improved to 820 ° / min when annealing at 640 ° C. for 4 hours. This value is only about 10% larger than that of a thermal oxide film or a silicon oxide film formed by a sputtering method. Therefore, over-etching is prevented, and the above-mentioned failure caused by over-etching is also improved. Further, since a silicon oxide film formed by a plasma CVD method can be used as the base film, mass productivity is improved. In particular, when heat treatment is performed in an oxidizing atmosphere such as oxygen, nitrogen oxide, and ozone,
Since carbon and hydrogen in silicon oxide could be removed and dangling bonds of silicon could be filled with oxygen, the film quality could be further improved.

The glass substrate which has been subjected to the above-mentioned thermal annealing treatment does not shrink even by the subsequent heat treatment at a lower temperature, which is very convenient for forming a semiconductor element / circuit. In addition, by forming the base film before the thermal annealing and the slow cooling process, the characteristics of the base film can be improved, and the characteristics and yield of the semiconductor element can be improved. When a crystallization method in which a catalytic metal element must be selectively added is adopted, 500 to 600
Conventionally, there was a large problem of shrinkage of the substrate due to the presence of a patterning step interposed between a thermal annealing step (crystallization step) at ℃. However, according to the present invention, the patterning can be performed stably and the yield is high. Could be formed.

In the present invention, using a silicon oxide film formed by a plasma CVD method as a base film has a great advantage in terms of mass productivity. Conventionally, silicon oxide by sputtering has been most suitable in consideration of the characteristics and etching rate of the underlying film, but has a problem in that productivity (throughput) is low. According to the present invention, a silicon oxide film comparable to a sputtering method can be used as a base film even by plasma CVD.

[0032]

【Example】

[Embodiment 1] This embodiment forms a circuit in which a P-channel TFT (referred to as PTFT) and an N-channel TFT (referred to as NTFT) using a crystalline silicon film formed on a glass substrate are complementarily combined. Here is an example. The configuration of this embodiment can be used for a switching element of a pixel electrode and a peripheral driver circuit of an active type liquid crystal display device, as well as an image sensor and an integrated circuit.

FIG. 1 is a sectional view showing a manufacturing process of this embodiment. The patterning step and the main heat treatment step (excluding the thermal annealing / gradual cooling step of the substrate) in this embodiment are as follows. Patterning of nickel doping mask (Fig. 1
(See (A)) Crystallization annealing (550 ° C. or 600 ° C., FIG. 1)
(See (B)) Active layer patterning (See FIG. 1 (C)) Gate electrode patterning Contact hole patterning Source / drain electrode / wiring patterning (FIG. 1
(Refer to (D).) Among them, since a patterning step exists before and after the thermal annealing step, it is required that the substrate does not shrink in the thermal annealing step.

First, the substrate (Corning 7059) 101
CVD and plasma CVD using TEOS and oxygen as raw materials
A silicon oxide base film 102 having a thickness of 2000 ° was formed by the method. Next, using the thermal annealing furnace shown in FIG.
1, 600-660 ° C higher than the strain point (593 ° C),
For example, annealing is performed at 640 ° C. for 1 to 4 hours, for example, 4 hours, and then 0.1 to 0.5 ° C./min, for example, 0.2 ° C.
The temperature was gradually lowered to 450 to 590 ° C, for example, 550 ° C. The control of the cooling rate was performed by changing the flow rate of the atmospheric gas. It is desirable that this take-out temperature be equal to or lower than the maximum temperature of the subsequent heat treatment step. That is, in this embodiment, since the crystallization annealing temperature is the highest temperature thereafter, if the crystallization annealing temperature is 600 ° C.,
It is desirable to take out at the following temperature. In addition, the above-described thermal annealing was performed in an oxygen stream. This thermal annealing is desirably performed at an angle of ± 30 degrees or less from the horizontal in order to prevent the substrate from bending.

A mask 103 made of a photoresist or an etchable polyimide or a photosensitive polyimide (photonice) is formed on the substrate subjected to such processing.
Was formed and then patterned to form a region 100 where the underlying film was selectively exposed. (FIG. 1A) Then, a nickel film having a thickness of 5 to 20 °, for example, 10 ° was formed by a sputtering method. Since this nickel film is extremely thin, it does not strictly exhibit a shape as a film. The above figures of the film thickness are average. In this case, it was preferable to heat the substrate to 150 to 300 ° C.
It is preferable that the mask 103 has a certain heat resistance. After that, the mask 103 was removed. Then, an intrinsic (I-type) amorphous silicon film 104 having a thickness of 300 to 1500 Å, for example, 800 に よ っ て by plasma CVD, and a protective film 1 having a thickness of 200 に よ っ て by plasma CVD.
06 was formed.

Then, a nitrogen inert atmosphere (atmospheric pressure),
It was crystallized by thermal annealing at 550 ° C. for 8 hours or at 600 ° C. for 4 hours. At this time, in the region 100 where the nickel film was selectively formed, the crystallization of the crystalline silicon film 104 progressed in the direction perpendicular to the substrate 101. Then, in an area other than the area 100, as indicated by an arrow,
Crystal growth proceeded from the region 100 in the lateral direction (the direction parallel to the substrate). The area around the area 100 where nickel was directly formed and the area at the tip of the crystal growth were areas 105 where the nickel concentration was high. (FIG. 1 (B))

After this step, the silicon film was patterned to form a TFT island-shaped active layer 104 '. At this time, a tip portion of crystal growth (that is, a boundary between the crystalline silicon region and the amorphous silicon region,
(High nickel concentration) is important. This makes it possible to prevent carriers moving between the source and the drain from being affected by the nickel element in the channel formation region. The crystal growth distance in this step, that is, the distance from the nickel added region 100 to the tip of the crystal growth is at most 100 μm.
Met.

Conventionally, the nickel introduction mask 103
1000 pp due to the crystallization annealing step between the patterning of
m, that is, 5 on the top and bottom for a 100 mm square substrate
Such fine patterning could not be performed because the substrate shrank by as much as 0 μm. However, in the present embodiment, the shrinkage of the substrate is suppressed to 70 ppm or less, that is, 4 μm or less in the upper and lower directions, which is sufficiently possible.

The size of the active layer 104 'is determined in consideration of the TFT channel length and channel width. 50 μm × 20 μm for small objects, 100 μm ×
It was 1000 μm. Many such active layers were formed on the substrate. The silicon oxide film 10 having a thickness of 1200 ° is formed by plasma CVD using TEOS and oxygen as raw materials.
7 was formed into a gate insulating film. (Fig. 1 (C))

Subsequently, by a sputtering method,
Aluminum (including 0.01 to 0.2% scandium) having a thickness of 6000 to 8000 °, for example, 6000 ° was deposited. Then, the aluminum film was patterned to form gate electrodes 108 and 110. Further, the surface of the aluminum electrode was anodized to form oxide layers 109 and 111 on the surface. This anodization was performed in an ethylene glycol solution containing tartaric acid at 1 to 5%. The thickness of the obtained oxide layers 109 and 111 is 2
000Å. The oxides 109 and 111
Becomes the thickness for forming the offset gate region in the subsequent ion doping process, so that the length of the offset gate region can be determined in the anodic oxidation process.

Next, by an ion doping method (also referred to as a plasma doping method), a gate electrode portion (a gate electrode 108, an oxide layer 109 around the gate electrode 108, a gate electrode 11) is formed in an active layer region (constituting a source / drain and a channel).
0 and the surrounding oxide layer 111) as a mask, an impurity imparting P or N conductivity type is added in a self-aligned manner. Phosphine (PH ₃ ) and diborane (B ₂ H ₆ ) were used as the doping gas. In the former case, the acceleration voltage was 60 to 90 kV, for example, 80 kV, and in the latter case, the acceleration voltage was 40 to 80 kV, for example, 65 kV. The dose is 1 × 10 ¹⁵ to 8 × 10 ¹⁵ cm ⁻² , for example, 2 × 1
0 ¹⁵ cm ^-2 and boron was set to 5 × 10 ¹⁵ . At the time of doping, each element was selectively doped by covering one region with a photoresist. As a result, N-type impurity regions 115 and 117 and P-type impurity regions 112 and 114 are formed.
(PTFT) region and N-channel TFT (NTFT)
Area was formed.

Thereafter, annealing was performed by laser light irradiation. As the laser light, a KrF excimer laser (wavelength: 248 nm, pulse width: 20 nsec) was used, but another laser may be used. The irradiation condition of the laser light is such that the energy density is 200 to 400 mJ / c.
m ² , for example, 250 mJ / cm ^2, and 2
Irradiation was performed for 10 to 10 shots, for example, 2 shots. The effect may be increased by heating the substrate to about 200 to 450 ° C. during the irradiation with the laser light. (Figure 1
(D))

Subsequently, a silicon oxide film 11 having a thickness of 6000.degree.
8 was formed as an interlayer insulator by a plasma CVD method. As the interlayer insulator, polyimide or a two-layer film of silicon oxide and polyimide may be used. Further, a contact hole is formed, and a metal material, for example, a multilayer film of titanium nitride and aluminum is used to form a TFT electrode / wiring 1.
19, 120 and 121 were formed. Finally, annealing is performed at 350 ° C. for 30 minutes in a hydrogen atmosphere at 1 atm.
Was completed in a complementary type. (Figure 1
(E) The circuit shown above has a CMOS structure in which PTFTs and NTFTs are provided in a complementary manner. In the above-described process, two TFTs are simultaneously formed and cut at the center to form two independent TFTs. It is also possible to manufacture them at the same time.

In this embodiment, as a method for introducing nickel, nickel is selectively thinned on the base film 102 under the amorphous silicon film 104 (it is difficult to observe nickel as a thin film). And a method of growing crystals from this portion is adopted.
After the formation of 4, a method of selectively forming a nickel film may be used. That is, crystal growth may be performed from the upper surface of the amorphous silicon film, or may be performed from the lower surface. Alternatively, a method in which an amorphous silicon film is formed in advance and nickel ions are selectively implanted into the amorphous silicon film 104 by using an ion doping method may be employed. This case has a feature that the concentration of the nickel element can be finely controlled. Alternatively, a method using a plasma treatment or a CVD method may be used.

[Embodiment 2] This embodiment is an example in which an N-channel TFT is provided in each pixel as a switching element in an active liquid crystal display device. Hereinafter, one pixel will be described, but a large number (generally, hundreds of thousands) of other pixels are formed in a similar structure. Also, N
It goes without saying that a P-channel TFT may be used instead of a channel TFT. Further, it can be used not only for the pixel portion of the liquid crystal display device but also for the peripheral circuit portion. Further, it can be used for image sensors and other devices. That is, as long as it is used as a thin film transistor, its use is not particularly limited.

FIG. 2 shows an outline of the manufacturing process of this embodiment.
In this embodiment, as the substrate 201, an OA-2 substrate manufactured by NEC Corporation (strain point 635 ° C., thickness 1.1 mm,
00 × 400 mm). First, a base film 202 (silicon oxide) is formed on a substrate 201 by a plasma CVD method.
Å was formed. TEO as source gas for CVD
S and oxygen were used. After annealing the substrate subjected to such heat treatment at 700 ° C. at a temperature equal to or higher than the strain point for 2 hours,
It was gradually cooled to 600 ° C. at 0.2 ° C./min. Thermal annealing and slow cooling were performed in an oxygen stream. The shrinkage of the substrate was greatly reduced by the above heat treatment. For example, 600 ° C, 4
In the annealing for 20 hours, only shrinkage of 10 ppm was observed in the annealing at 550 ° C. for 4 hours.

Thereafter, a mask 203 was formed of polyimide in order to selectively introduce nickel. Then, a nickel film was formed by a sputtering method. This nickel film has a thickness of 5-
It was formed to a thickness of 200 °, for example, 20 °. Thus, the nickel film was selectively formed in the region 204.
(Fig. 2 (A))

Thereafter, LPCVD or plasma C
An amorphous silicon film 205 was formed to a thickness of 1000 ° by a VD method, and a silicon oxide film 206 having a thickness of 200 ° was formed as a protective film by a plasma CVD method. And 45
After dehydrogenation at 0 ° C. for 1 hour, crystallization was performed by heat annealing. This annealing step was performed at 600 ° C. for 4 hours in a nitrogen atmosphere. In this annealing step, since a nickel film was formed in a region 204 below the amorphous silicon film 205, crystallization occurred from this portion. During this crystallization, silicon crystal growth proceeded in a direction perpendicular to the substrate 201 in the region 204 where nickel was deposited. In addition, as indicated by arrows, in regions where nickel was not deposited (regions other than region 205), crystal growth proceeded in a direction parallel to the substrate. (FIG. 2 (B))

After this thermal annealing step, the crystallized silicon film was patterned to leave only the island-like active layer 205 'of the TFT and to remove the others. At this time, it is important that the tip of the grown crystal does not exist in the active layer, especially in the channel formation region. Specifically, in the silicon film 205 of FIG. 2B, at least the tip of crystallization and the portion of 204 into which nickel has been introduced are removed by etching, and the crystalline silicon film 205 is removed in a direction parallel to the substrate. It is preferable to use the intermediate portion where the crystal has grown as an active layer. This is to prevent the nickel concentrated at the front end portion from adversely affecting the characteristics of the TFT based on the fact that nickel is concentrated at the front end portion and the introduction portion of the crystal growth.

Thereafter, a gate insulating film of silicon oxide (thickness: 70 to 120 nm, typically 120 nm) is formed from TEOS by plasma CVD in an oxygen atmosphere.
207 were formed. The substrate temperature was 350 ° C. (Figure 2
(C) Next, a known film containing polycrystalline silicon as a main component is formed by a CVD method, and is patterned to form a gate electrode 2.
08 was formed. Phosphorus was introduced into polycrystalline silicon as an impurity in an amount of 0.1 to 5% in order to improve conductivity.

Thereafter, phosphorus was implanted as an N-type impurity by an ion doping method to form a source / drain region 210 and a channel formation region 209 in a self-aligned manner.
Then, by performing annealing at 550 ° C. for 4 hours, the crystallinity of the silicon film having deteriorated crystallinity due to ion implantation was improved. The active layer was easily crystallized because it originally contained nickel which has the effect of promoting crystallization. Due to this thermal annealing, the source / drain sheet resistance of this TFT is 300 to 800 Ω / c.
It became m ^2. (FIG. 2 (D))

Thereafter, an interlayer insulator 211 is formed of silicon oxide or polyimide, and further, a pixel electrode 212 is formed.
Was formed by ITO. Then, a contact hole is formed, and a chromium /
The electrodes 213 and 214 are formed of an aluminum multilayer film, and one of the electrodes 214 is also connected to the ITO 212. Finally, hydrogenation was performed by annealing in hydrogen at 200 to 400 ° C. for 2 hours. In this way,
The TFT was completed. This step is performed simultaneously in other many pixel regions. In order to further improve the moisture resistance, a passivation film may be formed on the entire surface using silicon nitride or the like. (FIG. 2 (E))

In the TFT manufactured in this embodiment, a crystalline silicon film grown in the direction in which carriers flow is used as an active layer constituting a source region, a channel formation region, and a drain region. Is not traversed by the carrier, that is, the carrier moves along the crystal grain boundary of the needle-like crystal, so that a TFT having high carrier mobility can be obtained. TFT manufactured in this example
Is an N-channel type, and its mobility is 90 to 130.
(Cm ² / Vs). The movement of a conventional N-channel TFT using a crystalline silicon film obtained by crystallization by thermal annealing at 600 ° C. for 48 hours is 50 to 70 (c).
m ² / Vs), which is a great improvement in characteristics.

In this embodiment, a thermal annealing means is used for activating the doping impurities. This is a milder reaction than the case where laser light is used as in the first embodiment. In particular, in laser annealing, the discontinuity of crystallinity at the boundary between the shadowed portion of the gate electrode portion and the portion irradiated with the laser caused a decrease in reliability. Since the / drain region was similarly heated, it was particularly excellent in reliability.

[Embodiment 3] This embodiment will be described with reference to FIG. No. 1733 glass (strain point: 640 ° C.) manufactured by Corning Incorporated was used as the substrate. The base film 302 is formed by a plasma CVD method on a glass substrate 301, furthermore, the more points the distortion of the substrate 700 ° C. of dinitrogen monoxide (N ₂
O) After annealing in an atmosphere for 1 hour, the sample was gradually cooled to 600 ° C. at a rate of 0.2 ° C./min. Then, an amorphous silicon film 304 having a thickness of 300 to 800 ° was formed by a plasma CVD method. Further, a silicon oxide mask 30 having a thickness of 1000 °
3 was used to form a nickel film in the region indicated by 300 in the same manner as in Example 1. Next, heat annealing at 550 ° C. for 8 hours was performed to crystallize the silicon film 304. At this time, as indicated by an arrow 305, crystal growth proceeded in a direction parallel to the substrate. (FIG. 3 (A))

Next, the mask 303 (which is also a protective film during crystallization annealing) was removed, and the silicon film 304 was patterned to form island-like active layer regions 306 and 307. At this time, the region indicated by 300 in FIG.
This is a region where nickel is directly introduced, and a region where nickel is present at a high concentration. Also, as shown in Examples 1 and 2, nickel also exists at a high concentration at the end point of crystal growth. It has been found that these regions have a nickel concentration that is nearly an order of magnitude higher than the crystallized regions between them. Therefore, in this embodiment, the active layer regions 306 and 307, which are regions for forming an active element, for example, a TFT, are patterned so as to avoid these regions having a high nickel concentration, and the regions having a high nickel concentration are intentionally formed. Removed. The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction. (FIG. 3
(B))

In the present embodiment, a complementary TFT circuit is obtained using the active layers 306 and 307. That is, the circuit of the present embodiment is different from the configuration of the first embodiment shown in FIG. 1D in that the PTFT and the NTFT are separated.
That is, in the structure shown in FIG.
The active layer of the FT is continuously connected, and the nickel concentration is high in the intermediate region. However, the present embodiment has a feature that the nickel concentration is low regardless of which part is taken. Therefore, operation stability can be improved.

Next, a silicon oxide or silicon nitride film 308 having a thickness of 200 to 3000 ° was formed by a plasma CVD method. Then, lamp annealing of visible / near infrared light was performed. A halogen lamp was used as an infrared light source. The wavelength is 0.5 which is well absorbed by crystalline silicon.
４4 μm, preferably 0.8-1.3 μm. The intensity of the visible / near-infrared light is 800 to 1300 ° C. on the single crystal silicon wafer of the monitor, typically 900 to 1
Adjusted to be between 200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. Note that the infrared light irradiation was performed in an H ₂ atmosphere. 0.1% to 10% HCl, a compound of hydrogen halide, fluorine, chlorine, or bromine may be mixed in the H ₂ atmosphere.

In this embodiment, when irradiating visible / near infrared light,
Since a protective film of silicon oxide or silicon nitride was formed on the surface of the active layer, it was possible to prevent the surface from being roughened and contaminated upon irradiation with infrared light. By using such a lamp annealing step together, it was possible to improve the crystallinity, which was insufficient only by crystallization by thermal annealing. (FIG. 3C) After the irradiation with visible / near infrared light, the protective film 308 was removed. After that, a gate insulating film 309 and gate electrodes 310 and 311 were formed as in Example 1. Tantalum is used as the gate electrode, and the surface of the gate electrode is anodized,
The tantalum oxide film is coated at 1000 to 3000
000 mm formed. Then, as in Example 1, an impurity element was introduced by ion doping to form source / drain regions.

The lamp annealing method was used to activate the impurities. A halogen lamp was used as an infrared light source. The wavelength is 0.5-4 μm, preferably 0.8-1.3.
Irradiation with visible / infrared light of μm was performed for 30 to 180 seconds. Visible / near infrared rays of the above wavelengths contain 10 ¹⁹ to 10 ²¹ phosphorus or boron.
It is easily absorbed by amorphous silicon to which cm ^{-3 is} added.
An effective anneal comparable to a thermal anneal of 00 ° C. or more can be performed. On the other hand, since it is hardly absorbed by the glass substrate, it is not necessary to heat the glass substrate to a high temperature, and the process can be performed in a short time. .
In particular, in the present embodiment, the processing is performed in advance so as not to cause the contraction of the substrate.

The intensity of the visible / near-infrared light was adjusted so that the temperature of the monitor on the single crystal silicon wafer was 800 to 1300 ° C., typically 900 to 1200 ° C. Specifically, the temperature of the thermocouple embedded in the silicon wafer was monitored and fed back to the infrared light source. Note that the infrared light irradiation was performed in an H ₂ atmosphere. 0.1% to 10% HCl, a compound of hydrogen halide, fluorine, chlorine, or bromine may be mixed in the H ₂ atmosphere. (FIG. 3 (D))

Thereafter, an interlayer insulator 312 is formed, and a contact hole is formed in the interlayer insulator 312.
14, 315 were formed. Further, hydrogenation was performed by annealing at 250 to 400 ° C., for example, 350 ° C. in a hydrogen atmosphere at 1 atm. (FIG. 3E) Thus, a complementary TFT circuit was formed. In the present embodiment, a protective film is formed on the surface of the active layer during lamp annealing (visible / near-infrared light irradiation), so that surface roughness and contamination are prevented. Therefore, the characteristics (electric field mobility and threshold voltage) and reliability of the TFT of this example were extremely good.

[Embodiment 4] This embodiment will be described with reference to FIG. The substrate used was NA4 manufactured by NH Techno Glass Co., Ltd.
Five glasses (strain point 610 ° C.) were used. Glass substrate 60
A two-layer base film was formed on the substrate 1 by a plasma CVD method. First, a silicon nitride film 602 was formed to a thickness of 1000 上 on a substrate, and a silicon oxide film 603 was formed to a thickness of 1000 さ ら に. The above film formation was performed continuously. The reason for forming the silicon nitride film 602 is to eliminate contamination by mobile ions and the like from the glass substrate.

Further, the substrate was annealed for 1 hour in an atmosphere of dinitrogen monoxide (N ₂ O) at 650 ° C. above the strain point, and then gradually cooled to 500 ° C. at a rate of 0.2 ° C./min. Then, an amorphous silicon film 604 having a thickness of 300 to 800 Å, for example, 500 Å was formed by a plasma CVD method. Further, a silicon oxide mask 605 having a thickness of 1000 ° was formed. Then, a nickel acetate film 606 was formed by a spin coating method using a nickel acetate aqueous solution.
The concentration of nickel is 50 to 300 ppm, for example, 100 ppm.
ppm. At this time, the nickel acetate film 606 has several
It is not necessarily a film because it is extremely thin, about several tens of kilometers. (FIG. 6 (A))

Next, heat annealing at 550 ° C. for 8 hours was performed to crystallize the amorphous silicon film 604. At this time, as indicated by arrows, crystal growth proceeded in a direction parallel to the substrate. Next, after removing the mask 605 (which is also a protective film during crystallization annealing), laser crystallization was performed to improve crystallinity. KrF excimer laser light (wavelength 248 nm) is 200 to 300 mJ / c
By irradiation with m ² , a crystalline silicon film 607 was obtained. (FIG. 6 (B))

After that, the crystalline silicon film 607 was patterned to form an island-shaped active layer region 611. On this occasion,
A region indicated by 608 in FIG. 6B is a region where nickel is directly introduced, and is a region where nickel is present at a high concentration. Also, as shown in Examples 1 and 2, nickel also exists at a high concentration at the end points 609 and 610 of the crystal growth. It has been found that these regions have a nickel concentration that is nearly an order of magnitude higher than the crystallized regions between them. Therefore, in the present embodiment, the active layer region, which is a region for forming an active element, for example, a pixel TFT, is patterned so as to avoid these regions having a high nickel concentration, and the high concentration region of nickel is intentionally removed. . The etching of the active layer was performed by the RIE method having anisotropy in the vertical direction.

Next, as the gate insulating film 612, a silicon oxide film having a thickness of 200 to 3000 Å, for example, 1000 Å was formed by a plasma CVD method. After that, thickness 1
An aluminum (containing 1 wt% of Si or 0.1 to 0.3 wt% of Sc) film of 000 to 3 μm, for example, 5000 Å was formed by a sputtering method.
Then, a photoresist was formed by a spin coating method. If an aluminum oxide film having a thickness of 100 to 1000 ° is formed on the surface by anodic oxidation before forming the photoresist, the adhesiveness of the photoresist is improved. Thereafter, the photoresist and the aluminum film were patterned to form a gate electrode 613. After the etching is completed, the photoresist is not removed, and the gate electrode 61 is not removed.
3 as a mask film 614.

Further, a porous anodic oxide 615 having a thickness of 3000 to 6000 °, for example, 5000 °, was formed by passing a current through the electrolyte in an electrolytic solution. The porous anodic oxidation may be performed using a 3 to 20% aqueous acid solution of citric acid or oxalic acid, phosphoric acid, chromic acid, sulfuric acid, or the like, and a constant current of 5 to 30 V may be applied to the gate electrode. In this example, in a oxalic acid solution (30 ° C.), the voltage was set to 10 V, and anodic oxidation was performed for 20 to 40 minutes. The thickness of the porous anodic oxide was controlled by the time for performing anodic oxidation. (FIG. 6 (C))

Thereafter, the mask 614 was peeled off and barrier anodic oxidation was performed. In this case, the substrate was adjusted to pH 7, 7, 1
The electrode was immersed in an ethylene glycol solution of ~ 3% tartaric acid, and the anode was used as a cathode with platinum as the anode and the voltage was gradually increased to proceed anodic oxidation. Thus, a dense and high withstand voltage barrier-type anodic oxide 616 was formed.
Then, the gate insulating film 612 was etched by a dry etching method. At this time, the anodic oxides 615, 6
16 was not etched, only the gate insulating film 612 was etched, and the etching was terminated when the island-shaped active layer 611 appeared. As a result, the porous anodic oxide 6
The gate insulating film 612 'under 15 remained without being etched. (FIG. 6 (D))

Thereafter, the porous anodic oxide 615 was removed by etching. Then, boron is implanted into the island-like active layer 611 as an impurity in the island-like active layer 611 in a self-aligned manner using the gate electrode portion (gate electrode, barrier type anodic oxide, silicon oxide film) as a mask. 617 were formed. Here, diborane (B ₂ H ₆ ) was used as the doping gas. At this time, the dose of boron is 1 to 4 × 10 ¹⁵ atoms / cm ² , and the acceleration voltage is 1
0 kV. Here, since the acceleration voltage is low, the lower part of the gate insulating film is not doped and boron is not introduced, and an offset region is formed. (FIG. 6E)

Further, this was subjected to thermal annealing at 350 to 550 ° C., for example, 500 ° C. for 4 hours to activate the doped impurities. Furthermore, in order to promote further activation, a KrF excimer laser (wavelength 2
48 nm and a pulse width of 20 nsec). The energy density of the laser was 200 to 400 mJ / cm ² , and preferably 250 to 300 mJ / cm ² .
At this time, the PI junction existing under the gate insulating film 612 ′ was sufficiently activated by the laser irradiation. Here, activation may be performed by thermal annealing. Next, a silicon oxide film was formed as an interlayer insulating film 619 at 3000 ° by a plasma CVD method.

Then, the interlayer insulating film 619 was etched to form a contact hole in the source region.
Thereafter, an aluminum film was formed by a sputtering method, and patterning was performed to form a source electrode 619. (FIG. 6F) Finally, a passivation film 620 having a thickness of 1000 to 1000
A silicon nitride film of 6000Å, for example, 3000Å was formed by a plasma CVD method, and the interlayer insulating film 618 was etched to form a contact hole in the drain. Thereafter, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 621. (FIG. 6G) As described above, a pixel TFT having a P-channel type offset region was formed.

[Embodiment 5] This embodiment will be described with reference to FIG. No. 1733 glass manufactured by Corning was used as the substrate. First, a base film was formed over a glass substrate 701. Here, an aluminum nitride film 702 is formed on a substrate by sputtering at a thickness of 1000 Å, and a silicon oxide film 703 is formed on the substrate by a plasma CVD method at a thickness of 1000 Å.
A film was formed to form an underlayer consisting of two layers. The reason for forming the aluminum nitride film 702 is to eliminate contamination by mobile ions and the like from the glass substrate.

Further, after annealing the substrate in a nitrogen (N ₂ ) atmosphere at 700 ° C. above the strain point for 1 hour,
At 600 ° C./min. And plasma CVD
An amorphous silicon film 704 having a thickness of 300 to 800 Å, for example, 500 に よ っ て is formed by the method. In addition, thickness 1000
A mask 705 of silicon oxide was formed. And, by spin coating method using nickel acetate solution,
A nickel acetate film 706 was formed. (FIG. 7 (A))

Next, heat annealing was performed at 550 ° C. for 8 hours to crystallize the amorphous silicon film 704. At this time, as indicated by arrows, crystal growth proceeded in a direction parallel to the substrate. Next, after removing the mask, laser crystallization was performed to improve crystallinity. The crystalline silicon film 707 was obtained by irradiating a KrF excimer laser beam at 200 to 300 mJ / cm ² .
(FIG. 7B) After that, the crystalline silicon film 707 was patterned to form an island-shaped active layer region 711. At this time, as in Example 4, the active layer was formed avoiding the region where the nickel concentration was high.

Next, as the gate insulating film 712, a silicon oxide film having a thickness of 200 to 3000 例 え ば, for example, 1200 Å was formed by a plasma CVD method. After that, thickness 1
An aluminum film of 000 ° to 3 μm, for example, 6000 ° was formed by a sputtering method. Then, a gate electrode 713, a photoresist mask 714, and a porous anodic oxide 715 were formed in the same manner as in Example 4. (FIG. 7 (C)

Thereafter, the mask 714 was peeled off and barrier anodic oxidation was carried out to form a barrier anodic oxide 716. Then, as a result of etching the gate insulating film by the dry etching method, the porous anodic oxide 71 is formed.
The gate insulating film 712 'under 6 remains. (FIG. 7
(D)) Thereafter, the porous anodic oxide 715 is removed by etching, and a gate electrode portion (gate electrode, barrier anodic oxide, silicon oxide film) is formed on the island-shaped active layer region 711 by ion doping. Is used as a mask, boron is implanted as an impurity in a self-aligned manner to form a P-type impurity region 717. (FIG. 7E)

Further, a KrF excimer laser (wavelength 2
Irradiation of 48 nm and a pulse width of 20 nsec) was performed to activate the impurity region 717. Further, in order to improve the junction between the source / channel and the drain / channel, thermal annealing was performed at 350 to 550 ° C., for example, 500 ° C. for 4 hours. Next, a silicon oxide film is formed as an interlayer insulating film 718 by plasma CVD at 3000.
Was formed. Then, the interlayer insulating film 718 was etched to form a contact hole in the source region.
Thereafter, an aluminum film was formed by a sputtering method, and patterning was performed to form a source electrode 719. (FIG. 7F) Finally, a passivation film 720 having a thickness of 2000 to 2000
A silicon nitride film of 6000Å, for example, 3000Å was formed by a plasma CVD method, and the interlayer insulating film 718 was etched to form a contact hole in the drain. Thereafter, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 721. (FIG. 7G) As described above, the pixel TFT having the P-channel type offset region was formed.

[Embodiment 6] This embodiment will be described with reference to FIG. No. 7059 glass manufactured by Corning was used as the substrate. First, a base film was formed over a glass substrate 801. Here, a silicon oxide film 802 is formed on a substrate by a plasma CVD method to a thickness of 1000 °
A silicon nitride oxide film 803 was formed at a thickness of 1000 ° by a VD method to form a two-layer base film.

Further, after annealing the substrate in an ammonia (NH ₃ ) atmosphere at 640 ° C. above the strain point for 1 hour,
It was gradually cooled to 400 ° C. at 0.2 ° C./min. Then, a thickness of 300 to 800 °, for example, 5
An amorphous silicon film 804 of 00 ° was formed. Further, a mask 805 of silicon oxide having a thickness of 1000 ° was formed. Then, a nickel acetate film 806 was formed by a spin coating method using a nickel acetate solution. (FIG. 8
(A)) Next, heat annealing at 550 ° C. for 8 hours was performed to crystallize the amorphous silicon film 804. At this time, as indicated by arrows, crystal growth proceeded in a direction parallel to the substrate.

Next, after removing the mask, laser crystallization was performed to improve the crystallinity. By irradiating with a KrF excimer laser beam at 200 to 300 mJ / cm ² , a crystalline silicon film 807 was obtained. (FIG. 8
(B)) Thereafter, the crystalline silicon film 807 was patterned to form an island-shaped active layer region 811. At this time, as in Example 4, the active layer was formed avoiding the region where the nickel concentration was high. At this time, etching was performed by the RIE method. However, since the etching rate of the silicon nitride oxide film 803 was much lower than that of the silicon film, overetching of the base film was small.

Next, as the gate insulating film 812, a silicon oxide film having a thickness of 200 to 3000 例 え ば, for example, 1200 Å was formed by a plasma CVD method. After that, thickness 1
An aluminum film of 000 ° to 3 μm, for example, 6000 ° was formed by a sputtering method. Then, a gate electrode 813, a photoresist mask 814, and a porous anodic oxide 815 were formed in the same manner as in Example 4. (FIG. 8 (C))

Thereafter, the mask 814 was peeled off and barrier anodic oxidation was performed to form a barrier anodic oxide 816. Then, as a result of etching the gate insulating film by the dry etching method, the porous anodic oxide 81 is formed.
The gate insulating film 812 'under 6 remains. (FIG. 8
(D))

Thereafter, the porous anodic oxide 815 is etched and removed, and the porous anodic oxide 815 is removed by ion doping.
A gate electrode portion (gate electrode,
Using a barrier-type anodic oxide, a silicon oxide film) as a mask, boron as an impurity was implanted in a self-aligned manner to form a P-type impurity region 817. (FIG. 8E) Further, thermal annealing at 350 to 550 ° C., for example, 500 ° C. for 4 hours was performed to activate the doped impurities. Then, in order to more preferably activate, a KrF excimer laser (wavelength 248 n
m, pulse width 20 nsec). Thereafter, in order to improve the characteristics of the source / channel junction and the drain / channel junction, 350 to 550 ° C., for example, 4 ° C.
Annealing was performed at 80 ° C. for 1 hour. Next, a silicon oxide film was formed as an interlayer insulating film 818 at 3000 ° by a plasma CVD method.

Then, the interlayer insulating film 818 was etched to form a contact hole in the source region.
Thereafter, an aluminum film was formed by a sputtering method, and patterning was performed to form a source electrode 819. (FIG. 8F) Finally, a passivation film 820 having a thickness of 2000 to 2000 is formed.
A silicon nitride film of 6000Å, for example, 3000Å was formed by a plasma CVD method, and the interlayer insulating film 718 was etched to form a contact hole in the drain. Thereafter, an indium tin oxide film (ITO film) was formed, and this was etched to form a pixel electrode 821. (FIG. 8G) As described above, the pixel TFT having the P-channel type offset region was formed.

[0086]

As described above, the substrate is thermally annealed at a temperature equal to or higher than the strain point and gradually cooled, whereby the shrinkage of the substrate due to the subsequent heat treatment becomes very small. Generally, the patterning step (mask alignment step) of introducing nickel as shown in the embodiment does not require much accuracy compared to other patterning steps. On the other hand, patterning for forming contact holes and forming gate electrodes requires an accuracy of several μm or less. For this reason, conventionally, activation of doping impurities has mainly been performed by laser annealing which does not substantially involve a thermal process.

However, according to the present invention, since the substrate shrinkage can be suppressed to a considerable temperature, it is more suitable for mass production such as thermal annealing as shown in Embodiment 2 and lamp annealing as shown in Embodiment 3. Means can be used. As described above, the present invention is extremely effective for forming a semiconductor device on an insulating substrate.

[Brief description of the drawings]

FIG. 1 shows a manufacturing process of a TFT of Example 1.

FIG. 2 illustrates a manufacturing process of a TFT of Example 2.

FIG. 3 illustrates a manufacturing process of a TFT according to a third embodiment.

FIG. 4 shows an example of a conventional patterning shift due to substrate shrinkage.

FIG. 5 shows an example of conventional over-etching of a base film when forming a TFT.

FIG. 6 shows a process for manufacturing a TFT of Example 4.

FIG. 7 shows a process for manufacturing a TFT of Example 5.

FIG. 8 shows a manufacturing process of the TFT of Example 6.

FIG. 9 shows a configuration example of a thermal annealing furnace used in the present invention.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 nickel-introduced portion 101 glass substrate 102 base film (silicon oxide film) 103 mask 104 silicon film 104 ′ island-like silicon film (active layer) 105 region with high nickel concentration 106 protective film (silicon oxide) 107 gate insulating film (oxidation) Silicon film) 108 gate electrode (aluminum) 109 anodized layer (aluminum oxide) 110 gate electrode 111 anodized layer 112 source (drain) region 113 channel forming region 114 drain (source) region 115 source (drain) region 116 channel forming region 117 drain (source) region 118 interlayer insulator 119 electrode 120 electrode 121 electrode

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Shoji Miyanaga, 398 Hase, Hase, Atsugi, Kanagawa Prefecture, Japan (72) Inventor Hisashi Ohtani, 398 Hase, Hase, Atsugi, Kanagawa, Japan 72) Inventor Hirohide Zhang 398 Hase, Atsugi-shi, Kanagawa, Japan Semiconductor Energy Laboratory Co., Ltd. (72) Inventor Yasuhiko Takemura 398 Hase, Atsugi-shi, Kanagawa, Japan Semiconductor Energy Laboratory, Inc.

Claims (7)

[Claims] A first step of forming a base film on a glass substrate; a second step of thermally annealing the glass substrate at a first temperature equal to or higher than a strain point thereof; A third step of gradually cooling to a second temperature below the strain point at a rate of not more than ° C./min, a fourth step of selectively forming a catalyst film on the undercoat film, A fifth step of forming an amorphous silicon film on the catalyst film; and a sixth step of thermally annealing the substrate at a temperature in the range of 30 ° C. above and below the temperature at which the amorphous silicon film crystallizes. When,
A method for manufacturing a semiconductor device, comprising: 2. A first step of forming a base film on a glass substrate; a second step of thermally annealing the glass substrate at a first temperature equal to or higher than a strain point thereof; A third step of gradually cooling to a second temperature below the strain point at a rate of not more than ° C./min, a fourth step of forming an amorphous silicon film on the base film, and the amorphous silicon film Of selectively forming a catalyst film on the substrate
And a sixth step of thermally annealing the substrate at a temperature in the range of 30 ° C. above and below the temperature at which the amorphous silicon film is crystallized. A first step of forming a base film on the glass substrate; a second step of shrinking the glass substrate by 1000 ppm or more by thermally annealing the glass substrate at a first temperature equal to or higher than a strain point thereof; A third step of selectively forming a catalyst film on the base film; a fourth step of forming an amorphous silicon film on the base film and on the catalyst film; Fifth, the amorphous silicon film is crystallized from the selectively formed region of the film.
And a method of manufacturing a semiconductor device. 4. A first step of forming a base film on a glass substrate, a second step of causing the glass substrate to contract by 1000 ppm or more by thermally annealing the glass substrate at a first temperature equal to or higher than its strain point; A third step of forming an amorphous silicon film on the base film, and a fourth step of selectively forming a catalyst film on the amorphous silicon film.
A step of crystallizing the amorphous silicon film from the selectively formed region of the catalyst film by performing thermal annealing.
And a method of manufacturing a semiconductor device. 5. The method for manufacturing a semiconductor device according to claim 1, wherein the base film is silicon oxide, silicon nitride, aluminum nitride, or a multilayer film thereof formed by a plasma CVD method. 6. The method for manufacturing a semiconductor device according to claim 1, wherein the second step is performed in an oxidizing atmosphere. 7. The method for manufacturing a semiconductor device according to claim 1, wherein the second step is performed in a nitriding atmosphere.