JPH1050767A - Semiconductor device and method for mounting the same - Google Patents

Semiconductor device and method for mounting the same

Info

Publication number
JPH1050767A
JPH1050767A JP8223097A JP22309796A JPH1050767A JP H1050767 A JPH1050767 A JP H1050767A JP 8223097 A JP8223097 A JP 8223097A JP 22309796 A JP22309796 A JP 22309796A JP H1050767 A JPH1050767 A JP H1050767A
Authority
JP
Japan
Prior art keywords
bump
electrode
electrodes
semiconductor device
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8223097A
Other languages
Japanese (ja)
Other versions
JP3410298B2 (en
Inventor
Mitsuru Mura
満 村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Corp
Original Assignee
Sony Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Corp filed Critical Sony Corp
Priority to JP22309796A priority Critical patent/JP3410298B2/en
Publication of JPH1050767A publication Critical patent/JPH1050767A/en
Application granted granted Critical
Publication of JP3410298B2 publication Critical patent/JP3410298B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector

Landscapes

  • Wire Bonding (AREA)

Abstract

PROBLEM TO BE SOLVED: To improve the reliability of electric connection with a wiring board, irrespective of the repetitive temp. change by laminating conductive layers of a conductive material on first electrodes formed on one surface of a semiconductor device to form bump electrodes. SOLUTION: A semiconductor device 1 has bumps 5 having a laminate structure of laminated conductive layers which will cleave in a stress acting direction perpendicular to the conductive layer laminating direction if stressed in this direction. If a bump 5 is stressed because of the thermal expansion coefficient difference between the device 1 and substrate 2, the bump will hold the electric connection of a pad 3 and land 4 whereas it deforms to escape the stress. When the ordinary temp. is recovered, the bump 5 recovers the original shape. Thus it is possible to hold the electric connection and ensure a good electric connection with the wiring board, irrespective of the repetitive temp. change.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【目次】以下の順序で本発明を説明する。 発明の属する技術分野 従来の技術 発明が解決しようとする課題 課題を解決するための手段 発明の実施の形態 (1)第1実施例(図1〜図3) (2)第2実施例(図4及び図5) (3)他の実施例 発明の効果[Table of Contents] The present invention will be described in the following order. BACKGROUND OF THE INVENTION Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) First Embodiment (FIGS. 1 to 3) (2) Second Embodiment (FIG. 4 and FIG. 5) (3) Other Embodiments Advantages of the Invention

【0002】[0002]

【発明の属する技術分野】本発明は半導体装置及び半導
体装置の実装方法に関し、例えばフリツプチツプ法によ
り突起電極(いわゆるバンプ)が複数設けられた半導体
装置及び半導体装置の実装方法に適用して好適なもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a semiconductor device mounting method, and more particularly, to a semiconductor device provided with a plurality of projecting electrodes (so-called bumps) by a flip-chip method and a method suitable for mounting the semiconductor device. It is.

【0003】[0003]

【従来の技術】近年、電子機器においては、回路構成を
小型化及びコンパクト化することが望まれており、その
ためにICチツプ等の半導体装置を高密度実装する技術
が重要なポイントになつている。こうした高密度実装を
実現するための技術として、現在、フリツプチツプ法が
注目されている。
2. Description of the Related Art In recent years, in electronic equipment, it has been desired to reduce the circuit configuration in size and size, and for that purpose, the technology for mounting semiconductor devices such as IC chips at high density has become an important point. . As a technique for realizing such high-density mounting, a flip-chip method is currently receiving attention.

【0004】通常、ベアチツプを用いたフリツプチツプ
実装では、まずベアチツプの回路面に形成されている複
数の電極(以下、これをパツドと呼ぶ)上に、メツキ法
や蒸着法を用いて、錫(Sn)と鉛(Pb)の合金であ
るはんだで突起電極(以下、これをバンプと呼ぶ)を形
成する。この後ベアチツプの回路面と配線基板の一面と
を対向させて、ベアチツプの回路面上に形成したバンプ
を配線基板の一面に設けられた対応するランドと当接さ
せる。ここでランドには予めはんだが塗布されている。
こうしてそれぞれ対応するランドにバンプを当接させた
後に、当該配線基板を例えばリフロー装置内で加熱す
る。バンプ及びランド上に塗布されたはんだは当該加熱
によつて溶融して接合し、ベアチツプの回路面上のパツ
ドと配線基板上のランドとを電気的に接続する。このよ
うにベアチツプはバンプを介して配線基板上に実装され
る。
Normally, in flip-chip mounting using a bare chip, first, tin (Sn) is formed on a plurality of electrodes (hereinafter referred to as pads) formed on the circuit surface of the bare chip by using a plating method or a vapor deposition method. ) And lead (Pb) are formed into a bump electrode (hereinafter, referred to as a bump) by using a solder as an alloy. Thereafter, the circuit surface of the bare chip and the one surface of the wiring board are opposed to each other, and the bump formed on the circuit surface of the bare chip is brought into contact with a corresponding land provided on one surface of the wiring substrate. Here, solder is applied to the lands in advance.
After the bumps are brought into contact with the corresponding lands in this way, the wiring board is heated, for example, in a reflow device. The solder applied to the bumps and lands is melted and joined by the heating, and electrically connects the pads on the circuit surface of the bare chip to the lands on the wiring board. Thus, the bare chip is mounted on the wiring board via the bump.

【0005】このようなフリツプチツプ法を用いてベア
チツプを配線基板上に実装した場合、ワイヤボンデイン
グ等の手法を用いて実装した場合に比して、パツドと当
該パツドに対応するランドとの間の長さを短くし得、両
者間を接合する接合部、すなわちバンプのインダクタン
ス及び容量を低減させることができ、かくして電子機器
の回路構成を小型化及びコンパクト化し得ると共に、ベ
アチツプの高速特性及び高周波特性を向上させることが
できる。因みにベアチツプを形成する部材としては一般
にシリコンが用いられており、また配線基板を形成する
部材としてはガラスエポキシ又はセラミツク等が用いら
れている。
When a bare chip is mounted on a wiring board using such a flip-chip method, the length between the pad and the land corresponding to the pad is larger than when the bare chip is mounted using a method such as wire bonding. In addition, the inductance and the capacitance of the junction, that is, the bump, can be reduced, and the circuit configuration of the electronic device can be reduced in size and size, and the high-speed characteristics and high-frequency characteristics of the bare chip can be improved. Can be improved. Incidentally, silicon is generally used as a member forming the bare chip, and glass epoxy or ceramic is used as a member forming the wiring board.

【0006】[0006]

【発明が解決しようとする課題】ところがこうしてフリ
ツプチツプ法を用いてベアチツプを配線基板上に実装し
た場合、温度変化によつてバンプが破断し、これにより
ベアチツプと配線基板との電気的接続の信頼性が低下す
るという問題があつた。
However, when the bare chip is mounted on the wiring board by using the flip-chip method, the bump breaks due to a change in temperature, and the reliability of the electrical connection between the bare chip and the wiring board is thereby reduced. There is a problem that is reduced.

【0007】すなわち、回路をオン状態にしてベアチツ
プに電流を流した場合、内部回路が動作して電力を消費
することによりベアチツプが発熱する。また回路をオフ
状態にしてベアチツプに流れる電流を遮断した場合、回
路動作が停止してベアチツプの温度は室温まで低下す
る。このため回路をオン状態にして熱を生じた場合に、
ベアチツプを形成する部材と配線基板を形成する部材と
がそれぞれの熱膨張係数に応じて伸長する。しかし両者
の熱膨張係数が異なるために両者の伸び量の差分に応じ
て歪みが発生し、この歪みから両者を接合しているバン
プに応力がかかることになる。したがつてこうした状態
の変化が回路のオン及びオフの切り換えによつて繰り返
され、バンプが金属疲労して破断することになる。因み
にこうしたバンプの破断は回路のオン及びオフの切り換
えによつてのみ生じるものでは無く、外部環境の温度変
化によつても生じる可能性がある。
That is, when a current is supplied to the bare chip with the circuit turned on, the internal circuit operates and consumes electric power, so that the bare chip generates heat. If the circuit is turned off to interrupt the current flowing through the bare chip, the circuit operation stops and the temperature of the bare chip drops to room temperature. Therefore, when heat is generated by turning on the circuit,
The member forming the bare chip and the member forming the wiring board extend according to their respective thermal expansion coefficients. However, since the two have different coefficients of thermal expansion, a distortion is generated in accordance with the difference in the amount of elongation between them, and a stress is applied to the bump joining the two from the distortion. Therefore, such a change in state is repeated by switching the circuit on and off, and the bump is broken due to metal fatigue. Incidentally, the breakage of the bump is not caused only by switching the circuit on and off, but may also be caused by a temperature change of the external environment.

【0008】こうした問題を回避するために、ベアチツ
プと配線基板との隙間にエポキシ樹脂等を封入する手法
が考えられる。こうした手法によつてバンプにかかる応
力は封入されたエポキシ樹脂等により緩和され、信頼性
を向上させることができる。しかし当該手法はバンプに
かかる応力を完全には除去し得ず、上述の問題を根本的
に解決しているわけでは無い。したがつて温度変化によ
るバンプの破断は完全には回避し得ず、長期間での信頼
性の高い電気的接続を得ることが困難であつた。
In order to avoid such a problem, a method of encapsulating an epoxy resin or the like in a gap between the bare chip and the wiring board can be considered. By such a method, the stress applied to the bump is reduced by the encapsulated epoxy resin or the like, and the reliability can be improved. However, this method cannot completely remove the stress applied to the bump, and does not fundamentally solve the above-mentioned problem. Therefore, the breakage of the bump due to the temperature change cannot be completely avoided, and it has been difficult to obtain a reliable electrical connection for a long period of time.

【0009】本発明は以上の点を考慮してなされたもの
で、繰り返しの温度変化に係わらず、配線基板との電気
的接続の信頼性を向上し得る半導体装置及び半導体装置
の実装方法を提案しようとするものである。
The present invention has been made in view of the above points, and proposes a semiconductor device and a semiconductor device mounting method capable of improving the reliability of electrical connection with a wiring board regardless of repeated temperature changes. What you want to do.

【0010】[0010]

【課題を解決するための手段】かかる課題を解決するた
め本発明においては、半導体装置の一面側に設けられた
第1の電極上にそれぞれ、導電材からなる導電層を複数
積層して突起電極を形成する。
According to the present invention, a plurality of conductive layers made of a conductive material are laminated on a first electrode provided on one surface of a semiconductor device. To form

【0011】突起電極に温度環境の変化に起因する応力
が加えられた場合、突起電極の各導電層がへき開して変
形することにより、破断すること無く電気的接続を維持
することができる。
When a stress caused by a change in the temperature environment is applied to the bump electrode, each conductive layer of the bump electrode is cleaved and deformed, so that electrical connection can be maintained without breaking.

【0012】また本発明においては、第1の電極上にそ
れぞれ形成された各突起電極を収縮性を有した樹脂材で
なる被覆部によつて被覆する。
In the present invention, each protruding electrode formed on the first electrode is covered with a covering portion made of a resin material having shrinkage.

【0013】突起電極に温度環境の変化に起因する応力
が加えられた場合、被覆部の収縮力によつて突起電極の
組織に破断による隙間が生じることを防止して、電気的
接続を維持することができる。
When a stress caused by a change in the temperature environment is applied to the protruding electrode, a gap due to breakage in the structure of the protruding electrode due to the contraction force of the covering portion is prevented, and the electrical connection is maintained. be able to.

【0014】[0014]

【発明の実施の形態】以下図面について、本発明の一実
施例を詳述する。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

【0015】(1)第1実施例 図1において、半導体素子1は基板2の回路面である一
面上に実装されており、半導体素子1の一面に設けられ
た第1の電極3(以下、これをパツド3と呼ぶ)と基板
2上に設けられた第2の電極4(以下、これをランド4
と呼ぶ)とが、パツド3表面に形成された突起電極5
(以下、これをバンプ5と呼ぶ)を介して電気的に接続
されている。また半導体素子1と基板2との隙間には封
止樹脂6が封入されている。封止樹脂6は半導体素子1
と基板2との熱膨張係数の違いに起因してバンプ5にか
かる応力を緩和すると共に、半導体素子1の回路面を覆
つて外気に含まれた不純物や水分から保護するようにな
されている。
(1) First Embodiment In FIG. 1, a semiconductor device 1 is mounted on one surface of a substrate 2 which is a circuit surface, and a first electrode 3 (hereinafter, referred to as a first electrode) provided on one surface of the semiconductor device 1 is provided. This is called a pad 3 and a second electrode 4 (hereinafter referred to as a land 4) provided on the substrate 2.
Is referred to as “protruding electrode 5” formed on the surface of the pad 3.
(Hereinafter, referred to as bumps 5). A sealing resin 6 is sealed in a gap between the semiconductor element 1 and the substrate 2. The sealing resin 6 is the semiconductor element 1
The stress applied to the bumps 5 due to the difference in thermal expansion coefficient between the semiconductor element 1 and the substrate 2 is reduced, and the circuit surface of the semiconductor element 1 is covered to protect it from impurities and moisture contained in the outside air.

【0016】図1との対応部分に同一符号を付した図2
に示すように、バンプ5は鱗片状でなる導電体の層(以
下、これを導電層と呼ぶ)が複数積層された円柱形状の
突起電極でなる。バンプ5を形成する各導電層は隣接す
る他の層と当接しており、この当接によつてパツド3及
びランド4間が電気的に接続された状態となつている。
このため、バンプ5は導電層の積層方向に応力が与えら
れた場合、変形すること無くパツド3とランド4との電
気的接続を維持する。
FIG. 2 in which parts corresponding to those in FIG.
As shown in FIG. 5, the bump 5 is a columnar projecting electrode in which a plurality of scale-like conductor layers (hereinafter, referred to as conductive layers) are stacked. Each conductive layer forming the bump 5 is in contact with another adjacent layer, and by this contact, the pad 3 and the land 4 are electrically connected.
Therefore, when a stress is applied to the bump 5 in the stacking direction of the conductive layers, the bump 5 maintains the electrical connection between the pad 3 and the land 4 without deformation.

【0017】一方、図1との対応部分に同一符号を付し
た図3に示すように、温度環境等が変化した場合、基板
2の膨張係数(例えば一般的なガラスエポキシ基板の場
合、約18[ppm/ ℃] )と半導体素子1の膨張係数(例
えば一般的に用いられるシリコンの場合、約3[ppm/
℃] )とが異なるため、両者の膨張係数の差に室温から
の温度差を乗じた分、変位が生じてバンプ5に当該変位
により導電層の積層方向と垂直な方向に応力が加えられ
る。ここでは図中に示すAが半導体素子1の変位量を示
しており、図中に示すBが基板2の変位量を示してい
る。
On the other hand, as shown in FIG. 3 in which the same reference numerals are given to the portions corresponding to FIG. 1, when the temperature environment or the like changes, the expansion coefficient of the substrate 2 (for example, about 18 in the case of a general glass epoxy substrate). [ppm / ° C.]) and the expansion coefficient of the semiconductor element 1 (for example, about 3 [ppm /
[° C.])), the displacement is generated by multiplying the difference between the two expansion coefficients by the temperature difference from room temperature, and a stress is applied to the bump 5 in the direction perpendicular to the lamination direction of the conductive layer due to the displacement. Here, A shown in the figure indicates the amount of displacement of the semiconductor element 1, and B shown in the figure indicates the amount of displacement of the substrate 2.

【0018】この際、バンプ5の各導電層は物理的には
接合していないため、各導電層が当接することでパツド
3とランド4との電気的接続を維持しつつも、当該応力
に応じた方向に変形(いわゆるへき開)するようになさ
れている。ちなみに常温に戻り半導体素子1及び基板2
の膨張が無くなつた場合は、元の状態(図2)に復元す
る。
At this time, since the respective conductive layers of the bump 5 are not physically joined, the respective conductive layers come into contact with each other to maintain the electrical connection between the pad 3 and the land 4 and to withstand the stress. Deformation (so-called cleavage) in a corresponding direction is performed. By the way, the semiconductor element 1 and the substrate 2 are returned to room temperature.
When the expansion of の has disappeared, the original state (FIG. 2) is restored.

【0019】このようなバンプ5は、異なる条件でのメ
ツキを繰り返すことにより形成される。通常のメツキで
は、少しづつメツキ層を堆積させて形成していく場合、
このようなメツキにより形成される各導電層が分離しな
いように電流値等を制御して堆積させることにより、複
数回のメツキで全体として一つの層になる。バンプ5は
敢えて各導電層が分離するようにメツキ処理すること
で、メツキにより形成された各導電層が物理的には接合
しておらずに面接触のみしており、このため各導電層が
電気的にのみ接続した積層構造となるようになされてい
る。
Such bumps 5 are formed by repeating the plating under different conditions. In normal plating, when depositing and forming the plating layer little by little,
By depositing by controlling the current value and the like so that the conductive layers formed by such plating do not separate, a plurality of plating makes one layer as a whole. The bumps 5 are intentionally plated so that the conductive layers are separated, so that the conductive layers formed by the plating are not physically joined but are only in surface contact. The laminated structure is connected only electrically.

【0020】以上の構成において、半導体素子1はバン
プ5を、導電層が複数積層した積層構造とすると共に導
電層の積層方向と垂直な方向に応力が加わつた場合に当
該応力に応じた方向にへき開する構造とした。半導体素
子1と基板2との膨張係数の違いから熱膨張によつてバ
ンプ5に応力が加えられた場合、バンプ5は変形(図
3)することにより応力によるストレスを逃がしながら
も、各導電層の接触によつてパツド3とランド4との電
気的接続を維持する。また常温に戻つた際、バンプ5は
元の形状に復元する。このようなバンプ5の変形はへき
開によるものであり、バンプ5そのものが破壊するもの
で無いため、繰り返し応力が加えられた場合でも、従来
のような金属疲労による接続信頼性の低下が起こらな
い。このように半導体素子1は温度変化に起因する応力
が繰り返し加えられる場合においても、破断することな
く基板2との電気的接続を維持するバンプ5によつて、
長期間の接続信頼性を向上させることができる。
In the above configuration, the semiconductor element 1 has the bump 5 in a laminated structure in which a plurality of conductive layers are laminated, and when a stress is applied in a direction perpendicular to the laminating direction of the conductive layers, the bump 5 moves in a direction corresponding to the stress. Cleaved structure. When a stress is applied to the bump 5 due to thermal expansion due to a difference in expansion coefficient between the semiconductor element 1 and the substrate 2, the bump 5 is deformed (FIG. 3) to release the stress due to the stress, but to reduce the stress caused by the stress. By this contact, the electrical connection between the pad 3 and the land 4 is maintained. When the temperature returns to room temperature, the bumps 5 return to their original shapes. Such deformation of the bump 5 is due to cleavage, and does not break the bump 5 itself. Therefore, even when repeated stress is applied, the reduction in connection reliability due to metal fatigue does not occur as in the related art. As described above, even when stress caused by a temperature change is repeatedly applied, the semiconductor element 1 is not broken by the bumps 5 that maintain the electrical connection with the substrate 2.
Long-term connection reliability can be improved.

【0021】以上の構成によれば、半導体素子1の突起
電極であるバンプ5を、導電層が複数積層した積層構造
とすると共に導電層の積層方向と垂直な方向に応力が加
わつた場合に応力に応じてへき開する構造としたことに
より、温度変化に起因する応力がバンプ5に繰り返し加
えられる場合においても、バンプ5が破断することなく
基板2との電気的接続を維持することができ、かくする
につき、長期間の接続信頼性を向上させることができ
る。
According to the above configuration, the bumps 5 serving as the protruding electrodes of the semiconductor element 1 have a laminated structure in which a plurality of conductive layers are laminated, and when a stress is applied in a direction perpendicular to the laminating direction of the conductive layers, the stress is increased. , The electrical connection with the substrate 2 can be maintained without breaking the bump 5 even when the stress due to the temperature change is repeatedly applied to the bump 5. Therefore, long-term connection reliability can be improved.

【0022】(2)第2実施例 図2との対応部分に同一符号を付した図4において、バ
ンプ7は従来通り、はんだで形成されており、パツド3
及びランド4と当接する面を溶融させて接合することに
より、パツド3とランド4とを電気的に接続している。
またバンプ7はパツド3及びランド4と当接しない周側
面を樹脂8によつて隙間無く被覆している。
(2) Second Embodiment In FIG. 4 in which the same reference numerals are given to the parts corresponding to those in FIG. 2, the bumps 7 are formed by soldering,
The pad 3 and the land 4 are electrically connected to each other by melting and joining the surface in contact with the land 4.
The bump 7 is covered with the resin 8 on the peripheral side surface that does not contact the pad 3 and the land 4 without any gap.

【0023】バンプ7を被覆する樹脂8は収縮性を有し
た樹脂材でなり、例えばシリコン樹脂等が用いられる。
樹脂8は常温状態でのバンプ7の形状に合わせて被覆さ
れており、バンプ7に応力が加えられて変形した際に追
従して変形すると共に、応力が無くなつた際にはバンプ
7を常温状態時の形状に復元する。このようなバンプ7
は、以下に説明する手法により形成される。すなわち図
5に示すように、予め半導体素子1のパツド3表面に形
成したバンプ7を樹脂溜まり9に浸す。ここで樹脂溜ま
り9には樹脂8が満たされている。バンプ7は樹脂溜ま
り9に浸された後に引き上げられ、外側に付着した樹脂
8を硬化させることにより樹脂8を被覆する。この際、
ランド4と当接する面に被覆されている樹脂8はレーザ
光によつて除去される。バンプ7は、こうして樹脂8が
除去された面がはんだが剥き出しの状態となつているた
め、通常通り、当該面をランド4に当接させて熱を加え
ることにより溶融したはんだによつてランド4と接合す
ることができる。
The resin 8 for covering the bump 7 is made of a resin material having shrinkage, for example, a silicon resin or the like.
The resin 8 is coated so as to conform to the shape of the bump 7 at room temperature. When the resin is deformed by applying stress to the bump 7, the resin is deformed. Restores to the original shape. Such a bump 7
Is formed by a method described below. That is, as shown in FIG. 5, the bumps 7 previously formed on the surface of the pad 3 of the semiconductor element 1 are immersed in the resin reservoir 9. Here, the resin pool 9 is filled with the resin 8. After being immersed in the resin pool 9, the bump 7 is lifted up and covers the resin 8 by curing the resin 8 attached to the outside. On this occasion,
The resin 8 coated on the surface in contact with the land 4 is removed by a laser beam. Since the surface of the bump 7 from which the resin 8 has been removed is in a state in which the solder is exposed, the surface is brought into contact with the land 4 and heat is applied to the land 4 by the molten solder as usual. And can be joined.

【0024】以上の構成において、バンプ7は樹脂8を
周側面に隙間無く被覆したことにより、バンプ7内部の
組織破壊によるパツド3及びランド4間の電気的接続の
破断を防止している。すなわち従来、バンプに温度環境
の変化に起因する応力が加えられた場合、バンプは当該
応力により変形し、組織が破壊されてしまう。こうして
破壊された組織は内部に隙間を生じさせ、このため電気
的接続を破断させることになる。バンプ7は応力が加え
られた際の変形によつて組織が破壊しても、外側に隙間
無く被覆した樹脂8の収縮力により破壊した組織を押さ
えつけ、組織内部に隙間が生じることを防止することが
できる。これによりバンプ7は電気的接続の破断を防止
して、電気的接続の信頼性を長期間、維持することがで
きる。
In the above configuration, the bump 7 is covered with the resin 8 on the peripheral side surface without any gap, thereby preventing the breakage of the electrical connection between the pad 3 and the land 4 due to the destruction of the structure inside the bump 7. That is, conventionally, when a stress due to a change in the temperature environment is applied to the bump, the bump is deformed by the stress and the tissue is destroyed. The tissue thus destroyed creates gaps therein, thereby breaking the electrical connection. Even if the structure is destroyed by deformation when stress is applied, the bumps 7 hold down the broken structure due to the shrinkage force of the resin 8 coated on the outside without gaps, and prevent gaps from being formed inside the tissue. Can be. Accordingly, the bumps 7 prevent the electrical connection from being broken, and the reliability of the electrical connection can be maintained for a long time.

【0025】以上の構成によれば、バンプ7の外側に収
縮性を有した樹脂8を隙間無く被覆したことにより、温
度環境の変化に起因する応力によるバンプ7の変形を許
容すると共に、変形による組織破壊が生じても樹脂8の
収縮力によつて内部に隙間が生じることを防止して、バ
ンプ7の電気的接続の破断を防止することができ、かく
するにつき、長期間の接続信頼性を向上させることがで
きる。
According to the above configuration, since the outside of the bump 7 is covered with the shrinkable resin 8 without any gap, the deformation of the bump 7 due to the stress caused by the change in the temperature environment is allowed and the deformation due to the deformation is allowed. Even if tissue destruction occurs, it is possible to prevent a gap from being formed inside due to the contraction force of the resin 8, thereby preventing breakage of the electrical connection of the bump 7, and thus, long-term connection reliability. Can be improved.

【0026】(3)他の実施例 なお上述の第1実施例においては、鱗片状でなる導電体
の層が複数積層された構造でなるバンプ5を設けた場合
について述べたが、本発明はこれに限らず、導電体でな
る各導電層を形成するために複数の導電材料を用いても
よい。例えば半導体素子側のパツドに当接する層にはC
r(クロム)やTi(チタン)等を用い、また基板側の
ランドに当接する層にはNi(ニツケル)を用いる。一
般にパツドにはアルミが用いられており、またランドに
は銅が用いられているため、このようにそれぞれ当接す
る金属と相性のよい金属を各導電層に用いることによ
り、パツド及びランドとの接合性を向上させることがで
きる。
(3) Other Embodiments In the first embodiment described above, a case was described in which the bumps 5 having a structure in which a plurality of scale-like conductor layers were stacked were provided. The present invention is not limited to this, and a plurality of conductive materials may be used to form each conductive layer made of a conductor. For example, the layer in contact with the pad on the semiconductor element side has C
r (chromium), Ti (titanium), or the like is used, and Ni (nickel) is used for a layer in contact with a land on the substrate side. In general, aluminum is used for the pad and copper is used for the land. Thus, by using a metal that is compatible with the abutting metal for each conductive layer, the connection between the pad and the land can be made. Performance can be improved.

【0027】また上述の第1実施例においては、鱗片状
でなる層を積層した円柱形状の突起電極であるバンプ5
の場合について述べたが、本発明はこれに限らず、例え
ば平板状でなる層を積層した角柱形状としてもよい。す
なわち形状に係わらず、各層が応力を加えられた場合に
へき開する構造であるならば第1実施例と同様の効果を
得ることができる。
In the first embodiment described above, the bumps 5 which are columnar protruding electrodes formed by laminating scale-like layers are used.
However, the present invention is not limited to this, and may be, for example, a prismatic shape in which layers having a flat plate shape are stacked. That is, irrespective of the shape, the same effect as in the first embodiment can be obtained if the structure is cleaved when each layer is stressed.

【0028】さらに上述の第1実施例においては、めつ
きによつて導電層を複数堆積させて形成したバンプ5の
場合について述べたが、本発明はこれに限らず、例えば
蒸着法を用いて積層形成してもよい。この場合でも第1
実施例と同様の効果を得ることができる。
Further, in the first embodiment described above, the case of the bump 5 formed by depositing a plurality of conductive layers by plating has been described. However, the present invention is not limited to this, and the present invention is not limited thereto. It may be formed by lamination. Even in this case, the first
The same effect as that of the embodiment can be obtained.

【0029】また上述の第1実施例においては、積層さ
れた各導電層が応力を加えられた際にへき開する構造で
なるバンプ5の場合について述べたが、本発明はこれに
限らず、このようなへき開する構造でなるバンプの周側
面に収縮性を有した樹脂を被覆するようにしてもよい。
これにより温度環境の変化に起因する応力によつて変形
したバンプが、温度環境が常温に復帰して変形前の形状
に復元する際に、バンプを被覆する樹脂の収縮力によつ
て容易に元の形状に復元することができる。
In the first embodiment described above, the case of the bump 5 having a structure in which each of the stacked conductive layers is cleaved when a stress is applied thereto has been described. However, the present invention is not limited to this. The peripheral side surface of the bump having such a cleavage structure may be covered with a resin having shrinkage.
As a result, when the bump deformed due to the stress caused by the change in the temperature environment returns to the normal temperature and restores the shape before the deformation, the bump easily deforms due to the shrinkage of the resin covering the bump. Shape can be restored.

【0030】また上述の第2実施例においては、収縮性
を有した樹脂としてシリコン樹脂を用い、バンプ5を被
覆した場合について述べたが、本発明はこれに限らず、
シリコン樹脂以外の樹脂を用いてもよい。すなわち収縮
性を有した樹脂であるならば第2実施例と同様の効果を
得ることができる。
Further, in the above-described second embodiment, the case where the bump 5 is covered by using a silicone resin as the shrinkable resin is described. However, the present invention is not limited to this.
Resins other than silicon resin may be used. That is, if the resin has shrinkage, the same effect as in the second embodiment can be obtained.

【0031】さらに上述の第2実施例においては、収縮
性を有した樹脂としてシリコン樹脂を用い、バンプ5を
被覆した場合について述べたが、本発明はこれに限ら
ず、例えば半導体素子と基板との隙間に封入する封止樹
脂に収縮性を有した樹脂を用いるようにしてもよい。こ
の場合、封止樹脂と別にバンプを被覆する樹脂を用いる
必要が無く、簡易な構成で第2実施例と同様の効果を得
ることができる。
Further, in the second embodiment described above, a case was described in which the bump 5 was covered by using a silicone resin as the shrinkable resin. However, the present invention is not limited to this. The shrinkable resin may be used as the sealing resin sealed in the gap. In this case, there is no need to use a resin for covering the bumps separately from the sealing resin, and the same effect as in the second embodiment can be obtained with a simple configuration.

【0032】[0032]

【発明の効果】上述のように本発明によれば、半導体装
置の一面側に設けられた第1の電極上にそれぞれ、導電
材からなる導電層を複数積層して突起電極を形成するよ
うにしたことにより、突起電極に温度環境の変化に起因
する応力が加えられた場合、突起電極の各導電層がへき
開して変形することにより、破断すること無く電気的接
続を維持することができ、かくするにつき、繰り返しの
温度変化に係わらず、配線基板との電気的接続の信頼性
を向上し得る。
As described above, according to the present invention, a plurality of conductive layers made of a conductive material are laminated on a first electrode provided on one surface side of a semiconductor device to form a projecting electrode. By doing so, when a stress due to a change in the temperature environment is applied to the bump electrode, each conductive layer of the bump electrode is cleaved and deformed, so that electrical connection can be maintained without breaking, Thus, the reliability of the electrical connection with the wiring board can be improved irrespective of the repeated temperature change.

【0033】また本発明によれば、第1の電極上にそれ
ぞれ形成された各突起電極を収縮性を有した樹脂材でな
る被覆部によつて被覆するようにしたことにより、突起
電極に温度環境の変化に起因する応力が加えられた場
合、被覆部の収縮力によつて突起電極の組織に破断によ
る隙間が生じることを防止して、電気的接続を維持する
ことができ、かくするにつき、繰り返しの温度変化に係
わらず、配線基板との電気的接続の信頼性を向上し得
る。
Further, according to the present invention, each of the projecting electrodes formed on the first electrode is covered with the covering portion made of a resin material having shrinkage, so that the temperature of the projecting electrode is reduced. When a stress due to an environmental change is applied, it is possible to prevent a gap from being formed in the structure of the protruding electrode due to the contraction force of the covering portion, thereby maintaining the electrical connection. In addition, the reliability of the electrical connection with the wiring board can be improved regardless of the repeated temperature change.

【図面の簡単な説明】[Brief description of the drawings]

【図1】半導体素子の基板上への実装状態を示す側面か
らの断面図である。
FIG. 1 is a side sectional view showing a state in which a semiconductor element is mounted on a substrate.

【図2】第1実施例によるバンプの構造を示す拡大図で
ある。
FIG. 2 is an enlarged view showing a structure of a bump according to the first embodiment.

【図3】高温状態での半導体素子及び基板の接続状態の
説明に供する拡大図である。
FIG. 3 is an enlarged view for explaining a connection state between a semiconductor element and a substrate in a high temperature state.

【図4】第2実施例によるバンプの構造を示す拡大図で
ある。
FIG. 4 is an enlarged view showing a structure of a bump according to a second embodiment.

【図5】第2実施例によるバンプの説明に供する略線図
である。
FIG. 5 is a schematic diagram for explaining a bump according to a second embodiment.

【符号の説明】[Explanation of symbols]

1……半導体素子、2……基板、3……パツド、4……
ランド、5、7……バンプ、6……封止樹脂、8……樹
脂、9……樹脂溜まり。
1 ... semiconductor element, 2 ... substrate, 3 ... pad, 4 ...
Land 5, 7, bump, 6 sealing resin, 8 resin, 9 resin pool.

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】一面側に複数の第1の電極が設けられ、当
該各第1の電極を基板上の対応する各第2の電極と接合
するようにして上記基板上に実装される半導体装置にお
いて、 導電材からなる導電層を複数積層することにより形成さ
れ、各上記第1の電極上にそれぞれ設けられた突起電極
を具えることを特徴とする半導体装置。
A semiconductor device mounted on the substrate such that a plurality of first electrodes are provided on one surface side and each of the first electrodes is joined to a corresponding one of the second electrodes on the substrate; 2. The semiconductor device according to claim 1, further comprising: a plurality of conductive layers made of a conductive material, each of which is formed by laminating a plurality of conductive layers, and each of the first electrodes includes a protruding electrode.
【請求項2】上記突起電極は、 上記第1の電極と接合される上記導電層が当該第1の電
極と接合性の良い導電材を用いて形成されると共に、上
記第2の電極と接合される上記導電層が当該第2の電極
と接合性の良い導電材を用いて形成されることを特徴と
する請求項1に記載の半導体装置。
2. The projection electrode according to claim 1, wherein the conductive layer bonded to the first electrode is formed using a conductive material having a good bonding property with the first electrode, and the conductive layer is bonded to the second electrode. 2. The semiconductor device according to claim 1, wherein the conductive layer to be formed is formed using a conductive material having a good bonding property with the second electrode.
【請求項3】一面側に複数の第1の電極が設けられ、当
該各第1の電極を基板上の対応する各第2の電極と接合
するようにして上記基板上に実装される半導体装置にお
いて、 各上記第1の電極上にそれぞれ形成された突起電極と、 各上記突起電極を被覆する収縮性を有した樹脂材からな
る被覆部とを具えることを特徴とする半導体装置。
3. A semiconductor device having a plurality of first electrodes provided on one surface side and mounted on the substrate such that each of the first electrodes is joined to each corresponding second electrode on the substrate. 3. The semiconductor device according to claim 1, further comprising: a protruding electrode formed on each of the first electrodes; and a covering portion made of a contractible resin material for covering each of the protruding electrodes.
【請求項4】一面側に複数の第1の電極が設けられ、当
該各第1の電極を基板上の対応する各第2の電極と接合
するようにして上記基板上に実装される半導体装置の実
装方法において、 各上記第1の電極上に、導電材からなる導電層を複数積
層するようにして当該積層された複数の上記導電層から
なる突起電極を形成する第1のステツプと、 上記突起電極を介して、上記第1の電極を上記第2の電
極と接合する第2のステツプとを具えることを特徴とす
る半導体装置の実装方法。
4. A semiconductor device having a plurality of first electrodes provided on one surface side and mounted on the substrate such that each of the first electrodes is joined to each of the corresponding second electrodes on the substrate. In the mounting method of the first aspect, a first step of forming a plurality of conductive layers made of a conductive material on each of the first electrodes to form a bump electrode made up of the plurality of stacked conductive layers, A method of mounting a semiconductor device, comprising: a second step of joining the first electrode to the second electrode via a protruding electrode.
【請求項5】上記第1のステツプでは、 上記導電材をめつきにより順次堆積させることにより各
上記導電層を形成することを特徴とする請求項4に記載
の半導体装置の実装方法。
5. The method according to claim 4, wherein in the first step, the conductive layers are formed by sequentially depositing the conductive material by plating.
【請求項6】上記第1のステツプでは、 上記突起電極の上記第1の電極と接合される上記導電層
を当該第1の電極と接合性の良い導電材を用いて形成す
ると共に、上記第2の電極と接合される上記導電層を当
該第2の電極と接合性の良い導電材を用いて形成するこ
とを特徴とする請求項4に記載の半導体装置の実装方
法。
6. In the first step, the conductive layer to be bonded to the first electrode of the protruding electrode is formed using a conductive material having a good bonding property with the first electrode. 5. The method according to claim 4, wherein the conductive layer bonded to the second electrode is formed using a conductive material having good bonding properties with the second electrode.
JP22309796A 1996-08-05 1996-08-05 Semiconductor device and method for forming bump electrode Expired - Fee Related JP3410298B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP22309796A JP3410298B2 (en) 1996-08-05 1996-08-05 Semiconductor device and method for forming bump electrode

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP22309796A JP3410298B2 (en) 1996-08-05 1996-08-05 Semiconductor device and method for forming bump electrode

Publications (2)

Publication Number Publication Date
JPH1050767A true JPH1050767A (en) 1998-02-20
JP3410298B2 JP3410298B2 (en) 2003-05-26

Family

ID=16792790

Family Applications (1)

Application Number Title Priority Date Filing Date
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Country Status (1)

Country Link
JP (1) JP3410298B2 (en)

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