JPH1041748A - Clock generating circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a clock generating circuit in which a high speed operation can be attained at low costs. SOLUTION: When a frequency signal generated by a signal inputted from the outside is inputted to a data clock circuit 60, the amplitude of the inputted frequency signal is limited, and a part which is unnecessary for the generation of a clock pulse in the frequency signal is removed in the data clock circuit 60. Thus, in a clock generating circuit, the necessary number of bits can be reduced, manufacturing costs can be reduced, and a high speed operation can be attained at the same costs.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock generation circuit, and more particularly to a DDS (Direct Digital Synthesizer).
And a clock generation circuit using the same.

[0002]

2. Description of the Related Art FIG. 4 is a block diagram showing a configuration example of a conventional clock generation circuit.

In this conventional example, as shown in FIG. 4, a system clock and a phase addition data are inputted from the outside, a phase adder 10 for adding the inputted phase addition data to the output data, and outputting the added data. The clock and the data output from the phase adder 10 are input, and the phase adder 1
A sine wave conversion circuit 20 that converts data output from 0 into a sine wave and outputs the sine wave;
The data output from the conversion circuit 20 is input, and sin
A D / A converter 30 that converts data output from the wave conversion circuit 20 into an analog signal and outputs the analog signal, and a D / A converter 3
A low-pass filter 40 that passes and outputs only the low-frequency components of the analog signal output from 0 and a signal that has passed through the low-pass filter 40 is compared with a certain level,
A comparator 5 that generates and outputs a clock pulse
0. Note that the phase adder 10 and si
DDS (Direct Digital Synth) for generating a frequency signal from an externally input signal from the n-wave conversion circuit 20
esizer) is formed.

In the clock generation circuit configured as described above, of the signals that have passed through the low-pass filter 40, the signal at the zero-cross point, which is a cross point with the threshold value in the comparator 50, is used. Generates and outputs a clock pulse.

FIGS. 5A and 5B are waveform diagrams of the circuit shown in FIG. 4, in which FIG. 5A shows a signal passed through the low-pass filter 40, and FIG. 5B shows a clock pulse output from the comparator 50. It is.

[0006]

However, in the above-described conventional clock generation circuit, when the DDS is operated at a high speed, a high-speed DDS is required.
A / A converter must be used, but in a D / A converter, the higher the speed, the smaller the number of bits, and there is a possibility that the number of bits for the scale required for conversion may not be satisfied. .

Further, if the speed is the same, a clock circuit can be formed at low cost by using a bit having a small number of bits.

The present invention has been made in view of the above-mentioned problems of the conventional technology, and has as its object to provide an inexpensive and high-speed clock generating circuit. .

[0009]

According to the present invention, there is provided a clock generating circuit for generating a frequency signal from an externally input signal and generating a clock pulse based on the frequency signal. Limiting means for limiting the amplitude of the frequency signal, a D / A converter for converting the frequency signal whose amplitude is limited by the limiting means into an analog signal and outputting the analog signal, and a signal output from the D / A converter. It has a low-pass filter that passes only low-frequency components of a signal, and a comparator that compares the signal that has passed through the low-pass filter with a certain level, thereby generating and outputting a clock pulse.

Further, the frequency signal is a sine wave.

(Operation) In the present invention configured as described above, when a frequency signal generated by a signal input from the outside is input to the limiting means, the amplitude of the input frequency signal is controlled by the limiting means. , And a portion of the frequency signal that is unnecessary for generating the clock pulse is removed.

For this reason, the number of bits required in the clock generation circuit is reduced, and the manufacturing cost is reduced.
In addition, high-speed operation is possible with the same cost.

[0013]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a clock generation circuit according to the present invention.

In this embodiment, as shown in FIG. 1, a system clock and a phase addition data are inputted from the outside, a phase adder 10 for adding the inputted phase addition data to the output data and outputting the same, and a system clock. And the data output from the phase adder 10
S to convert the data output from to a sin wave and output
Limiting means for receiving an in-wave conversion circuit 20, a system clock and data output from the sine conversion circuit 20, limiting the amplitude of the data output from the sine wave conversion circuit 20, and outputting the data having the limited amplitude. And a D / A for converting data output from the data clip circuit 60 into an analog signal and outputting the analog signal
A converter 30, a low-pass filter 40 that passes only the low-frequency components of the analog signal output from the D / A converter 30 and outputs the signal, and compares the signal that has passed through the low-pass filter 40 with a certain level. And a comparator 50 for generating and outputting a clock pulse. In addition, a DDS (Direct Digital Synthesizer) that generates a frequency signal from a signal input from the outside is formed from the phase adder 10 and the sine wave conversion circuit 20.

In the clock generation circuit configured as described above, when the data converted into the sine wave by the sine wave conversion circuit 20 is input to the data clip circuit 60, the input data is Is limited, and data with the limited amplitude is output.

Thereafter, similarly to the circuit shown in FIG. 4, the signal at the zero-cross point, which is a cross point with the threshold value in the comparator 50, of the signal passed through the low-pass filter 40 is used. A clock pulse is generated and output.

FIGS. 2A and 2B are waveform diagrams of the circuit shown in FIG. 1. FIG. 2A shows a signal passed through the low-pass filter 40, and FIG. 2B shows a clock pulse output from the comparator 50. It is.

As shown in FIG. 2, the low-pass filter 40
The amplitude of the sine wave output from the sine wave conversion circuit 20 is limited in the data that has passed through, and the unnecessary portion of the sine wave in the comparator 50 is removed.

As a result, the number of bits required for the D / A converter 30 can be reduced, and an inexpensive and high-speed clock generation circuit can be realized.

FIG. 3 is a circuit block diagram showing one configuration example of the data clip circuit 60 shown in FIG.

FIG. 3 shows a data clipping circuit according to this embodiment.
, An upper limit data comparator 61 for controlling the upper limit of the input data, a lower limit data comparator 62 for controlling the lower limit of the input data,
3 to 66.

In the data clipping circuit configured as described above, when the input DDS data exceeds a predetermined upper limit, the upper limit data comparator 61
Output an "H" signal, whereby the upper limit full scale data is output from the data clip circuit 60 and
If the DS data falls below a predetermined lower limit,
The “H” signal is output from the lower limit data comparator 62, whereby the lower limit full scale data is output from the data clip circuit 60.

On the other hand, if the input DDS data is within a predetermined range of upper and lower limits, the DDS data is output from the data clip circuit 60 as it is.

[0025]

As described above, in the present invention,
Since the limiting means for limiting the amplitude of the frequency signal generated by the signal input from the outside is provided, a part of the frequency signal that is not necessary for generating the clock pulse is removed.

As a result, the number of bits required in the clock generation circuit is reduced, the manufacturing cost can be reduced, and a high-speed operation can be performed at the same cost.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a clock generation circuit of the present invention.

FIG. 2 is a waveform chart in the circuit shown in FIG. 1;
(A) is a diagram showing a signal passed through a low-pass filter,
(B) is a diagram showing a clock pulse output from the comparator.

FIG. 3 is a circuit block diagram illustrating a configuration example of a data clip circuit illustrated in FIG. 1;

FIG. 4 is a block diagram illustrating a configuration example of a conventional clock generation circuit.

FIG. 5 is a waveform chart in the circuit shown in FIG. 4;
(A) is a diagram showing a signal passed through a low-pass filter,
(B) is a diagram showing a clock pulse output from the comparator.

[Explanation of symbols]

 Reference Signs List 10 phase adder 20 sine wave conversion circuit 30 D / A converter 40 low-pass filter 50 comparator 60 data clipping circuit 61 upper limit data comparator 62 lower limit data comparator 63 to 66 logic gate

Claims (2)

[Claims] 1. A clock generating circuit for generating a frequency signal based on a signal input from the outside and generating a clock pulse based on the frequency signal, comprising: limiting means for limiting the amplitude of the frequency signal; A D / A converter that converts a frequency signal whose amplitude is limited by the means into an analog signal and outputs the analog signal; a low-pass filter that passes only a low-frequency component of the signal output from the D / A converter; A clock generation circuit comprising: a comparator that compares a signal that has passed through a low-pass filter with a predetermined level, thereby generating and outputting a clock pulse. 2. The clock generation circuit according to claim 1, wherein the frequency signal is a sine wave.