JPS628080Y2 - - Google Patents

Description

[Detailed Description of the Invention] This invention relates to a digital data slope conversion circuit. Here, the digital data slope conversion circuit is a circuit that converts rapidly changing input digital data into slowly changing digital data.

For example, in digital electronic musical instruments, musical sound waveforms are naturally expressed as digital data. Therefore, in order to generate a musical sound waveform expressed by this digital data as a musical tone, this digital data is usually converted into an appropriate analog signal using a digital-to-analog converter, etc., and then the musical sound waveform converted into this analog signal is generated. is input into a sound system consisting of an amplifier, speakers, etc.

In such digital electronic musical instruments, when the digital data rapidly increases or decreases, a large amount of aliasing noise is contained in the digital data, so the musical sounds emitted from the sound system become noisy. It has the disadvantage that it contains a large amount of silica and produces an unpleasant sound.

The above-mentioned aliasing noise refers to the frequency fs/2 of the frequency components included in the digital data relative to the data rate fs (also called the sampling frequency, which corresponds to the number of times the digital data changes per second). The above frequency components are aliased around the frequency fs/2 as the center of symmetry, and appear as frequency components lower than the frequency fs/2. In order to remove the aliasing noise contained in such digital data, conventional techniques such as special 1971-
It has been proposed to use interpolation techniques such as those disclosed in JP-A-9348, JP-A-51-14015, and JP-A-51-14016.
However, in electronic musical instruments that use conventional interpolation, the digital data (music waveform) often changes rapidly for high-pitched keys, contains a large amount of aliasing noise, and In keys, there are not many sudden changes in digital data, so there is not much aliasing noise, so it is necessary to vary the degree of interpolation from keys with low pitches to keys with high pitches. Therefore,
It is inevitable that the configuration for removing aliasing noise will be complicated and large-scale. This was a contributing factor to the rise in prices of devices (such as electronic musical instruments).

This invention was devised to eliminate such conventional drawbacks, and an object thereof is to provide a digital data slope conversion circuit of a simple configuration that eliminates the above-mentioned aliasing noise.

The digital data slope conversion circuit of this invention includes an up-down counter that counts predetermined clock pulses and outputs a count value with the same number of bits as the input digital data, and a combination of the input digital data value and the up-down counter. It is composed of a comparator that compares the magnitude relationship with the output count value. The digital data slope conversion circuit of this invention stops or stops the counting operation of the counter according to the output of the comparator.
The count-up operation and count-down operation are controlled respectively, so that the count value of the up-down counter interpolates the input digital data in response to a sudden change in the input digital data, and the count value of the up-down counter interpolates the input digital data. It is configured to output numerical values as new converted digital data.

The present invention will be described in more detail below with reference to embodiments shown in the accompanying drawings.

In the following description, a case will be explained in which the digital data slope conversion circuit according to the present invention is used for musical waveform processing of an electronic musical instrument, and it is assumed that the input digital data represents a musical waveform.

As shown in Figure 1, 10-bit digital data (hereinafter referred to as waveform data MW) representing a musical sound waveform output from a musical sound waveform forming circuit of an electronic musical instrument (not shown)
10-bit digital data (corresponding to the count value of counter 2) is input to the first input terminal A of the comparator 1, and the 10-bit digital data output from the up-down counter 2 is input to the second input terminal B. (hereinafter referred to as converted waveform data MW') is input. Comparator 1 compares the digital data values of waveform data MW input to input terminal A and converted waveform data MW' input to input terminal B,
When MW>MW', a logic value "1" is output from the first input terminal 01, and when MW<MW', the first
Outputs logical value “0” from output terminal 01 of MW
=MW', the logic value "1" is output from the second output terminal 02. A first output terminal 01 of the comparator 1 is connected to an up-down designation input terminal U/D of an up-down counter 2, and a second output terminal 02 is connected to a count stop command input terminal CS. The oscillator 3 is connected to the count input terminal Ci of the up-down counter 52.
The clock pulse φ outputted by is inputted.
The up-down counter 2 stops its counting operation when a logical value "1" is input to the count stop command input terminal CS. In addition, if the logical value "1" is input to the up-down designation input terminal U/D while the logical value "0" is input to the count stop command input terminal CS, the up-down counter 2 is in the up mode. , and sequentially counts up the clock pulses φ input to the count input terminal Ci. In addition, if a logical value "0" is input to the count stop command input terminal CS and a logical value "0" is input to the up-down designation input terminal U/D, the up-down counter 2 is in the down mode. The clock pulse φ set to 0 and input to the count input terminal Ci is counted down sequentially. This up-down counter 2 converts the counted value into 10-bit converted waveform data.
The converted waveform data MW' is output as MW', and as described above, this converted waveform data MW' is input to the input terminal B of the comparator 1. It is assumed that the oscillation frequency of the clock pulse φ output from the oscillator 3 is sufficiently higher than the frequency of change of the waveform data MW.

Next, regarding the operation of this digital data slope conversion circuit having the above configuration, we will discuss (a) the case where the waveform data MW changes significantly in a step-like manner, and (b)
The explanation will be divided into two cases in which the waveform data MW changes in a small stepwise manner.

(b) When the waveform data MW changes significantly in a step-like manner, that is, as shown in Figure 2A, the waveform data MW
If the value increases significantly in a stepwise manner at time t ₁ , MW >MW' at time t ₁ , so a logical value "1" is output from the first output terminal 01 of the comparator 1, and the second A logical value “0” is output from the output terminal 02. Therefore, the count stop command input terminal CS of up-down counter 2
Since the logical value "0" is input to the up-down designation input terminal U/D and the logical value "1" is input to the up-down designation input terminal U/D, the up-down counter 2 is set to the up mode. Therefore, up-down counter 2
sequentially counts up the clock pulses φ input to its count input terminal Ci, and increases the count value sequentially. Up-down counter 2 converts this count value into 10-bit converted waveform data.
MW', which is input to the second input terminal B of the comparator 1 as described above. This converted waveform data MW' is also stored in the up-down counter 2.
With the count-up operation, the value gradually increases as shown in FIG. 2A, and eventually reaches a value equal to the value of the waveform data MW at time _t2 .
At this time, the comparator 1 outputs the logical value "1" from the output terminal 02, and the up-down counter 2 outputs this logical value "1" from the count stop command input terminal.
Upon receiving CS, the counting operation is temporarily stopped.

As shown in Figure 2B, the waveform data MW is time
If there is a significant stepwise decrease at t' ₁ , then at this time t' ₁ the comparator 1 outputs a logic value "0" from its output terminals 01 and 02.
As a result, the logical value "0" is input to both the up-down designation input terminal U/D and the count stop command input terminal CS of the up-down counter 2, so that the up-down counter 2 is set to the down mode. Therefore, the up-down counter 2 sequentially counts down the clock pulses φ input to the count input terminal Ci, and sequentially decreases the count value. This count value is inputted to the input terminal B of the comparator 1 as converted waveform data MW', and becomes equal to the value of the waveform data MW at time t'2 shown in FIG. _2B . At this time, the comparator 1 outputs the logical value "1" from the output terminal 02, and the up-down counter 2 receives this logical value "1" at the count stop command input terminal CS and temporarily stops the counting operation.

As is clear from the above explanation, when the digital data slope conversion circuit shown in Fig. 1 is used, the rapidly changing waveform data MW is converted into the slowly changing converted waveform data MW', which causes aliasing noise. It is possible to obtain converted waveform data MW' with less. In particular, when a high pitch key is pressed, the waveform data MW generated inside the electronic musical instrument changes very rapidly, so this digital data slope conversion circuit works particularly effectively to reduce aliasing noise. It has the effect of significantly reducing

(b) When the waveform data MW changes slightly in steps As shown in Figure 3A, the waveform data MW changes over time.
If there is a small stepwise increase at t ₁ , MW >MW' at time t ₁ . Therefore,
As in case (a) above, the up-down counter 2 is set to the up mode in response to the output of the comparator 1, and sequentially counts up the clock pulse φ output from the oscillator 3. The up-down counter 2 outputs its count value as 10-bit converted waveform data MW', which is input to the second input terminal B of the comparator 1 as described above. When the converted waveform data MW' becomes equal to the waveform data MW at time _t2 shown in FIG. 3A, the comparator 1 outputs a logic value "1" from the output terminal 02.
is output, and the up-down counter 2 temporarily stops counting. Here, the time from time t ₁ to t ₂ is very short because the frequency of the clock pulse φ output from the oscillator 3 is sufficiently high.

In addition, as shown in Figure 3B, the waveform data MW
If the value decreases slightly in a stepwise manner at time t' ₁ , then MW<MW' at time t' ₁ . Therefore, as in case (a) above, comparator 1
The up-down counter 2 is set to the down mode in response to the output of the oscillator 3, and sequentially counts down the clock pulse φ output from the oscillator 3. The up-down counter 2 outputs the counted value as the 10-bit converted waveform data MW' as described above, which is input to the second input terminal B of the comparator 1. As shown in FIG. 3B, when the converted waveform data MW becomes equal to the waveform data MW at time t' ₂ , the comparator 1 outputs a logic value "1" from the output terminal 02, and the up-down counter 2
pauses the counting operation. Here, time t′ ₁
The time from t' ₂ to t' 2 is very short because the frequency of the clock pulse φ output from the oscillator 3 is sufficiently high.

As is clear from the above explanation, even when the waveform data MW changes in small steps, the converted waveform data MW' can follow the changes in the waveform data MW in a short time, and the converted waveform data
The change in MW' is slower than the change in the waveform data MW.

In addition, when the waveform data MW and the converted waveform data MW' (count value) outputted from the up-down counter 2 are the same value (MW=MW'), a logical value "1'' is output and is input to the count stop command input terminal CS of the up-down counter 2, so the up-down counter 2 stops its counting operation until the waveform data MW changes next time. Therefore, in this case, the waveform data MW and the converted waveform data MW' are held at the same value, and the contents of the waveform data MW are not impaired.

In the above explanation, the digital data slope conversion circuit according to this invention is used for processing musical waveform data of an electronic musical instrument. However, this invention is not limited to this, and can be used to process other waveform data ( For example, it can be used to process envelope waveform data, control waveform data, etc.), and can also be used to process waveform data other than electronic musical instruments. The point is that it can be used in all cases where it is desired to convert only the rapid changes in digital data into smooth changes without damaging the content of the data.

As is clear from the above description, according to this invention, rapidly changing input digital data is converted into slowly changing digital data, thereby making it possible to effectively remove aliasing noise. In addition, by using the digital data slope conversion circuit of this invention in an electronic musical instrument, it is possible to generate clear musical tones, and especially when generating musical tones with high pitches, changes in the musical waveform can be achieved. Since the aliasing noise occurs suddenly, this idea works effectively and has the effect of significantly reducing the aliasing noise.

[Brief explanation of the drawing]

Figure 1 is a block diagram showing an embodiment of this invention.
FIGS. 2A and 2B, 3A and 3B, and FIG. 1 are waveform charts for explaining the operation of the embodiment shown in FIG. 1, respectively. 1...Comparator, 2...Up-down counter,
3... Oscillator.

Claims (1)

[Utility Model Claims] [1] An up-down counter that counts clock pulses having a higher frequency than the change frequency of input digital data and outputs a count value having the same number of bits as the input digital data, and a comparator that compares the value of the input digital data with the count value output by the up-down counter; and based on the comparison result output by the comparator,
A digital data slope conversion circuit which controls the stop of the count operation and the count up and count down operations of the up/down counter so that the count value of the up/down counter interpolates the change in the input digital data and outputs this count value as new digital data. [2] A digital data slope conversion circuit as set forth in claim [1] for utility model registration, which causes the up/down counter to count up when the comparison result of the comparator is (the input digital data value)>(the count value output by the up/down counter), causes the up/down counter to stop counting when (the input digital data value)=(the count value output by the up/down counter), and causes the up/down counter to count down when (the input digital data value)<(the count value output by the up/down counter).