KR950007152Y1 - Variable otave address generating apparatus of electronic musical instrument - Google Patents

Abstract

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Description

Variable Octave Address Generator of Electronic Instruments

1 is a block diagram showing a sound generator of a general electronic musical instrument.

2 is a block diagram of an address generator of a conventional electronic musical instrument.

3a, b, and c are timing charts of the control signal generator provided in the conventional address generator.

4 is a PCM waveform diagram sampled according to the pitch of a conventional address generator.

5 is a block diagram of a variable octave address generator of the present invention.

Figure 6 is a PCM waveform diagram sampled according to the pitch of the variable octave address generator of the present invention.

* Explanation of symbols for main parts of the drawings

7: control signal generator 8: RAM

10: decoder 11: adder

The present invention relates to an address generator that can generate sounds of multiple octaves by varying the interval of reading of one octave PCM sample data in an electronic instrument of pulse code modulation (PCM) method, and the size of the PCM data memory. It is suitable to collapse.

As shown in FIG. 1, a sound generator of a general electronic musical instrument includes a frequency generator 1 for generating a frequency for reading and processing PCM data and a frequency clock FCLK output from the frequency generator 1. The PCM data output from the frequency generating section 1 by the address generator 2 generating the access address ADDR of the PCM data memory section 3 and the PCM data output from the PCM data memory section 3. A data processor 4 for processing an error signal output from the frequency generator 1, a data output unit 5 for outputting an error processed signal from the data processor 4, and a data output unit 5 It consists of a D / A converter (6) for converting the output signal from the analog signal to the output.

As shown in FIG. 1, the general electronic instrument configured as described above, when the frequency clock is output from the frequency generator 1 by the PCM data, the address generator 2 sets the address ADDR by 1 by the frequency clock. Incrementally, the access address is supplied to the PCM data memory section 3.

In this way, if the data processing unit 4 reads the PCM data DATA output from the PCM data memory unit 3 and processes the error signal in accordance with the clock output from the frequency generating unit 1, the data output unit 5 generates an error. The processed signal is converted into an analog signal by the D / A converter 6 to output a sound signal.

In the general electronic musical instrument configured as described above, the conventional address generator 2 is a control signal generator for controlling and outputting a read / write signal by a frequency clock output from the frequency generator 1 as shown in FIG. 7), a RAM 8 for outputting or storing address data according to the control output read / write signal READ / WRITE, and the RAM 8 when the control signal generator 7 outputs a read signal. And an adder 9 which increases the current address by one and outputs the access address to the PCM data memory section 3.

Referring to FIGS. 2 and 3, the operation of the address generator 2 will be described. When the frequency clock FCLK is output from the frequency generator 1 by the PCM data as shown in FIG. The control signal generator 7 outputs read / write control signals READ / WRITE by the frequency clock.

At this time, when the read signal READ is output from the control signal generator 7 as shown in FIG. 3B, the current address stored in the RAM 8 is read, and the address ADDR increased by 1 through the adder 9 is read. When the write signal WRITE is output from the control signal generator 7 as shown in FIG. 3C, the RAM 8 receives an address incremented by one from the adder 9, as shown in FIG. By storing, the PCM data are sequentially accessed by the frequency clock output from the sound generator 1.

The accessed PCM data is input to the data processor 4 to process an error signal, and then a sound signal is output by converting the signal output from the data output unit 5 to an analog signal through the D / A converter 6. will be. However, in the conventional electronic instrument address generator, the frequency clock output from the frequency generator 1 is about 30-60 KHz, which is only variable by about one octave.

That is, as shown in FIG. 4, if the frequency clock of the "hour" sound of the octave 1 is about 63.2 KHz, the frequency clock of the "hour" sound of the octave 2 should be about 63.2 x 2 = 126.4 KHz. Because it is difficult to implement, PCM sample data is usually created for every octave.

Therefore, when the sample data of octave 2, which is twice the sample frequency of octave 1, is made and the sound of octave 2 is generated, the sample data of octave 2 is accessed and the samples of octave 2, 3, 4 ... are needed. There was a problem that the memory capacity of the unit 3 became large.

The present invention aims to reduce the size of the memory portion of the PCM data by varying the interval of reading of the PCM sample data of the one octave in order to solve such a conventional problem, so that the size of the PCM data memory portion, Referring to the configuration and effect of the present invention by the drawings as follows.

First, as shown in FIG. 5, the variable octave generator of the inventive electronic musical instrument includes a control signal generator 7 for outputting a control signal for outputting a read / write control signal by a frequency clock output from the frequency generator. ), A RAM 8 for outputting or storing address data according to the output read / write signal, a decoder unit 10 for selecting an address value to be increased by the input octave selection signal, and the decoder unit ( The adder 11 adds the address increase signal selected in step 10) and the address stored in the RAM 8 to sequentially increase and output the access address of the PCM sound data.

Referring to Fig. 6, the effect of the present invention configured as described above will be described. When the frequency clock FCLK is supplied from the frequency generator, the control signal generator 7 reads the read / write control signal READ by the frequency clock. / WRITE).

At this time, when the read signal READ is output from the control signal generator 7, the read address of the PCM sound data is output from the RAM 8. At this time, the adder 11 selects the address increase value selected from the decoder 10 and the RAM ( The address value supplied in step 8) is added to sequentially output the address ADDR which is increased.

That is, when the input octave selection signal is "ψ", the output terminal Yψ of the decoder unit 10 becomes "1" and the address increase value becomes "1", so it is input through the input terminal A of the adder 11. Since the RAM 8 output value is added to the value 1, the address ADDR increases by "1", and when the octave selection signal is "1", "1" is output from the output terminal Y1 of the decoder unit 10. At this time, the address increase value becomes "2", and this value is input through the input terminal A of the adder 11, so that the added output address ADDR increases by "2".

In addition, when the input octave selection signal is "2", "1" is output from the output terminal Y2 of the decoder unit 10, so that the address increase value is "4", and this value changes the input terminal A of the adder 11. The address ADDR is incremented by "4" because it is input through the.

Thus, in this case, the octave is increased by two octaves, increasing the address of the PCM data by four times as shown in FIG. 6, and the multiple octaves are transmitted through the data output by one PCM sample data stored in the PCM data memory. It is output as an analog signal by the A converter.

As described above, the size of the PCM data memory can be reduced by varying the reading interval of the one-octave PCM sample data so that the sound of several octaves can be generated, thereby making it suitable for digital IC.

Claims (1)

A control signal generator 7 for outputting a read / write control signal by the frequency clock output from the frequency generator, a RAM 8 for outputting or storing address data according to the output read / write signal, and The decoder 10 selects the address value to be increased by the octave selection signal, and the address increase signal selected by the decoder 10 and the address stored in the RAM 8 are sequentially increased to access PCM sound data. A variable octave address generator for electronic musical instruments, characterized by comprising an adder (11) for outputting an address.