JPH0567976A - D/a converter - Google Patents

Abstract

PURPOSE:To improve the S/N and to reduce the oversampling ratio in the D/A converter which utilizes the oversampling technology and the noise shaping technology. CONSTITUTION:A level detection circuit 22 detects that a digital input value is less than a prescribed level and a shift control circuit 26 and a shift circuit 20 increase the digital value by a prescribed value in response to the detection output of the level detection circuit 22. Moreover, an analog output extracted from a low pass filter 18 is attenuated corresponding to a prescribed quantity at an attenuation control circuit 32 and an attenuator 30 in response to the detection output of the level detection circuit 22. The attenuation control is implemented as to a digital signal at an output side of a noise shaper 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a DA converter using an oversampling technique and a noise shaping (delta sigma modulation) technique, and more particularly, it detects that a digital input value is below a predetermined level and outputs the digital input value. The S / N ratio is improved and the oversampling ratio can be reduced by increasing the analog output by a predetermined amount and decreasing the analog output corresponding to the predetermined amount.

[0002]

2. Description of the Related Art Conventionally, as a DA converter utilizing the oversampling technique and the noise shaping technique, the one exemplified in FIG. 4 has been proposed.

In FIG. 4, 10 is a digital filter for oversampling a multi-bit digital input DI, and 12 is a multi-bit digital signal A from the digital filter 10, and the number of bits is reduced by delta-sigma modulation (calculation processing). A noise shaper (delta sigma modulator) for transmitting the digital signal B, a waveform shaping circuit 14 for shaping the pulse forming the digital signal B from the noise shaper 12 according to the shaping clock signal, and a frequency f _s. A clock generator for generating a system clock signal φ _s having 18
Is a low pass filter (LPF) that filters the pulse output C from the circuit 14 and converts it into an analog output AO corresponding to the input DI.

The circuit portion surrounded by the alternate long and short dash line IC is configured as a monolithic or hybrid type integrated circuit and arranged in one package, and 16A is a crystal oscillator externally attached to the clock generator 16. I am a child. In some cases, the digital circuit 10 and its related portion (the portion surrounded by the broken line) are integrated into a circuit.

The digital input DI is, for example, waveform data containing 16-bit (1 word) data for each sample, and the data transmission frequency is 44.1 KHz. The frequency of the system clock signal φ _s is 1
It is 6.9 MHz, and the data transmission frequency from the digital filter 10 to the noise shaper 12 is normally f _s / 2.
(For example, 8.45 MHz).

The noise shaper 12 is provided to reduce the oversampling frequency in the oversampling DA conversion. Noise shaper 12
When a primary or secondary noise shaper is used as, a pulse density modulation (bit stream) output is obtained as the noise shaper output B, and when a tertiary or higher-order noise shaper is used, the pulse width is output B A modulated output is obtained.

In the noise shaper 12, the digital signal is converted into a representation with a reduced number of bits, and the error caused by such conversion becomes larger in the higher frequency region. That is, FIG. 5 shows the power spectrum of the ideal output of the noise shaper 12, and the noise power by noise shaping is maximum in the high frequency region near f _s / 2. Further, the monochromatic sharp power component P _a in the low frequency region is obtained when a sine wave is given to the input digital signal component, and the power component P _b
Is due to the system clock signal φ _s .

Since various noises are added to the ideal state of the noise shaper output B due to fluctuations when subjected to digital processing, if the output B is directly converted into an analog output by the LPF 18, an error will occur due to the noise component. Therefore, the noise shaper output B is shaped by the waveform shaping circuit 14 based on the system clock signal φ _s , and then the LPF
By supplying it to 18, the error due to the noise component is reduced.

[0009]

In the above DA converter, if the frequencies of the input of the digital filter 10 and the output of the noise shaper are f _i and f _o , respectively, f _o / f _i is called the oversampling ratio. The larger the oversampling ratio, the larger the S / N ratio.
As an example, the relationship between the oversampling ratio and the S / N ratio is as shown in FIG. 6 when the number of quantization bits is 2 and the order of the noise shaper is K = 1 to 4.
To obtain a good S / N ratio, the oversampling ratio may be increased.

For example, in order to obtain an S / N ratio of 120 dB with K = 2, the oversampling ratio is set to 4 from FIG.
It should be around 00. Original sampling is 50K
When performed at Hz, noise shaping is 400
× 50 KHz = 20 MHz, and the noise-shaping system clock frequency f _s is 20 MHz.

In order to operate the system at such a high frequency, circuits such as 10, 12, 14, 16 capable of high-speed operation are prepared, and shield measures are taken to prevent radio interference due to unnecessary radiation. However, it is necessary to apply them, which inevitably complicates the configuration and increases the cost.

An object of the present invention is to make it possible to obtain a high S / N ratio even if the oversampling ratio is lowered in the above-mentioned oversampling type DA converter.

[0013]

According to the present invention, in an oversampling type DA converter as described above, it is detected that the value of a digital input to a digital filter or a noise shaper is below a predetermined level, and a detection output is output. The level detecting means that is generated, the input increasing means that increases the value of the digital input by a predetermined amount according to the detection output from the level detecting means, the signal path from the noise shaper to the converting means, and the converting means. Signal control means connected to at least one of the output signal paths, wherein the at least one of the at least one of the signal control means is arranged to reduce the analog output in response to the detection output from the level detection means. And a device for controlling the signal of the signal path.

[0014]

According to the structure of the present invention, for low-level digital inputs below a predetermined level, noise shaping is performed with the input value increased by a predetermined amount, so that the S / N ratio is improved. As for the analog output corresponding to the low-level digital input, the signal and noise levels are reduced corresponding to a predetermined amount, so that a true analog value corresponding to the input value before the increase can be obtained and improved. The obtained S / N ratio is maintained as it is.

As described above, since the S / N ratio can be improved independently of the oversampling ratio, the S / N ratio higher than the conventional one can be obtained with the oversampling ratio lower than the conventional one.

[0016]

1 is a circuit diagram of an oversampling type DA converter according to an embodiment of the present invention.
The same parts as those in FIG. 4 are designated by the same reference numerals, and detailed description thereof will be omitted.

In the circuit of FIG. 1, on the output side of the digital filter 10, there is provided a shift circuit 20 capable of bit-shifting the digital signal A for each sample in the reflex direction. The output SA of this circuit 20 is a noise shaper. 12 are supplied. The level detection circuit 22 divides the system clock signal φ _{s or} the like to generate a digital signal A according to the timing signal T _m generated from the timing circuit 24.
It is determined whether the value is less than or equal to a predetermined level for each sample of 1. If the determination result is negative, a signal of "0" is generated as the detection output P, and if affirmative, a signal of "1" is generated. Occur. The predetermined level used for the determination is predetermined in consideration of the noise level.

The shift control circuit 26 includes the level detection circuit 2
The shift amount designation signal Q is supplied to the shift circuit 20 in accordance with the detection output P from 2. When the detection output P is "0", zero is designated as the shift amount by the signal Q, and P is "1". In case of, a predetermined number of bits is designated. When zero is designated as the shift amount, the shift circuit 20 sends the signal A as the output SA without shifting. If, for example, 2 bits are designated as the shift amount, the shift circuit 20
Sends an output SA having a value four times that of signal A by left-shifting one sample of signal A by 2 bits. In this way, the S / N ratio can be improved by increasing the value of the low-level digital signal of the predetermined level or less and inputting it to the noise shaper 12.

On the other hand, an attenuator 30 for receiving the analog signal AS from the LPF 18 via the buffer circuit 28 is provided on the output side of the LPF 18, and the attenuation amount of this attenuator 30 depends on the detection output P of the level detection circuit 22. Is controlled by the attenuation control circuit 32.

The attenuator 30 is, for example, an R-2R type resistor ladder network, and control switches S ₀ , S ₁ , S ₂ ... Connected to the series path of the resistors R by the resistor ladder network as shown in the figure.
S _n and an arbitrary control switch S _i (i
The output AO when any of (= 0 to n) is turned on is represented by AO = AS / 2 ⁱ when the input is AS.

The attenuation control circuit 32 generates a switch control signal S according to the detection output P. When P is "0", a signal S is generated to turn on the switch S ₀ , and P is "1". In the case of "", the signal S is generated so as to turn on a predetermined specific switch for compensating the above-mentioned shift amount. The shift amount is 2 bits as in the above example (magnification is 4 times)
In this case, the signal S is generated to turn on the switch S ₂ according to P = “1”, and as a result, the level of the analog signal AS and the accompanying noise is multiplied by 1/4.
Therefore, the analog value corresponding to the input value before being multiplied by 4 in the shift circuit 20 is obtained, and the S / N ratio improved in the shift circuit 20 remains as it is because the signal and the noise are both multiplied by 1/4. Maintained.

FIG. 2 shows an oversampling type DA converter according to another embodiment of the present invention. The same parts as those in FIG. 1 are designated by the same reference numerals and their detailed description will be omitted.

The feature of the embodiment shown in FIG. 2 is that the attenuation control is performed at the digital stage. That is, the pulse output B of the noise shaper 12 is input to the pulse width variable attenuator 34, where the pulse output B corresponds to the shift amount according to the attenuation control signal DS from the attenuation control circuit 32, as illustrated in FIG. The width is controlled to decrease. For example, when the shift amount is zero, a pulse output having a width W is transmitted as shown by K ₁ in FIG. 3, and when the shift amount is 1 bit, a pulse output having a width W / 2 is shown as K ₂ in FIG. When the shift amount is 2 bits, a pulse output having a width W / 4 is transmitted as indicated by K ₃ in FIG. In this way, when the pulse width is controlled to be reduced by the attenuator 34 in accordance with the shift amount in the shift circuit 20,
The pulse output K such as K _{1 to} K ₃ from the attenuator 34 is set to L
The analog output AO obtained through the PF 18 is K ₁ ~
The level will decrease in response to a decrease in pulse width such as K ₃ .

The present invention is not limited to the above embodiments, but can be implemented in various modified forms. For example, the following changes are possible.

(1) The circuit section including the shift circuit 20 and the shift control circuit 26 may be changed to a digital arithmetic circuit that multiplies the digital signal A by a predetermined coefficient and sends it as the output SA.

(2) Even if the circuit section including the buffer circuit 28, the attenuator 30 and the attenuation control circuit 32 is changed to an analog arithmetic circuit which multiplies the analog signal AS by a predetermined coefficient and sends it as the output AO. Good.

(3) In the level detection circuit 22, the input value range below a predetermined level may be divided into a plurality of ranges, and the shift amount and the attenuation amount may be controlled for each divided range.
That is, the level detection output P, the shift control circuit output Q, and the attenuation control circuit output S may all take a plurality of values of 3 or more.

(4) The shift circuit 20 may be provided before the digital filter 10 and the level detection may be performed on the input side of the shift circuit 20.

(5) The circuit section including the buffer circuit 28 and the attenuator 30 may be provided between the waveform shaping circuit 14 and the LPF 18.

(6) In the above description, one sample value (instantaneous value) of the digital input level was explained.
This description can be extended to input levels of waveforms consisting of multiple digital inputs, for example sine wave input levels. That is, when the sine wave input level is lower than a certain value,
The digital input forming the waveform may be shift-expanded and attenuated by the analog attenuator.

[0031]

As described above, according to the present invention, it is detected that the digital input value to the digital filter or noise shaper is below a predetermined level, the digital input value is increased by a predetermined amount, and the analog output is increased. Since the S / N ratio is improved by reducing the amount corresponding to the predetermined amount, the oversampling ratio can be reduced, and an oversampling DA converter with a simple structure and low cost can be realized. Is obtained.

[Brief description of drawings]

FIG. 1 is a block diagram showing a DA converter according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a DA converter according to another embodiment.

FIG. 3 is a signal waveform diagram for explaining the operation of the device of FIG.

FIG. 4 is a block diagram showing an example of a conventional DA converter.

FIG. 5 is a graph showing a power spectrum of a noise shaper output.

FIG. 6 is a graph showing the dependence of the S / N ratio on the oversampling ratio.

[Explanation of symbols]

10 ... Digital filter, 12 ... Noise shaper, 1
4 ... Waveform shaping circuit, 16 ... Clock generator, 18 ... Low pass filter, 20 ... Shift circuit, 22 ... Level detection circuit, 24 ... Timing circuit, 26 ... Shift control circuit, 2
8 ... Buffer circuit, 30 ... Attenuator, 32 ... Attenuation control circuit, 34 ... Pulse width variable attenuator.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Juro Hoshi 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka Yamaha Stock Association In-house (72) Inventor Tatsuya Kishii 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka In-house ( 72) Inventor Kuniaki Morita 10-1 Nakazawa-machi, Hamamatsu-shi, Shizuoka Yamaha Stock Association In-house

Claims (2)

[Claims] 1. A noise shaper for transmitting a digital signal having a reduced number of bits by delta-sigma modulating an oversampled multi-bit digital input, and (b) a digital signal from this noise shaper. A DA converter having conversion means for converting an analog output corresponding to a digital input, comprising: (c) a level detection means for detecting that the value of the digital input is below a predetermined level and generating a detection output; (D) input increasing means for increasing the value of the digital input by a predetermined amount according to the detection output from the level detecting means, and (e) a signal path from the noise shaper to the converting means and an output of the converting means. Signal control means connected to at least one of the signal paths, the level detecting means A DA converter for controlling the signal of the at least one signal path so as to reduce the analog output corresponding to the predetermined amount in accordance with the detection output from the means. 2. A digital filter for (a) oversampling a multi-bit digital input and sending it out, and (b) a digital signal with a reduced number of bits by delta-sigma modulating the digital signal from this digital filter. In a DA converter having a noise shaper for performing the following, and (c) a conversion means for converting a digital signal from the noise shaper into an analog output corresponding to the digital input, (d) the value of the digital input is below a predetermined level. (E) Input increasing means for increasing the value of the digital input by a predetermined amount according to the detection output from the level detecting means, and (f) A signal path from the noise shaper to the conversion means and an output signal of the conversion means Signal control means connected to at least one of the signal paths, the at least one signal path for reducing the analog output corresponding to the predetermined amount in response to a detection output from the level detection means. And a device for controlling the signal of.