JPH10335827A - Multilayered circuit board and hybrid integrated circuit using the board - Google Patents

Multilayered circuit board and hybrid integrated circuit using the board

Info

Publication number
JPH10335827A
JPH10335827A JP9145364A JP14536497A JPH10335827A JP H10335827 A JPH10335827 A JP H10335827A JP 9145364 A JP9145364 A JP 9145364A JP 14536497 A JP14536497 A JP 14536497A JP H10335827 A JPH10335827 A JP H10335827A
Authority
JP
Japan
Prior art keywords
layer
circuit board
circuit
conductive
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9145364A
Other languages
Japanese (ja)
Inventor
Toshiki Saito
俊樹 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP9145364A priority Critical patent/JPH10335827A/en
Publication of JPH10335827A publication Critical patent/JPH10335827A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/4038Through-connections; Vertical interconnect access [VIA] connections
    • H05K3/4046Through-connections; Vertical interconnect access [VIA] connections using auxiliary conductive elements, e.g. metallic spheres, eyelets, pieces of wire
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4644Manufacturing multilayer circuits by building the multilayer layer by layer, i.e. build-up multilayer circuits
    • H05K3/4652Adding a circuit layer by laminating a metal foil or a preformed metal foil pattern

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
  • Structure Of Printed Boards (AREA)

Abstract

PROBLEM TO BE SOLVED: To provide a multilayered circuit board which has a high interlayer connection reliability and a good productivity. SOLUTION: This is a multilayer circuit board, wherein at least one of conductor circuit layers 3 which is not the outermost layer is partially exposed, and at least one of the conductor circuit layers having exposed sections is electrically connected to the conductor circuit layer in the outermost layer via a conductive adhesive 7 and a conductive component 8. In such a multilayered circuit board, the shape of the exposed section is preferably a square or a rectangle, and the area is 0.25 mm<2> or larger.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、生産性に優れ、し
かも層間接続信頼性に優れた多層回路基板とそれを用い
た混成集積回路に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board excellent in productivity and excellent in reliability of interlayer connection and a hybrid integrated circuit using the same.

【0002】[0002]

【従来の技術】近年、半導体素子の高密度実装化を達成
する目的で、絶縁層を介して配線回路を複数層重ねた多
層構造の回路基板が注目されている。配線回路の多層化
を達成する手段としては、両面回路基板をプリプレグを
介して幾重かに張り合わせたものの表裏の最外層にプリ
プレグを介して銅箔を張り合わせる方法や、基材の上に
ビルドアップ方式で絶縁層と導体回路を順次形成する方
法等が知られているが、いずれの場合に於いても、各層
の導体回路を電気的に接続する手法は、銅メッキ、或い
は貴金属ペーストによる方法が主流となっている。
2. Description of the Related Art In recent years, for the purpose of achieving high-density mounting of semiconductor elements, a circuit board having a multilayer structure in which a plurality of wiring circuits are stacked via an insulating layer has attracted attention. Means to achieve multilayer wiring circuits include a method of laminating double-sided circuit boards several layers via prepreg, but bonding copper foil to the outermost layers on both sides via prepreg, or building up on the base material A method of sequentially forming an insulating layer and a conductor circuit by a method is known, but in any case, the method of electrically connecting the conductor circuits of each layer is a method using copper plating or a noble metal paste. It has become mainstream.

【0003】しかるに、銅メッキを行うためには、孔開
け、前処理、デスミア処理等の猥雑な工程を経ることが
余儀なくされ、生産性の点で満足できない。
[0003] However, in order to perform copper plating, it is necessary to go through obscene steps such as drilling, pre-treatment, and desmear treatment, which is not satisfactory in terms of productivity.

【0004】又、貴金属ペーストによる方法は、生産性
の点では良好であるが、層間接続信頼性の点で不十分で
あり、長期に渡り信頼性を要求される用途には適してい
ない。
The method using a noble metal paste is good in terms of productivity, but is insufficient in terms of interlayer connection reliability, and is not suitable for applications requiring long-term reliability.

【0005】[0005]

【発明が解決しようとする課題】本発明は、上記の事情
に鑑みてなされたものであり、多層回路基板の最外層で
ない導体回路の少なくとも1つが部分的に露出してお
り、この露出部を有する導体回路の少なくとも1つを該
露出部で導電性接着剤と導電性の部品とを介して最外層
の導体回路と電気的に接続することにより、層間接続信
頼性に優れた多層回路基板を生産性良く形成することが
可能であるという知見に基づいている。
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and at least one of the conductor circuits which is not the outermost layer of a multilayer circuit board is partially exposed. By electrically connecting at least one of the conductive circuits having the exposed portion to the outermost conductive circuit via a conductive adhesive and a conductive component, a multilayer circuit board having excellent interlayer connection reliability is obtained. It is based on the finding that it can be formed with high productivity.

【0006】即ち、本発明の目的は、層間接続信頼性に
優れた多層回路基板を生産性良く提供することである。
That is, an object of the present invention is to provide a multilayer circuit board having excellent interlayer connection reliability with high productivity.

【0007】[0007]

【課題を解決するための手段】本発明は、基材上に絶縁
層を介して複数の導体回路層が積層され、前記導体回路
層のうちの最外層でない導体回路層の少なくとも1つが
部分的に露出してなる多層回路基板であって、前記露出
部を有する導体回路層の少なくとも1つが該露出部で導
電性接着剤と導電性の部品とを介して最外層の導体回路
層と電気的に接続してなることを特徴とする多層回路基
板である。
According to the present invention, a plurality of conductive circuit layers are laminated on a base material via an insulating layer, and at least one of the conductive circuit layers which is not the outermost layer is partially formed. A multilayer circuit board exposed at least one of the conductive circuit layers having the exposed portions, wherein at least one of the conductive circuit layers having the exposed portions is electrically connected to an outermost conductive circuit layer via a conductive adhesive and a conductive component. A multilayer circuit board characterized by being connected to a multi-layer circuit board.

【0008】また、本発明は、前記露出部が、基材と垂
直方向から眺めた時に、長方形及び/又は正方形であ
り、好ましくは、前記露出部の基材と垂直方向から眺め
たときの面積が、いずれも0.25mm2 以上であるこ
とを特徴とする前記の多層回路基板である。更に、本発
明は、前記導電性の部品がジャンパー線或いはチップ抵
抗であることを特徴とする前記の多層回路基板である。
[0008] The present invention also provides that the exposed portion has a rectangular shape and / or a square shape when viewed from a direction perpendicular to the substrate, and preferably, an area of the exposed portion when viewed from a direction perpendicular to the substrate. However, in any of the above-mentioned multilayer circuit boards, each of them is 0.25 mm 2 or more. Further, the present invention is the multilayer circuit board described above, wherein the conductive component is a jumper wire or a chip resistor.

【0009】加えて、本発明は、前記の多層回路基板上
に、電子部品を搭載してなる混成集積回路である。
[0009] In addition, the present invention is a hybrid integrated circuit in which electronic components are mounted on the multilayer circuit board.

【0010】[0010]

【発明の実施の形態】以下、図を用いて本発明について
詳細に説明する。図1は、本発明の多層回路基板の一例
の断面図である。基材1上に導体回路層3を載置し、前
記導体回路層3上に絶縁層4が載置され、更に前記絶縁
層4上に導体回路層5が載置され、導体回路層3が部分
的に露出している部位において導電性接着剤7と導電性
の部品8とを介して最外層の導体回路層5と電気的に接
続されている。即ち、本発明においては、基材上に絶縁
層を介して複数の導体回路層が積層され、最外層でない
導体回路はその一部分で該導体回路上の絶縁層、導体回
路が欠落し露出しており、この露出部を有する導体回路
が導電性接着剤と導電性の部品とを介して最外層の導体
回路と電気的に接続しておりさえすれば良い。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 is a sectional view of an example of the multilayer circuit board of the present invention. The conductor circuit layer 3 is placed on the base material 1, the insulating layer 4 is placed on the conductor circuit layer 3, the conductor circuit layer 5 is placed on the insulating layer 4, and the conductor circuit layer 3 is placed on the substrate 1. At a portion that is partially exposed, the conductive circuit layer 5 is electrically connected to the outermost conductive circuit layer 5 via the conductive adhesive 7 and the conductive component 8. That is, in the present invention, a plurality of conductor circuit layers are laminated on a base material via an insulation layer, and the conductor circuit that is not the outermost layer is partially exposed and the insulation layer on the conductor circuit, the conductor circuit is missing and exposed. It is only necessary that the conductor circuit having the exposed portion be electrically connected to the outermost conductor circuit via the conductive adhesive and the conductive component.

【0011】基材1上には必要に応じて絶縁層2が介在
しても良い。また、導体回路層5上には必要に応じて半
田レジスト6が形成される。図示していないが、最外層
の導体回路層5上には電子素子が必要に応じ搭載されて
いてもよいし、ワイヤーボンディング等により他の部品
と結合されていてもよい。更に、導体回路層3と絶縁層
4の間には、他の導体回路層と絶縁層とが組合わさって
多層構造を示すものであっても勿論構わない。この場合
において、前記複数の絶縁層が必ずしも同一組成である
必要はない。更に、導体回路層3、5は基板1の少なく
とも一主面上の少なくとも一部に載置されていれば良
く、最外層の導体回路層上に他の回路基板を少なくとも
1層以上積層していても構わない。また、導体回路層は
複数ヶ所が露出しても構わないし、部分的に露出してい
る導体回路層は複数層あっても勿論構わない。更に、前
記複数の露出ヶ所が全てにおいて、導電性の部品と導電
性接着剤とを介して最外層の導電回路層に電気的に接続
されている必要はない。
An insulating layer 2 may be interposed on the substrate 1 if necessary. A solder resist 6 is formed on the conductor circuit layer 5 as needed. Although not shown, an electronic element may be mounted on the outermost conductive circuit layer 5 as necessary, or may be connected to another component by wire bonding or the like. Further, between the conductor circuit layer 3 and the insulation layer 4, a combination of other conductor circuit layers and the insulation layer may be of a multi-layer structure. In this case, the plurality of insulating layers need not necessarily have the same composition. Furthermore, the conductor circuit layers 3 and 5 need only be placed on at least a part of at least one main surface of the substrate 1, and at least one other circuit board is laminated on the outermost conductor circuit layer. It does not matter. In addition, a plurality of conductor circuit layers may be exposed, or a plurality of partially exposed conductor circuit layers may of course be provided. Furthermore, it is not necessary that all of the plurality of exposed locations be electrically connected to the outermost conductive circuit layer via a conductive component and a conductive adhesive.

【0012】本発明の多層回路基板は、回路導体層の露
出部が部品搭載面側から見たときに長方形及び/又は正
方形であり、好ましくは前記露出部の面積がいずれも
0.25mm2 以上である。回路導体層の露出部の形状
については、本発明者の検討によれば、長方形又は正方
形のときに、並行な縁を有するので導電性の部品を導電
性接着剤等を用いて導体回路に電気的に接続する際に導
電性の部品のリード端子が固定し易いし、しかも直角的
に屈曲することの多い導体回路と並行な2つの縁を有す
るので前記の固定が一層容易であり、好ましい。又、そ
の面積については、0.25mm2 以上の時に導電性の
部品の固定が極めて容易であり、好ましい。
In the multilayer circuit board of the present invention, the exposed portion of the circuit conductor layer is rectangular and / or square when viewed from the component mounting surface side, and preferably, the exposed portion has an area of 0.25 mm 2 or more. It is. Regarding the shape of the exposed portion of the circuit conductor layer, according to the study of the present inventor, when it is rectangular or square, it has parallel edges, so the conductive component is electrically connected to the conductor circuit using a conductive adhesive or the like. When electrically connected, the lead terminals of the conductive parts are easy to fix, and have two edges parallel to the conductor circuit that is often bent at a right angle, so that the fixing is easier and more preferable. Further, when the area is 0.25 mm 2 or more, it is extremely easy to fix the conductive component, which is preferable.

【0013】前記露出部は、回路導体層3上の絶縁層
4、更に上層の回路導体層5を除去して作成される。絶
縁層については、一般的なバイアホールやスルーホール
の加工方法を用いて除去することが可能であり、これら
の方法としては、例えばエキシマレーザー、CO2 レー
ザー、YAGレーザー等の各種レーザー光線を用いる方
法、絶縁層に感光性樹脂を用いて露光することによりパ
ターニングした後に電気接続用小孔部分を溶解する方
法、或いはケミカルドリリングにより化学的に絶縁層を
溶解する方法やサンドブラストにより機械的に絶縁層を
除去する方法等があげられる。しかし、本発明者らの検
討によれば、最外層の導体回路層5の所定の位置をエッ
チングにより除去し直下の絶縁層4まで開孔し、該孔底
部にレーザー光線を照射して絶縁層4を除去することに
より、電気接続用小孔を形成する方法が、寸法精度が高
く、周辺部に傷をいれず、生産性が良いので好ましい。
The exposed portion is formed by removing the insulating layer 4 on the circuit conductor layer 3 and the upper circuit conductor layer 5 further. The insulating layer can be removed by using a general method of processing a via hole or a through hole. Examples of these methods include a method using various laser beams such as an excimer laser, a CO 2 laser, and a YAG laser. A method of dissolving the small holes for electrical connection after patterning by exposing the insulating layer with a photosensitive resin, or a method of dissolving the insulating layer chemically by chemical drilling or mechanically forming the insulating layer by sandblasting. There is a method of removing. However, according to the study of the present inventors, a predetermined position of the outermost conductive circuit layer 5 is removed by etching, a hole is opened to the insulating layer 4 immediately below, and the bottom of the hole is irradiated with a laser beam to form the insulating layer 4. The method of forming a small hole for electrical connection by removing is preferred because the dimensional accuracy is high, the peripheral portion is not damaged, and the productivity is good.

【0014】本発明において、導電性の部品8としては
所望の回路特性が得られるようにジャンパー線やチップ
抵抗を用いることができる。前記ジャンパー線の材質と
しては、銅、鉄、アルミニウム、ニッケル、鉛、錫、
銀、チタニウムなの金属の他に、導電性の非金属、或い
は2種類以上の材料を含む化合物や混合物などが用いる
ことができる。又、導電性接着剤7としては、半田や導
電粉入りの各種接着剤或いは溶接など、導電性と接着性
を併せもってさえいればよく、一般的には共晶半田が用
いられる。従来、多層回路基板の導電回路層間を電気的
に接続させるためには、銅めっきや導電ペースト等を行
う必要があったが、多層回路基板上に電子部品を搭載す
る際、同時に導電性の部品8と導電性接着剤7で最外層
の導電回路層と内部の導電回路層とを電気的に接続する
ことで、前記工程は不要となる。
In the present invention, a jumper wire or a chip resistor can be used as the conductive component 8 so as to obtain desired circuit characteristics. As the material of the jumper wire, copper, iron, aluminum, nickel, lead, tin,
In addition to metals such as silver and titanium, conductive nonmetals, or compounds or mixtures containing two or more kinds of materials can be used. Further, as the conductive adhesive 7, it is only necessary to have both conductivity and adhesiveness, such as solder or various adhesives containing conductive powder, or welding, and eutectic solder is generally used. Conventionally, copper plating or conductive paste had to be performed to electrically connect the conductive circuit layers of the multilayer circuit board. However, when mounting electronic components on the multilayer circuit board, the conductive By electrically connecting the outermost conductive circuit layer and the inner conductive circuit layer with the conductive adhesive 8 and the conductive adhesive 7, the above step becomes unnecessary.

【0015】絶縁層2、4を構成する樹脂としては、エ
ポキシ樹脂、フェノール樹脂、ポリイミド樹脂の他各種
のエンジニアリングプラスチックが単独または2種以上
を混合して用いることができるが、このうちエポキシ樹
脂が金属同士の接合力に優れるので好ましい。特に、エ
ポキシ樹脂のなかでは、流動性が高く、各種セラミック
粉末との混合性に優れるビスフェノールA型エポキシ樹
脂、ビスフェノールF型エポキシ樹脂は一層好ましい樹
脂である。これらの樹脂はガラス繊維やセラミック粉末
が充填されていてもかまわない。
As the resin constituting the insulating layers 2 and 4, various engineering plastics other than epoxy resin, phenol resin and polyimide resin can be used alone or in combination of two or more. Among them, epoxy resin is used. It is preferable because the bonding strength between metals is excellent. Particularly, among the epoxy resins, bisphenol A type epoxy resin and bisphenol F type epoxy resin, which have high fluidity and are excellent in mixing with various ceramic powders, are more preferable resins. These resins may be filled with glass fiber or ceramic powder.

【0016】導体回路3、5の材質は銅、アルミニウ
ム、ニッケル、鉄、錫、銀、チタニウムのいずれか、ま
たは、これらの金属を2種類以上含む合金及びそれぞれ
の金属を使用したクラッド箔等が用いることができる。
また、この時の箔の製造方法は電解法でも圧延法で作製
したものでもよく、箔上にはNiメッキ、Ni−Auメ
ッキ、半田メッキなどの金属メッキがほどこされていて
もかまわないが、絶縁層2との接着性の点から、導体回
路層3の表面はエッチングや黒化処理、あるいはメッキ
等により予め粗化処理されていれば更に好ましい。
The material of the conductor circuits 3 and 5 may be any one of copper, aluminum, nickel, iron, tin, silver and titanium, or an alloy containing two or more of these metals, and a clad foil using each metal. Can be used.
In addition, the method of manufacturing the foil at this time may be one produced by an electrolytic method or a rolling method, and the metal plating such as Ni plating, Ni-Au plating, and solder plating may be applied on the foil, From the viewpoint of adhesion to the insulating layer 2, it is more preferable that the surface of the conductive circuit layer 3 has been roughened in advance by etching, blackening, plating, or the like.

【0017】尚、本発明においては、基材1の材質や厚
さに特に制限は無く、一般的な樹脂板や金属板などが広
く使用できる。
In the present invention, the material and thickness of the substrate 1 are not particularly limited, and a general resin plate or metal plate can be widely used.

【0018】以下、実施例に基づき、本発明を更に詳細
に説明する。
Hereinafter, the present invention will be described in more detail with reference to Examples.

【0019】[0019]

【実施例】【Example】

〔実施例1〕250mm×500mm×1.6mmで銅
箔厚さがそれぞれ35μmの両面ガラスエポキシ基板
(松下電工(株)製;R1766)の両面に所定の回路
を形成した後、プリプレグ(松下電工(株)製;R16
61)を介して銅箔厚さが35μmの銅箔を両面にプレ
ス積層し、外層銅箔に所定の回路を形成し、4層基板を
作成した。前記回路基板の最外層の導体回路層の所望の
位置にドリルで直下の絶縁層に達するφ0.3mmの小
孔を開け、該小孔の底部にCO2 レーザーをあてること
で、外層の導体回路層から内層の導体回路層に達する小
孔を設けた。この小孔の内部を過マンガン酸カリ溶液に
てデスミア処理した後に、内層の導体回路と外層の導体
回路層間を鉄製のジャンパー線と共晶半田により電気的
に接続した。この多層回路基板について層間接続信頼性
とその生産性を以下に示す方法で調べた。これらの結果
を表1に示した。
Example 1 A predetermined circuit was formed on both sides of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; 250 mm × 500 mm × 1.6 mm, each having a copper foil thickness of 35 μm), and then prepreg (Matsushita Electric Works) R16
61), a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. A small hole of φ0.3 mm reaching the insulating layer immediately below is drilled at a desired position of the outermost conductive circuit layer of the circuit board, and a CO 2 laser is applied to the bottom of the small hole, whereby the outer conductive circuit is formed. A small hole extending from the layer to the inner conductor circuit layer was provided. After the inside of the small holes was desmeared with a potassium permanganate solution, the inner conductor circuit and the outer conductor circuit layer were electrically connected to each other by an iron jumper wire and eutectic solder. The interlayer connection reliability and productivity of this multilayer circuit board were examined by the following methods. The results are shown in Table 1.

【0020】<層間接続信頼性の評価方法>JIS C
5012に規定された熱衝撃(高温浸漬)試験の方法
に従い、基板に100サイクルの熱衝撃を加えた後の導
体抵抗の初期値に対する変化率により評価した。
<Evaluation method of interlayer connection reliability> JIS C
In accordance with the method of the thermal shock (high temperature immersion) test specified in No. 5012, the evaluation was made based on the rate of change of the conductor resistance to the initial value after 100 cycles of thermal shock was applied to the substrate.

【0021】<生産性の評価方法>名刺サイズ(90m
m×50mm)の基板10,000枚を製造するのに要
した時間で評価した。
<Productivity Evaluation Method> Business card size (90 m
The evaluation was based on the time required to manufacture 10,000 substrates (m × 50 mm).

【0022】[0022]

【表1】 [Table 1]

【0023】〔実施例2〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、外層銅箔に所定の回路を形
成し、4層基板を作成した。前記回路基板の外層の導体
回路層の所望の位置にドリルで直下の絶縁層に達するφ
0.3mmの小孔を開け、該小孔の底部にCO2 レーザ
ーをあてることで、外層の導体回路層から内層の導体回
路層に達する小孔を設けた。この小孔の内部を過マンガ
ン酸カリ溶液にてデスミア処理した後に、内層の導体回
路層と外層の導体回路層間をチップ抵抗と共晶半田によ
り電気的に接続した。この多層回路基板について層間接
続信頼性とその生産性を実施例1と同じ方法で調べた。
これらの結果を表1に示した。
[Example 2] 250 mm x 500 mm x
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm, and then via a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.). Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. Drill to a desired position of the outer conductor circuit layer of the circuit board and reach the insulating layer immediately below φ
A small hole of 0.3 mm was made, and a CO 2 laser was applied to the bottom of the small hole to form a small hole extending from the outer conductive circuit layer to the inner conductive circuit layer. After the inside of the small holes was desmeared with a potassium permanganate solution, the inner conductor circuit layer and the outer conductor circuit layer were electrically connected by a chip resistor and eutectic solder. The interlayer connection reliability and the productivity of this multilayer circuit board were examined in the same manner as in Example 1.
The results are shown in Table 1.

【0024】〔実施例3〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、外層銅箔に所定の回路を形
成し、4層基板を作成した。前記回路基板の外層の導体
回路層の所望の位置にドリルで直下の絶縁層に達するφ
0.3mmの小孔を開け、該小孔の底部にCO2 レーザ
ーをあてることで、外層の導体回路層から内層の導体回
路層に達する小孔を設けた。この小孔の内部を過マンガ
ン酸カリ溶液にてデスミア処理した後に、内層の導体回
路層と外層の導体回路層間を鉄製のジャンパー線で溶接
により電気的に接続した。この多層回路基板について層
間接続信頼性とその生産性を実施例1と同じ方法で調べ
た。これらの結果を表1に示した。
Example 3 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm, and then via a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.). Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. Drill to a desired position of the outer conductor circuit layer of the circuit board and reach the insulating layer immediately below φ
A small hole of 0.3 mm was made, and a CO 2 laser was applied to the bottom of the small hole to form a small hole extending from the outer conductive circuit layer to the inner conductive circuit layer. After the interior of the small hole was desmeared with a potassium permanganate solution, the inner conductive circuit layer and the outer conductive circuit layer were electrically connected by welding with an iron jumper wire. The interlayer connection reliability and the productivity of this multilayer circuit board were examined in the same manner as in Example 1. The results are shown in Table 1.

【0025】〔実施例4〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、外層銅箔に所定の回路を形
成し、4層基板を作成した。前記回路基板の最外層の導
体回路層の所望の位置にドリルで直下の絶縁層に達する
0.25mm角の小孔を開け、該小孔の底部にCO2
ーザーをあてることで、最外層の導体回路層から内層の
導体回路層に達する小孔を設けた。この小孔の内部を過
マンガン酸カリ溶液にてデスミア処理した後に、内層の
導体回路層と外層の導体回路層間を鉄製のジャンパー線
と共晶半田により電気的に接続した。この多層回路基板
について層間接続信頼性とその生産性を実施例1と同じ
方法で調べた。これらの結果を表1に示した。
Example 4 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm, and then via a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.). Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. A hole of 0.25 mm square reaching the insulating layer immediately below is drilled at a desired position of the outermost conductive circuit layer of the circuit board, and a CO 2 laser is applied to the bottom of the hole to form the outermost layer. Small holes were provided from the conductor circuit layer to the inner conductor circuit layer. After the inside of the small hole was desmeared with a potassium permanganate solution, the inner conductor circuit layer and the outer conductor circuit layer were electrically connected to each other by an iron jumper wire and eutectic solder. The interlayer connection reliability and the productivity of this multilayer circuit board were examined in the same manner as in Example 1. The results are shown in Table 1.

【0026】〔実施例5〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、外層銅箔に所定の回路を形
成し、4層基板を作成した。前記回路基板の外層の導体
回路層の所望の位置にドリルで直下の絶縁層に達する
0.5mm角の小孔を開け、該小孔の底部にCO2 レー
ザーをあてることで、外層の導体回路層から内層の導体
回路層に達する小孔を設けた。この小孔の内部を過マン
ガン酸カリ溶液にてデスミア処理した後に、内層の導体
回路層と外層の導体回路層間を鉄製のジャンパー線と共
晶半田により電気的に接続した。この多層回路基板につ
いて層間接続信頼性とその生産性を実施例1と同じ方法
で調べた。これらの結果を表1に示した。
Example 5 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm, and then via a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.). Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. A 0.5 mm square hole reaching the insulating layer immediately below is drilled at a desired position of the outer conductive circuit layer of the circuit board, and a CO 2 laser is applied to the bottom of the small hole. A small hole extending from the layer to the inner conductor circuit layer was provided. After the inside of the small hole was desmeared with a potassium permanganate solution, the inner conductor circuit layer and the outer conductor circuit layer were electrically connected to each other by an iron jumper wire and eutectic solder. The interlayer connection reliability and the productivity of this multilayer circuit board were examined in the same manner as in Example 1. The results are shown in Table 1.

【0027】〔実施例6〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、外層銅箔に所定の回路を形
成し、4層基板を作成した。前記回路基板の外層の導体
回路層の所望の位置にドリルで直下の絶縁層に達する
0.5mm×1.0mmの小孔を開け、該小孔の底部に
CO2 レーザーをあてることで、外層の導体回路層から
内層の導体回路層に達する小孔を設けた。この小孔の内
部を過マンガン酸カリ溶液にてデスミア処理した後に、
内層の導体回路層と外層の導体回路層間を鉄製のジャン
パー線と共晶半田により電気的に接続した。この多層回
路基板について層間接続信頼性とその生産性を実施例1
と同じ方法で調べた。これらの結果を表1に示した。
Example 6 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm, and then via a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.). Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. A hole of 0.5 mm × 1.0 mm reaching the insulating layer immediately below is drilled at a desired position of the conductor circuit layer on the outer layer of the circuit board, and a CO 2 laser is applied to the bottom of the hole. A small hole extending from the conductive circuit layer of No. 1 to the inner conductive circuit layer was provided. After desmearing the inside of this small hole with potassium permanganate solution,
The inner conductive circuit layer and the outer conductive circuit layer were electrically connected by an iron jumper wire and eutectic solder. Example 1 The interlayer connection reliability and the productivity of this multilayer circuit board were evaluated in Example 1.
I examined it in the same way. The results are shown in Table 1.

【0028】〔実施例7〕内層の導体回路層をシールド
パターンとした実施例6の多層回路基板に所定の電子部
品を搭載し、DC/DCコンバータたる混成集積回路を
作成した。この混成集積回路を動作させてみたが、ノイ
ズの発生は極めて少なく、またその他の電気的な異常も
認められなかった。
[Embodiment 7] Predetermined electronic components were mounted on the multilayer circuit board of Embodiment 6 in which the inner conductor circuit layer was a shield pattern, and a hybrid integrated circuit as a DC / DC converter was prepared. When the hybrid integrated circuit was operated, generation of noise was extremely small, and no other electrical abnormality was observed.

【0029】〔比較例1〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、外層銅箔に所定の回路を形
成し、4層基板を作成した。前記回路基板の外層の導体
回路層の所望の位置にドリルで直下の絶縁層に達するφ
0.3mmの小孔を開け、該小孔の底部にCO2 レーザ
ーをあてることで、外層の導体回路層から内層の導体回
路層に達する小孔を設けた。この小孔の内部を過マンガ
ン酸カリ溶液にてデスミア処理した後に、内層の導体回
路層と外層の導体回路層間を銀ペースト(アサヒ化研製
LS−506J)により電気的に接続した。この多層
回路基板について層間接続信頼性とその生産性を実施例
1と同じ方法で調べた。これらの結果を表1に示した
が、層間接続信頼性の点で不十分であった。
Comparative Example 1 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm, and then via a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.). Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. Drill to a desired position of the outer conductor circuit layer of the circuit board and reach the insulating layer immediately below φ
A small hole of 0.3 mm was made, and a CO 2 laser was applied to the bottom of the small hole to form a small hole extending from the outer conductive circuit layer to the inner conductive circuit layer. After the inside of the small hole was desmeared with a potassium permanganate solution, the inner conductive circuit layer and the outer conductive circuit layer were electrically connected by a silver paste (LS-506J manufactured by Asahi Kaken). The interlayer connection reliability and the productivity of this multilayer circuit board were examined in the same manner as in Example 1. These results are shown in Table 1, but were insufficient in terms of interlayer connection reliability.

【0030】〔比較例2〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、外層銅箔に所定の回路を形
成し、4層基板を作成した。前記回路基板の外層の導体
回路層の所望の位置にドリルで直下の絶縁層に達するφ
0.3mmの小孔を開け、該小孔の底部にCO2 レーザ
ーをあてることで、外層の導体回路層から内層の導体回
路層に達する小孔を設けた。この小孔の内部を過マンガ
ン酸カリ溶液にてデスミア処理した後に、内層の導体回
路層と外層の導体回路層間を厚さ20μmの銅メッキを
施し電気的に接続した。この多層回路基板について層間
接続信頼性とその生産性を実施例1と同じ方法で調べ
た。これらの結果を表1に示したが、生産性の点で不十
分であった。
Comparative Example 2 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm, and then via a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.). Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. Drill to a desired position of the outer conductor circuit layer of the circuit board and reach the insulating layer immediately below φ
A small hole of 0.3 mm was made, and a CO 2 laser was applied to the bottom of the small hole to form a small hole extending from the outer conductive circuit layer to the inner conductive circuit layer. After the interior of the small holes was desmeared with a potassium permanganate solution, the inner conductive circuit layer and the outer conductive circuit layer were plated with copper with a thickness of 20 μm and electrically connected. The interlayer connection reliability and the productivity of this multilayer circuit board were examined in the same manner as in Example 1. The results are shown in Table 1, but were insufficient in productivity.

【0031】[0031]

【発明の効果】本発明の多層回路基板は、層間接続信頼
性に優れているので、いろいろな用途に安心して用いる
ことができるし、本発明の製造方法によれば、前記多層
回路基板を生産性良く提供することができるので、産業
上非常に有用である。
The multilayer circuit board of the present invention has excellent interlayer connection reliability, so that it can be used for various applications with ease. According to the manufacturing method of the present invention, the multilayer circuit board is produced. Since it can be provided with good quality, it is very useful in industry.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の多層回路基板の一例を示す断面図。FIG. 1 is a sectional view showing an example of a multilayer circuit board of the present invention.

【符号の説明】[Explanation of symbols]

1 基材 2 絶縁層 3 導体回路層 4 絶縁層 5 導体回路層 6 半田レジスト 7 導電性接着剤 8 導電性の部品 REFERENCE SIGNS LIST 1 base material 2 insulating layer 3 conductive circuit layer 4 insulating layer 5 conductive circuit layer 6 solder resist 7 conductive adhesive 8 conductive component

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基材上に絶縁層を介して複数の導体回路層
が積層され、前記導体回路層のうちの最外層でない導体
回路層の少なくとも1つが部分的に露出してなる多層回
路基板であって、前記の露出部を有する導体回路層の少
なくとも1つが該露出部において導電性接着剤と導電性
の部品とを介して最外層の導体回路層と電気的に接続し
てなることを特徴とする多層回路基板。
1. A multilayer circuit board comprising a plurality of conductive circuit layers laminated on a base material via an insulating layer, and at least one of the conductive circuit layers which is not the outermost layer is partially exposed. Wherein at least one of the conductor circuit layers having the exposed portions is electrically connected to an outermost conductor circuit layer via a conductive adhesive and a conductive component at the exposed portions. Characteristic multilayer circuit board.
【請求項2】前記露出部が、基材と垂直方向から眺めた
時に、いずれも長方形及び/又は正方形であることを特
徴とする請求項1記載の多層回路基板。
2. The multilayer circuit board according to claim 1, wherein each of the exposed portions is rectangular and / or square when viewed from a direction perpendicular to the substrate.
【請求項3】前記露出部の基材と垂直方向から眺めたと
きの面積が、いずれも0.25mm2 以上であることを
特徴とする請求項2記載の多層回路基板。
3. The multilayer circuit board according to claim 2, wherein the area of each of the exposed portions when viewed from a direction perpendicular to the substrate is 0.25 mm 2 or more.
【請求項4】導電性の部品がジャンパー線であることを
特徴とする請求項1記載の多層回路基板。
4. The multilayer circuit board according to claim 1, wherein the conductive component is a jumper wire.
【請求項5】導電性の部品がチップ抵抗であることを特
徴とする請求項1記載の多層回路基板。
5. The multilayer circuit board according to claim 1, wherein the conductive component is a chip resistor.
【請求項6】請求項1、請求項2、請求項3、請求項
4、又は請求項5記載の多層回路基板上に、電子部品を
搭載してなる混成集積回路。
6. A hybrid integrated circuit in which electronic components are mounted on the multilayer circuit board according to claim 1, 2, 3, 4, or 5.
JP9145364A 1997-06-03 1997-06-03 Multilayered circuit board and hybrid integrated circuit using the board Pending JPH10335827A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9145364A JPH10335827A (en) 1997-06-03 1997-06-03 Multilayered circuit board and hybrid integrated circuit using the board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9145364A JPH10335827A (en) 1997-06-03 1997-06-03 Multilayered circuit board and hybrid integrated circuit using the board

Publications (1)

Publication Number Publication Date
JPH10335827A true JPH10335827A (en) 1998-12-18

Family

ID=15383508

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9145364A Pending JPH10335827A (en) 1997-06-03 1997-06-03 Multilayered circuit board and hybrid integrated circuit using the board

Country Status (1)

Country Link
JP (1) JPH10335827A (en)

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