JPH10284843A - Multilayered circuit board and its manufacture - Google Patents

Multilayered circuit board and its manufacture

Info

Publication number
JPH10284843A
JPH10284843A JP9097097A JP9097097A JPH10284843A JP H10284843 A JPH10284843 A JP H10284843A JP 9097097 A JP9097097 A JP 9097097A JP 9097097 A JP9097097 A JP 9097097A JP H10284843 A JPH10284843 A JP H10284843A
Authority
JP
Japan
Prior art keywords
holes
layer
circuit board
small hole
conductor circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9097097A
Other languages
Japanese (ja)
Inventor
Toshiki Saito
俊樹 斉藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Denka Co Ltd
Original Assignee
Denki Kagaku Kogyo KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Denki Kagaku Kogyo KK filed Critical Denki Kagaku Kogyo KK
Priority to JP9097097A priority Critical patent/JPH10284843A/en
Publication of JPH10284843A publication Critical patent/JPH10284843A/en
Pending legal-status Critical Current

Links

Abstract

PROBLEM TO BE SOLVED: To form a multilayer circuit board having extremely highly reliable via holes with high productivity by connecting conductor circuit layers to each other after the bottom sections of small holes for forming the via holes are etched and the carbon concentrations on the bottoms of the holes are made lower than a specific value. SOLUTION: After a conductor circuit layer 2 is provided on a substrate 1, another conductor circuit layer 4 is formed on the layer 2 through an insulating layer 3. Then holes are formed into the outermost conductor circuit layer 4 by partially etching off the layer 4 at prescribed positions and the insulating layer 3 exposed in the holes is removed with a laser beam. Therefore, small holes for electrical connection can be formed with high dimensional accuracy without giving any damage to the peripheral sections of the holes. After the holes are bored, the depths of the holes are increased to >=3 μm by etching the holes with an aqueous solution of ferric chloride, cupric chloride, etc., so that the carbon concentrations on the bottoms of the holes may become <=6×10<-8> g/mm<2> . Then the conductor circuit layers 4 and 2 are electrically connected to each other by forming via holes 5 by plating the holes with solder or copper.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、バイアホールの信
頼性に優れ、しかも生産性に優れた多層回路基板とその
製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer circuit board having excellent via hole reliability and excellent productivity, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、半導体素子の高密度実装化を達成
する目的で、配線回路を絶縁層を介して複数層重ねた多
層回路基板が注目されている。特に、基板の少なくとも
一主面上に絶縁層を介して配線回路を形成し、更に絶縁
層を介して配線回路を形成することを繰り返す方法(ビ
ルドアップ法)により得られる多層回路基板は、高密度
実装に対応しやすく、コスト的にも有利であるため、注
目を浴びている。
2. Description of the Related Art In recent years, for the purpose of achieving high-density mounting of semiconductor elements, a multilayer circuit board in which a plurality of wiring circuits are stacked via an insulating layer has attracted attention. In particular, a multilayer circuit board obtained by a method (build-up method) in which a wiring circuit is formed on at least one principal surface of a substrate with an insulating layer interposed therebetween and a wiring circuit is further formed with the insulating layer interposed therebetween is repeatedly used. It is attracting attention because it is easy to cope with density mounting and is advantageous in terms of cost.

【0003】一般に多層回路基板においては、空間的に
多層に配置されたおのおのの配線回路間を電気的に接続
するために、ワイヤーボンディング、バイアホール、ス
ルーホール等の構造が採用される。近年、基板の高密度
化、生産性の向上等の観点から、バイアホールが採用さ
れることが多くなってきたものの、電気的に信頼性の高
いバイアホールを安定して、生産性高く達成することは
容易なことでない。
In general, a multilayer circuit board employs a structure such as a wire bonding, a via hole, a through hole or the like in order to electrically connect wiring circuits arranged spatially in multiple layers. In recent years, via holes have been increasingly used from the viewpoints of increasing the density of substrates and improving productivity, etc., but achieve stable and highly productive via holes with high electrical reliability. It is not easy.

【0004】特に、前記ビルドアップ法で得られる多層
回路基板に関しては、信頼性に優れた層間接続を得るに
は、導体回路層に接続されたバイアホール用小孔を設
け、デスミア処理した後に銅めっきにより電気的に接続
する手法に頼らざるを得ないが、この方法ではバイアホ
ールの底面エッヂ部の銅めっきが細り易く、層間接続信
頼性の低下を招くと同時にデスミア処理による生産性の
低下を余儀なくされていた。
In particular, with respect to a multilayer circuit board obtained by the above build-up method, in order to obtain a highly reliable interlayer connection, a small hole for a via hole connected to a conductor circuit layer is provided, and after a desmear process, copper is removed. Although it is necessary to rely on a method of electrical connection by plating, this method tends to make the copper plating on the bottom edge of the via hole thinner, which lowers the reliability of interlayer connection and at the same time reduces productivity by desmearing. Had to be forced.

【0005】本発明は、上記の事情に鑑みてなされたも
のであり、バイアホール用小孔の底部をエッチングし炭
素濃度を低下させてから、各導体回路層間の接続を行う
ことにより、極めて信頼性に優れたバイアホールを有す
る多層回路基板を生産性良く形成することが可能である
という知見に基づいている。
[0005] The present invention has been made in view of the above circumstances, and by etching the bottom of a small hole for a via hole to lower the carbon concentration, and then connecting between the conductor circuit layers, extremely reliable. Based on the finding that it is possible to form a multilayer circuit board having via holes excellent in productivity with high productivity.

【0006】即ち、本発明の目的は、信頼性に極めて優
れたバイアホールを有する多層回路基板を生産性良く提
供することである。
That is, an object of the present invention is to provide a multilayer circuit board having via holes with extremely high reliability with high productivity.

【0007】[0007]

【課題を解決するための手段】本発明は、基板の少なく
とも一主面上に絶縁層を介して複数の導体回路層を載置
し、しかも最外層の導体回路層から最外層でない導体回
路層に電気的に接続するための小孔を設けてなる多層回
路基板であって、前記小孔の底面の炭素濃度が6×10
-8g/mm2 以下であることを特徴とする多層回路基板
であり、好ましくは、前記小孔の底面が該底面を形成す
る最外層でない導体回路層の表面よりも3μm以上低く
基板側に凹んでいる前記多層回路基板である。
According to the present invention, a plurality of conductive circuit layers are mounted on at least one principal surface of a substrate via an insulating layer, and the outermost conductive circuit layer is shifted to a non-outermost conductive circuit layer. A multi-layer circuit board provided with small holes for electrical connection to the substrate, wherein the carbon concentration at the bottom surface of the small holes is 6 × 10
-8 g / mm 2 or less, and preferably, the bottom surface of the small hole is at least 3 μm lower than the surface of the non-outermost conductive circuit layer forming the bottom surface. The multilayer circuit board is recessed.

【0008】又、本発明は、基板の少なくとも一主面上
に絶縁層を介して複数の導体回路層を載置し、前記導体
回路層のうちの最外層の導体回路層と最外層でない導体
回路層とを電気的に接続するための小孔を設ける多層回
路基板の製造方法であって、前記小孔を形成後、該小孔
の底面をエッチングし、しかる後に電気的接続すること
を特徴とする多層回路基板の製造方法であり、好ましく
は、前記小孔の底面をエッチングすることで、小孔の底
面の炭素濃度を制御することを特徴とする前記多層回路
基板の製造方法である。
Further, the present invention provides a method for mounting a plurality of conductive circuit layers on at least one principal surface of a substrate via an insulating layer, wherein the outermost conductive circuit layer and the non-outermost conductive circuit layer among the conductive circuit layers are provided. What is claimed is: 1. A method for manufacturing a multi-layer circuit board, wherein a small hole for electrically connecting a circuit layer is provided, wherein after forming the small hole, the bottom surface of the small hole is etched and then electrically connected. Preferably, the method is a method of manufacturing a multilayer circuit board, characterized in that the bottom surface of the small hole is etched to control the carbon concentration at the bottom surface of the small hole.

【0009】更に、本発明は、前記多層回路基板の製造
方法であって、小孔をレーザー照射により形成するこ
と、小孔の底面を3μm以上エッチングすることを特徴
とする多層回路基板の製造方法である。
Further, the present invention relates to a method for manufacturing a multilayer circuit board, wherein the small holes are formed by laser irradiation, and the bottom surface of the small holes is etched by 3 μm or more. It is.

【0010】[0010]

【発明の実施の形態】以下、図を用いて本発明について
詳細に説明する。図1に、本発明の多層回路基板の一例
について、その断面図を示す。基板1上に導体回路層2
を有し、更に前記導体回路層2上に絶縁層3が載置さ
れ、更に前記絶縁層3上に導体回路層4が載置され、最
外層の導体回路層4は導体回路層2とバイアホール5に
より電気的に接続されている。なお、図示していない
が、最外層の導体回路層4上には電子素子が必要に応じ
搭載されていてもよいし、ワイヤーボンディング等によ
り他の部品と結合されていてもよい。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described below in detail with reference to the drawings. FIG. 1 shows a cross-sectional view of an example of the multilayer circuit board of the present invention. Conductive circuit layer 2 on substrate 1
Further, an insulating layer 3 is mounted on the conductive circuit layer 2, a conductive circuit layer 4 is further mounted on the insulating layer 3, and the outermost conductive circuit layer 4 is It is electrically connected by the hole 5. Although not shown, an electronic element may be mounted on the outermost conductive circuit layer 4 as necessary, or may be connected to other components by wire bonding or the like.

【0011】尚、本発明の多層回路基板は、最外層の導
体回路層から最外層でない導体回路層に電気的に接続す
るバイアホールを有する多層回路基板であれば良く、図
1において前記導体回路層4上に更に絶縁層を介して導
体回路層が積層されたものであっても勿論構わない。更
に、導体回路層は基板1の少なくとも一主面上の少なく
とも一部に積層されていれば良く、最外層の導体回路層
上に他の回路基板を少なくとも1層以上積層していても
構わない。
The multi-layer circuit board of the present invention may be a multi-layer circuit board having via holes for electrically connecting from the outermost conductive circuit layer to a non-outermost conductive circuit layer. Of course, a conductive circuit layer may be further laminated on the layer 4 with an insulating layer interposed therebetween. Further, the conductor circuit layer may be laminated on at least a part of at least one main surface of the substrate 1, and at least one other circuit board may be laminated on the outermost conductor circuit layer. .

【0012】本発明の多層回路基板は、前記バイアホー
ル5に用いられる小孔の底面部を形成する導体回路層の
表面の炭素濃度が6×10-8g/mm2 以下であり、好
ましくは4×10-8g/mm2 以下である。この理由に
付いては明かでないが、本発明者らの実験的検討によれ
ば、炭素濃度が6×10-8g/mm2 より高い場合に
は、小孔に半田や銅メッキを施してバイヤホールを形成
するときに、小孔の底面での半田濡れ性や銅メッキ性が
悪く、電気的に信頼性高いバイヤホールが形成すること
ができないでの好ましくない。ことに炭素濃度が4×1
-8g/mm2 以下の時には電気的に信頼性の高いバイ
ヤホールを安定して得ることができ好ましい。
In the multilayer circuit board of the present invention, the surface of the conductor circuit layer forming the bottom of the small hole used in the via hole 5 has a carbon concentration of 6 × 10 −8 g / mm 2 or less, preferably It is not more than 4 × 10 −8 g / mm 2 . Although the reason for this is not clear, according to experimental studies by the present inventors, when the carbon concentration is higher than 6 × 10 −8 g / mm 2 , the small holes are plated with solder or copper. When forming a via hole, solder wettability and copper plating property at the bottom surface of the small hole are poor, and it is not preferable because a via hole having high electrical reliability cannot be formed. Especially when the carbon concentration is 4 × 1
When it is 0 -8 g / mm 2 or less, via holes having high electrical reliability can be stably obtained, which is preferable.

【0013】更に、本発明では、前記小孔の底面部が該
底面を形成する最外層でない導体回路層の表面よりも3
μm以上、特に5μm以上低く基板側に凹んでいること
が好ましい。この理由に付いては、小孔に半田或いは銅
メッキして電気的接続を施す際に、小孔の底部を構成す
る導体回路層とその直上の絶縁層との境界が底部と同一
平面上にないようにすることで、半田或いは銅メッキと
導体回路との接触面積が増加するとともに、半田或いは
銅メッキの角部への不要な応力集中を避けることができ
るものと推察される。尚、上限に付いては特にこだわる
理由がないが、導体回路層の厚みが一般的には9〜30
0μmであり、これにより制限される。
Further, in the present invention, the bottom surface of the small hole is more than the surface of the conductor circuit layer which is not the outermost layer and forms the bottom surface.
It is preferable that it is recessed toward the substrate side by at least 5 μm, particularly at least 5 μm. For this reason, when conducting electrical connection by soldering or copper plating in the small hole, the boundary between the conductor circuit layer constituting the bottom of the small hole and the insulating layer immediately above it is on the same plane as the bottom. It is presumed that by avoiding this, the contact area between the solder or copper plating and the conductor circuit increases and unnecessary stress concentration on the corners of the solder or copper plating can be avoided. Although there is no particular reason for the upper limit, the thickness of the conductor circuit layer is generally 9 to 30.
0 μm, which is limited by this.

【0014】本発明における、小孔底部の炭素濃度の測
定方法は、小孔の底面が受ける履歴と同一の履歴を受け
た銅箔についてその表面をSEM−EDX法により走査
し、予め化学分析法で炭素濃度が既知の試片を用いて作
成した検量線と比較することで、炭素濃度を測定する方
法による。
In the present invention, the method of measuring the carbon concentration at the bottom of a small hole is as follows: a copper foil having the same history as the bottom surface of the small hole is scanned by a SEM-EDX method on a surface thereof, and a chemical analysis method is performed in advance. The method is based on a method of measuring the carbon concentration by comparing with a calibration curve prepared using a test piece having a known carbon concentration.

【0015】本発明の電気接続用小孔は、一般的なバイ
アホールやスルーホールの加工方法を用いて作成するこ
とが可能であり、これらの方法としては、例えばエキシ
マレーザー、CO2 レーザー、YAGレーザー等の各種
レーザー光線を用いる方法、絶縁層に感光性樹脂を用い
て露光することによりパターニングした後に電気接続用
小孔部分を溶解する方法、或いはケミカルドリリングに
より化学的に絶縁層を溶解する方法やサンドブラストに
より機械的に絶縁層を除去する方法等があげられる。し
かし、本発明者らの検討によれば、最外層の導体回路層
4の所定の位置をエッチングにより除去し直下の絶縁層
3まで開孔し、該孔底部にレーザー光線を照射して絶縁
層3を除去することにより、電気接続用小孔を形成する
方法が、寸法精度が高く、周辺部に傷をいれず、生産性
が良いので好ましい。
The small hole for electric connection of the present invention can be formed by using a general method for processing a via hole or a through hole. These methods include, for example, an excimer laser, a CO 2 laser, and a YAG laser. A method of using various laser beams such as a laser, a method of dissolving the small holes for electrical connection after patterning by exposing the insulating layer with a photosensitive resin, or a method of chemically dissolving the insulating layer by chemical drilling, There is a method of mechanically removing the insulating layer by sandblasting. However, according to the study of the present inventors, a predetermined position of the outermost conductive circuit layer 4 is removed by etching, a hole is formed up to the insulating layer 3 immediately below, and the bottom of the hole is irradiated with a laser beam to form the insulating layer 3. The method of forming a small hole for electrical connection by removing is preferred because the dimensional accuracy is high, the peripheral portion is not damaged, and the productivity is good.

【0016】また、電気接続用孔の底面の表面の炭素濃
度を6×10-8g/mm2 以下、好ましくは4×10-8
g/mm2 以下にする方法としては、窄孔後に小孔の底
面の導体回路層の表面を過マンガン酸カリ、濃硫酸等に
よりデスミア処理する方法や、塩化第二鉄、塩化第二
銅、過硫酸塩類、硫酸+過酸化水素、アルカリエッチャ
ント等の水溶液を用いてエッチングする方法を採用する
ことができる。このうち、生産性の点から、又前述した
とおりに小孔の底部に凹みを付すことができるという面
からエッチングする方法が最も好ましい方法である。
尚、エッチングの深さは3μm以上、好ましくは5μm
以上が好ましい。3μm未満では孔の底面の表面の炭素
濃度が6×10-8g/mm2 以下にならないことがある
し、半田濡れ性が悪い場合があるためである。本発明者
らの検討によれば、エッチング深さを好ましい5μm以
上とする時には、前記炭素濃度が4×10-8g/mm2
以下を達成でき、高信頼性のバイアホールを有する多層
回路基板を得ることができる。
The carbon concentration on the bottom surface of the electrical connection hole is not more than 6 × 10 −8 g / mm 2 , preferably 4 × 10 −8 g / mm 2.
g / mm 2 or less, such as a method of desmearing the surface of the conductive circuit layer on the bottom surface of the small hole with potassium permanganate, concentrated sulfuric acid, or the like after the opening, ferric chloride, cupric chloride, or the like. An etching method using an aqueous solution of persulfates, sulfuric acid + hydrogen peroxide, alkali etchant, or the like can be employed. Among them, the most preferable method is the method of etching from the viewpoint of productivity and from the viewpoint that the bottom of the small hole can be recessed as described above.
The etching depth is 3 μm or more, preferably 5 μm.
The above is preferred. If it is less than 3 μm, the carbon concentration on the bottom surface of the hole may not be 6 × 10 −8 g / mm 2 or less, and the solder wettability may be poor. According to the study of the present inventors, when the etching depth is set to 5 μm or more, the carbon concentration is 4 × 10 −8 g / mm 2.
The following can be achieved, and a multilayer circuit board having a highly reliable via hole can be obtained.

【0017】絶縁層を構成する樹脂としては、エポキシ
樹脂、フェノール樹脂、ポリイミド樹脂の他各種のエン
ジニアリングプラスチックが単独または2種以上を混合
して用いることができるが、このうちエポキシ樹脂が金
属同士の接合力に優れるので好ましい。特に、エポキシ
樹脂のなかでは、流動性が高く、各種セラミック粉末と
の混合性に優れるビスフェノールA型エポキシ樹脂、ビ
スフェノールF型エポキシ樹脂は一層好ましい樹脂であ
る。これらの樹脂はガラス繊維やセラミック粉末が充填
されていてもかまわない。
As the resin constituting the insulating layer, various engineering plastics such as epoxy resin, phenol resin and polyimide resin can be used alone or in combination of two or more. It is preferable because of its excellent bonding strength. Particularly, among the epoxy resins, bisphenol A type epoxy resin and bisphenol F type epoxy resin, which have high fluidity and are excellent in mixing with various ceramic powders, are more preferable resins. These resins may be filled with glass fiber or ceramic powder.

【0018】導体回路2、4の材質は銅、アルミニウ
ム、ニッケル、鉄、錫、銀、チタニウムのいずれか、ま
たは、これらの金属を2種類以上含む合金及びそれぞれ
の金属を使用したクラッド箔等が用いることができる。
また、この時の箔の製造方法は電解法でも圧延法で作製
したものでもよく、箔上にはNiめっき、Ni+Auめ
っき、はんだめっきなどの金属めっきがほどこされてい
てもかまわないが、絶縁層3との接着性の点から、導体
回路2、4の表面はエッチングやめっきにより予め粗
化処理されていれば更に好ましい。
The material of the conductor circuits 2 and 4 is copper, aluminum, nickel, iron, tin, silver, titanium, an alloy containing two or more of these metals, and a clad foil using each metal. Can be used.
At this time, the foil may be manufactured by an electrolytic method or a rolling method, and the foil may be plated with a metal such as Ni plating, Ni + Au plating, or solder plating. from the viewpoint of adhesion to the 3, the surface of the conductor circuit 2 and 4 a further preferred if it is previously roughened by etching or plating.

【0019】尚、本発明においては、基板1の材質や厚
さに特に制限は無く、一般的な樹脂基板や金属基板など
が広く使用できる。
In the present invention, the material and thickness of the substrate 1 are not particularly limited, and general resin substrates and metal substrates can be widely used.

【0020】以下、実施例に基づき、本発明を更に詳細
に説明する。
Hereinafter, the present invention will be described in more detail with reference to Examples.

【0021】[0021]

【実施例】 〔実施例1〕250mm×500mm×1.6mmで銅
箔厚さがそれぞれ35μmの両面ガラスエポキシ基板
(松下電工(株)製;R1766)の両面に所定の回路
を形成した後、プリプレグ(松下電工(株)製;R16
61)を介して銅箔厚さが35μmの銅箔を両面にプレ
ス積層し、外層銅箔に所定の回路を形成し、四層基板を
作成した。前記回路基板の最外層の導体回路層の所望の
位置にドリルで直下の絶縁層に達する小孔を開け、該小
孔の底部にCO2 レーザーをあてることで、最外層の導
体回路層から内層の導体回路層に達する小孔を設けた。
この小孔の底面に相当する導体回路層の表面を深さ5μ
m迄エッチングした後、小孔の空隙部に半田を充填し内
層回路と外層回路を電気的に接続して多層回路基板を作
製した。この多層回路基板についてバイアホールの信頼
性とその生産性を以下に示す方法で調べた。これらの結
果を表1に示した。
Example 1 After forming a predetermined circuit on both sides of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; 250 mm × 500 mm × 1.6 mm, each having a copper foil thickness of 35 μm), Prepreg (Matsushita Electric Works, Ltd .; R16
61), a copper foil having a thickness of 35 μm was press-laminated on both sides to form a predetermined circuit on the outer copper foil, thereby producing a four-layer board. I drilled a small hole reaching the insulating layer immediately below a drill in a desired position of the outermost layer of the conductor circuit layer of the circuit board, by applying a CO 2 laser at the bottom of the small hole, the inner layer from the outermost conductor circuit layer A small hole reaching the conductor circuit layer was provided.
The surface of the conductor circuit layer corresponding to the bottom surface of the small hole has a depth of 5 μm.
After etching to a depth of m, solder was filled into the voids of the small holes, and the inner layer circuit and the outer layer circuit were electrically connected to produce a multilayer circuit board. The reliability of the via holes and the productivity of the multilayer circuit board were examined by the following methods. The results are shown in Table 1.

【0022】<半田濡れ性の評価方法>多層回路基板に
プリフラックスを塗布後、260℃の半田バス中に浸漬
した時、小孔の底面に相当する大きさの銅箔表面の半田
被覆面積率で評価した。
<Evaluation Method of Solder Wettability> When a pre-flux was applied to a multilayer circuit board and immersed in a solder bath at 260 ° C., the solder coating area ratio of the copper foil surface having a size corresponding to the bottom surface of the small hole was measured. Was evaluated.

【0023】<バイアホール部の信頼性の評価方法>J
IS C 5012に規定された熱衝撃(高温浸漬)試
験の方法に従い、基板に100サイクルの熱衝撃を加え
た後の導体抵抗の初期値に対する変化率により評価し
た。
<Method of Evaluating Reliability of Via Hole> J
In accordance with the thermal shock (high temperature immersion) test method specified in IS C 5012, the evaluation was made based on the rate of change of the conductor resistance to the initial value after 100 cycles of thermal shock was applied to the substrate.

【0024】<生産性の評価方法>名刺サイズ(90m
m×50mm)の基板10,000枚を製造するのに要
した時間で評価した。
<Productivity Evaluation Method> Business card size (90 m
The evaluation was based on the time required to manufacture 10,000 substrates (m × 50 mm).

【0025】[0025]

【表1】 [Table 1]

【0026】〔実施例2〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、四層基板を作成した。次
に、最外層の銅箔のバイアホールとなる部位をエッチン
グにより除去し小孔を形成した後、CO2 レーザーを用
いて前記小孔の底部より内層の導体回路層に達する小孔
とした。前記小孔の底面を形成する銅箔表面を深さ5μ
m迄エッチングした後、20μmの厚さで銅メッキする
ことで内層回路と最外層回路とを電気的に接続した。こ
のものの最外層銅箔に所定の回路を形成し、多層回路基
板を形成した。この多層回路基板のバイアホール部の信
頼性と生産性とを表1に示した。
Example 2 250 mm × 500 mm ×
After a predetermined circuit is formed on both sides of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 35 μm and a thickness of 1.6 mm, a prepreg (R1661, manufactured by Matsushita Electric Works, Ltd.) is interposed. Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a four-layer board. Next, a portion to be a via hole of the outermost copper foil was removed by etching to form a small hole, and then a small hole reaching the inner conductive circuit layer from the bottom of the small hole was formed using a CO 2 laser using a CO 2 laser. The copper foil surface forming the bottom surface of the small hole has a depth of 5 μm.
After etching to a depth of 20 m, the inner layer circuit and the outermost layer circuit were electrically connected by copper plating with a thickness of 20 μm. A predetermined circuit was formed on the outermost copper foil of this, and a multilayer circuit board was formed. Table 1 shows the reliability and productivity of the via holes of this multilayer circuit board.

【0027】〔実施例3〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、四層基板を作成した。この
ものの外層銅箔に所定の回路を形成した後、前記回路の
所望の位置にエッチングで小孔を形成し、前記小孔の底
部よりCO2 レーザーを用いて内層の導体回路層に達す
る小孔とした。この小孔の底面を形成している銅箔表面
を深さ3μm迄エッチングした後、小孔の空隙部に半田
を充填し内層回路と外層回路を電気的に接続して、多層
回路基板を形成した。この多層回路基板のバイアホール
部の信頼性と生産性とを表1に示した。
Example 3 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm. Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a four-layer board. After forming a predetermined circuit on the outer layer copper foil, a small hole is formed at a desired position of the circuit by etching, and a small hole reaching the inner conductor circuit layer from the bottom of the small hole using a CO 2 laser. And After etching the surface of the copper foil forming the bottom surface of the small hole to a depth of 3 μm, the gap portion of the small hole is filled with solder, and the inner layer circuit and the outer layer circuit are electrically connected to form a multilayer circuit board. did. Table 1 shows the reliability and productivity of the via holes of this multilayer circuit board.

【0028】〔実施例4〕250mm×500mm×
1.6mmで銅箔厚さがそれぞれ35μmの両面ガラス
エポキシ基板(松下電工(株)製;R1766)の両面
に所定の回路を形成した後、プリプレグ(松下電工
(株)製;R1661)を介して銅箔厚さが35μmの
銅箔を両面にプレス積層し、四層基板を作成した。次
に、最外層銅箔に所定の回路を形成した後、最外層銅箔
の所望の位置をエッチングして小孔を開け、該小孔の底
部にCO2 レーザーを照射して内層の導体回路層に達す
る小孔とした。前記小孔の底面を形成する銅箔表面を過
マンガン酸カリ溶液で80℃10分間の条件で洗浄した
後、小孔の空隙部に半田を充填し内層回路と最外層回路
とを電気的に接続して、多層回路基板を作製した。この
多層回路基板のバイアホール部の信頼性と生産性を表1
に示した。
Example 4 250 mm × 500 mm ×
A predetermined circuit is formed on both surfaces of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; R1766, manufactured by Matsushita Electric Works, Ltd.) having a thickness of 1.6 mm and a copper foil thickness of 35 μm. Then, a copper foil having a thickness of 35 μm was press-laminated on both sides to form a four-layer board. Next, after a predetermined circuit is formed on the outermost copper foil, a desired position of the outermost copper foil is etched to form a small hole, and the bottom of the small hole is irradiated with a CO 2 laser to form a conductor circuit in the inner layer. The pores reached the layer. After cleaning the surface of the copper foil forming the bottom surface of the small hole with a potassium permanganate solution at 80 ° C. for 10 minutes, the void portion of the small hole is filled with solder to electrically connect the inner layer circuit and the outermost layer circuit. By connecting, a multilayer circuit board was produced. Table 1 shows the reliability and productivity of via holes in this multilayer circuit board.
It was shown to.

【0029】〔比較例〕250mm×500mm×1.
6mmで銅箔厚さがそれぞれ35μmの両面ガラスエポ
キシ基板(松下電工(株)製;R1766)の両面に所
定の回路を形成した後、プリプレグ(松下電工(株)
製;R1661)を介して銅箔厚さが35μmの銅箔を
両面にプレス積層し、四層基板を作成した。次に、最外
層銅箔に所定の回路を形成した後、前記回路の所望の位
置に絶縁層に達する小孔をドリルで開け、前記小孔の底
部にCO2 レーザーを照射することで内層の導体回路層
に達する小孔とした。小孔の空隙部に半田を充填し内層
回路と最外層回路とを電気的に接続することを図った
が、半田濡れ性が不十分であるため、接続不能であっ
た。
Comparative Example 250 mm × 500 mm × 1.
After forming a predetermined circuit on both sides of a double-sided glass epoxy substrate (R1766, manufactured by Matsushita Electric Works, Ltd .; 6 mm in thickness, 35 μm in copper foil), a prepreg (Matsushita Electric Works, Ltd.)
(R1661), a copper foil having a thickness of 35 μm was press-laminated on both sides to form a four-layer board. Next, after a predetermined circuit is formed on the outermost copper foil, a small hole reaching the insulating layer is drilled at a desired position of the circuit with a drill, and the bottom of the small hole is irradiated with a CO 2 laser to form an inner layer. The holes were small holes reaching the conductor circuit layer. Attempts were made to electrically connect the inner layer circuit and the outermost layer circuit by filling the voids of the small holes with solder, but the connection was not possible due to insufficient solder wettability.

【0030】[0030]

【発明の効果】本発明の多層回路基板は、信頼性に優れ
たバイアホールを有するので、いろいろな用途に安心し
て用いることができるし、本発明の製造方法によれば、
前記多層回路基板を生産性良く提供することができるの
で、産業上非常に有用である。
The multilayer circuit board of the present invention has a highly reliable via hole, so that it can be used in various applications without worry. According to the manufacturing method of the present invention,
Since the multilayer circuit board can be provided with high productivity, it is industrially very useful.

【図面の簡単な説明】[Brief description of the drawings]

【図1】 本発明の多層回路基板の一例を示す断面図。FIG. 1 is a sectional view showing an example of a multilayer circuit board of the present invention.

【符号の説明】[Explanation of symbols]

1 基板 2 導体回路層 3 絶縁層 4 (最外層の)導体回路層 5 バイアホール REFERENCE SIGNS LIST 1 board 2 conductive circuit layer 3 insulating layer 4 (outermost) conductive circuit layer 5 via hole

Claims (6)

【特許請求の範囲】[Claims] 【請求項1】基板の少なくとも一主面上に絶縁層を介し
て複数の導体回路層を載置し、しかも最外層の導体回路
層から最外層でない導体回路層に電気的に接続するため
の小孔を設けてなる多層回路基板であって、前記小孔の
底面の炭素濃度が6×10-8g/mm2 以下であること
を特徴とする多層回路基板。
1. A method for mounting a plurality of conductive circuit layers on at least one principal surface of a substrate via an insulating layer and electrically connecting the outermost conductive circuit layers to the non-outermost conductive circuit layers. A multilayer circuit board provided with small holes, wherein the carbon concentration at the bottom surface of the small holes is 6 × 10 −8 g / mm 2 or less.
【請求項2】前記小孔の底面が該底面を形成する最外層
でない導体回路層の表面よりも3μm以上低く基板側に
凹んでいることを特徴とする請求項1記載の多層回路基
板。
2. The multilayer circuit board according to claim 1, wherein the bottom surface of the small hole is recessed toward the substrate by at least 3 μm lower than the surface of the conductor circuit layer which is not the outermost layer forming the bottom surface.
【請求項3】基板の少なくとも一主面上に絶縁層を介し
て複数の導体回路層を載置し、前記導体回路層のうちの
最外層の導体回路層と最外層でない導体回路層とを電気
的に接続するための小孔を設けてなる多層回路基板の製
造方法であって、前記小孔を形成後、該小孔の底面をエ
ッチングし、しかる後に電気的接続することを特徴とす
る多層回路基板の製造方法。
3. A plurality of conductive circuit layers are mounted on at least one principal surface of a substrate via an insulating layer, and an outermost conductive circuit layer and a non-outermost conductive circuit layer among the conductive circuit layers are separated from each other. What is claimed is: 1. A method for manufacturing a multilayer circuit board comprising a small hole for electrical connection, comprising: after forming the small hole, etching the bottom surface of the small hole; and then electrically connecting. A method for manufacturing a multilayer circuit board.
【請求項4】小孔の底面をエッチングすることで、小孔
の底面の炭素濃度を制御することを特徴とする請求項3
記載の多層回路基板の製造方法。
4. The method according to claim 3, wherein the carbon concentration at the bottom surface of the small hole is controlled by etching the bottom surface of the small hole.
A method for manufacturing the multilayer circuit board according to the above.
【請求項5】小孔をレーザー照射により形成することを
特徴とする請求項3又は請求項4記載の多層回路基板の
製造方法。
5. The method for manufacturing a multilayer circuit board according to claim 3, wherein the small holes are formed by laser irradiation.
【請求項6】小孔の底面を3μm以上エッチングするこ
とを特徴とする請求項3、請求項4又は請求項5記載の
多層回路基板の製造方法。
6. The method according to claim 3, wherein the bottom surface of the small hole is etched by 3 μm or more.
JP9097097A 1997-04-09 1997-04-09 Multilayered circuit board and its manufacture Pending JPH10284843A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9097097A JPH10284843A (en) 1997-04-09 1997-04-09 Multilayered circuit board and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9097097A JPH10284843A (en) 1997-04-09 1997-04-09 Multilayered circuit board and its manufacture

Publications (1)

Publication Number Publication Date
JPH10284843A true JPH10284843A (en) 1998-10-23

Family

ID=14013369

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9097097A Pending JPH10284843A (en) 1997-04-09 1997-04-09 Multilayered circuit board and its manufacture

Country Status (1)

Country Link
JP (1) JPH10284843A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252465A (en) * 2001-02-26 2002-09-06 Kyocera Corp Multilayer wiring board and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002252465A (en) * 2001-02-26 2002-09-06 Kyocera Corp Multilayer wiring board and its manufacturing method
JP4693258B2 (en) * 2001-02-26 2011-06-01 京セラ株式会社 Manufacturing method of multilayer wiring board

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