JP2003309214A - Method of manufacturing wiring board - Google Patents

Method of manufacturing wiring board

Info

Publication number
JP2003309214A
JP2003309214A JP2002115163A JP2002115163A JP2003309214A JP 2003309214 A JP2003309214 A JP 2003309214A JP 2002115163 A JP2002115163 A JP 2002115163A JP 2002115163 A JP2002115163 A JP 2002115163A JP 2003309214 A JP2003309214 A JP 2003309214A
Authority
JP
Japan
Prior art keywords
resin plate
metal layer
wiring board
manufacturing
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2002115163A
Other languages
Japanese (ja)
Inventor
Kazuki Kobayashi
和貴 小林
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Shinko Electric Industries Co Ltd
Original Assignee
Shinko Electric Industries Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Shinko Electric Industries Co Ltd filed Critical Shinko Electric Industries Co Ltd
Priority to JP2002115163A priority Critical patent/JP2003309214A/en
Publication of JP2003309214A publication Critical patent/JP2003309214A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151Die mounting substrate
    • H01L2924/153Connection portion
    • H01L2924/1531Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a wiring board which is capable of manufacturing wiring boards formed with fine vias on an industrial base. <P>SOLUTION: The wiring board 30 is formed with the vias 18 through a resin board 10, with one end of each via bonded to a wiring pattern 22 formed on one face of the resin board 10. The method of manufacturing the wiring board 30 comprises steps of: forming the vias 18 by filling the through holes 12 with metals by electrolytic plating wherein a thin metal layer 14 formed on the entire surface including inner wall faces of the through holes 12 formed through the resin board 10 used as a power supply layer; forming, on one face of the resin board 10, a metal layer 20 which is thicker than a metal layer 16 formed on the other face of the resin board 10; then, etching the metal layers 16 and 20 formed on both faces of the resin board 10 so that a prescribed thickness of the metal layer 20 is left over on one face of the resin board 10 while the metal layer 16 formed on the other face of the resin board 10 is removed; and patterning the metal layer 20 left over on one face of the resin board 10, to form the wiring pattern 22. <P>COPYRIGHT: (C)2004,JPO

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【発明の属する技術分野】本発明は配線基板の製造方法
に関し、更に詳細には樹脂板を貫通して形成されたヴィ
アの一端側が、前記樹脂板の一面側に形成された配線パ
ターンに接合されている配線基板の製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a wiring board, and more specifically, one end side of a via formed through a resin plate is joined to a wiring pattern formed on one surface side of the resin plate. Manufacturing method of the wiring board.

【0002】[0002]

【従来の技術】半導体装置等の電子機器に用いられる配
線基板としては、例えば図6に示す配線基板100があ
る。図6に示す配線基板100は、多層配線基板であっ
て、多層に積層されたパッド104を含む配線パターン
102は、絶縁層としての樹脂層106を介して積層さ
れ、配線パターン102及びパッド104は、樹脂層1
06を貫通するヴィア108を介して電気的に相互に接
続されている。図1に示す配線基板100では、その上
面側に形成されたパッド104,104・・の各々に
は、搭載される半導体素子110の電極端子が当接さ
れ、配線基板100の下面側に形成されたパッド10
4,104・・の各々には、はんだボール等の外部接続
端子112が装着される。図6に示す配線基板100
は、図7に示す様に、複数枚の樹脂基板100a,10
0b,100cを積層して形成することができる。かか
る樹脂基板100a,100b,100cの各々には、
樹脂層106の一面側又は両面側に、パッド104を含
む配線パターン108が形成されていると共に、パッド
104又は配線パターンに一端側が接合されたヴィア1
08が、樹脂層106を貫通して形成されている。
2. Description of the Related Art As a wiring board used for electronic equipment such as a semiconductor device, there is a wiring board 100 shown in FIG. 6, for example. The wiring board 100 shown in FIG. 6 is a multilayer wiring board, and the wiring pattern 102 including the pads 104 laminated in multiple layers is laminated via the resin layer 106 as an insulating layer, and the wiring pattern 102 and the pad 104 are , Resin layer 1
They are electrically connected to each other via a via 108 penetrating 06. In the wiring board 100 shown in FIG. 1, the electrode terminals of the semiconductor element 110 to be mounted are brought into contact with the pads 104, 104, ... Formed on the upper surface side thereof, and are formed on the lower surface side of the wiring board 100. Pad 10
An external connection terminal 112 such as a solder ball is attached to each of 4, 104. Wiring board 100 shown in FIG.
Is a plurality of resin boards 100a, 10 as shown in FIG.
It can be formed by stacking 0b and 100c. Each of the resin substrates 100a, 100b, 100c includes
Via 1 in which a wiring pattern 108 including a pad 104 is formed on one side or both sides of the resin layer 106 and one end side is joined to the pad 104 or the wiring pattern
08 is formed so as to penetrate the resin layer 106.

【0003】ところで、樹脂基板100a,100b,
100cの各々は、従来、図8又は図9に示す方法で製
造されている。図8に示す方法では、先ず、樹脂層10
6の一面側に銅箔116が貼着された図8(a)に示す
片面銅張板に、その他面側からレーザでヴィア穴120
を形成する[図8(b)の工程]。このヴィア穴120
の底面には、銅箔116の裏面が露出している。次い
で、銅箔116を給電層とする電解めっきによって、ヴ
ィア穴120内に銅を充填し、ヴィア108を形成する
[図8(c)の工程]。その後、銅箔116に公知の方
法でパターニングを施すことによって、所望形状のパッ
ド104を含む配線パターン108を形成できる。
By the way, the resin substrates 100a, 100b,
Each of 100c is conventionally manufactured by the method shown in FIG. 8 or FIG. In the method shown in FIG. 8, first, the resin layer 10
6 is a single-sided copper clad plate shown in FIG.
Are formed [step of FIG. 8 (b)]. This via hole 120
The back surface of the copper foil 116 is exposed on the bottom surface of the. Next, the via holes 120 are filled with copper by electrolytic plating using the copper foil 116 as a power supply layer to form the vias 108 [step of FIG. 8C]. Then, by patterning the copper foil 116 by a known method, the wiring pattern 108 including the pad 104 having a desired shape can be formed.

【0004】また、図9に示す方法では、先ず、アルミ
板200の一面側に感光性のドライフィルム202を貼
着し[図9(a)の工程]、ドライフィルム202をパ
ターニングして所定個所に凹部204,204・・を形
成する[図9(b)の工程]。この凹部204の底面に
には、アルミ板200が露出する。更に、アルミ板20
0を給電層とする電解めっきによって、凹部204内に
銅金属を充填しポスト206,206・・を形成した後
[図9(c)の工程]、ドライフィルム202を除去す
る[図9(d)の工程]。次いで、ポスト206,20
6・・が立設されたアルミ板200の一面側に、耐熱性
を有する樹脂を塗布し、樹脂層208を形成する[図9
(e)の工程]。形成した樹脂層208にポスト206,
206・・が覆われているため、樹脂層208に研磨を
施し、ポスト206,206・・の各上面を露出面とす
る[図9(f)の工程]。その後、ポスト206,20
6・・の各上面が露出する樹脂層208の露出面に、常
法によって配線パターン108を形成した後、アルミ板
200を除去することによって、図7に示す樹脂基板1
00a,100bを形成できる。
In the method shown in FIG. 9, first, a photosensitive dry film 202 is attached to one surface of the aluminum plate 200 [step of FIG. 9 (a)], and the dry film 202 is patterned to a predetermined position. .. are formed in the substrate [step of FIG. 9B]. The aluminum plate 200 is exposed on the bottom surface of the recess 204. Furthermore, aluminum plate 20
After the recesses 204 are filled with copper metal to form the posts 206, 206 ... By electrolytic plating using 0 as a power supply layer [step of FIG. 9C], the dry film 202 is removed [FIG. ) Step]. Then post 206, 20
A resin having heat resistance is applied to one surface side of the aluminum plate 200 on which 6 ...
Step (e)]. A post 206 is formed on the formed resin layer 208,
Since 206 ... Are covered, the resin layer 208 is polished to make the upper surfaces of the posts 206, 206 ... As exposed surfaces [step of FIG. 9 (f)]. Then post 206, 20
After the wiring pattern 108 is formed on the exposed surface of the resin layer 208 where the respective upper surfaces 6 and 6 are exposed by a conventional method, the aluminum plate 200 is removed to form the resin substrate 1 shown in FIG.
00a, 100b can be formed.

【0005】ところで、図7に示す樹脂基板100cの
様に、樹脂層106の両面側に配線パターン102及び
パッド104を形成する場合には、図8(c)に示す工
程の後、更に樹脂層106の他面側に無電解めっきによ
る薄銅層を形成する。次いで、銅箔116を給電層とす
る電解めっきを、樹脂層106の他面側に施し、樹脂層
106の他面側に所望厚さの銅層を形成する。その後、
樹脂層106の銅箔116及び電解めっきで形成した銅
層の各々にパターニングを施すことによって、樹脂層1
06の両面側に所望形状の配線パターン108及びパッ
ド104が形成された配線基板100cを得ることがで
きる。或いは、図9(f)に示す工程の後、ポスト20
6,206・・の各上面が露出する樹脂層208の露出
面に、常法によって配線パターン108を形成した後、
アルミ板200を除去する。次いで、樹脂層208のア
ルミ板200を除去した除去面に、無電解めっきによる
薄銅層を形成する。更に、形成した薄銅層を給電層とす
る電解めっきを、樹脂層208の除去面側に施し、樹脂
層208の除去面側に所望厚さの銅層を形成する。その
後、樹脂層208の除去面側に形成した銅層に、パター
ニングを施すことによって、樹脂層208の両面側に所
望形状の配線パターン108及びパッド104が形成さ
れた配線基板100cを得ることができる。
By the way, when the wiring pattern 102 and the pad 104 are formed on both sides of the resin layer 106 like the resin substrate 100c shown in FIG. 7, after the step shown in FIG. A thin copper layer is formed on the other side of 106 by electroless plating. Next, electrolytic plating using the copper foil 116 as a power feeding layer is performed on the other surface side of the resin layer 106 to form a copper layer having a desired thickness on the other surface side of the resin layer 106. afterwards,
By patterning each of the copper foil 116 of the resin layer 106 and the copper layer formed by electrolytic plating, the resin layer 1
It is possible to obtain the wiring board 100c in which the wiring pattern 108 and the pad 104 having a desired shape are formed on both surface sides of 06. Alternatively, after the step shown in FIG.
After forming the wiring pattern 108 on the exposed surface of the resin layer 208 where the upper surfaces of 6, 206 ...
The aluminum plate 200 is removed. Then, a thin copper layer is formed by electroless plating on the surface of the resin layer 208 from which the aluminum plate 200 has been removed. Further, electrolytic plating using the formed thin copper layer as a power feeding layer is performed on the removal surface side of the resin layer 208, and a copper layer having a desired thickness is formed on the removal surface side of the resin layer 208. Then, the copper layer formed on the removed surface side of the resin layer 208 is patterned to obtain the wiring board 100c in which the wiring pattern 108 and the pad 104 having a desired shape are formed on both surface sides of the resin layer 208. .

【0006】[0006]

【発明が解決しようとする課題】図8又は図9に示す方
法によって得られた樹脂基板のヴィア108又はポスト
206は、樹脂板にドリルで形成した貫通孔を利用して
形成したヴィアよりも小径にできる。しかし、図8に示
す方法では、図8(a)に示す片面銅張板の他面側から
レーザを照射して形成したヴィア穴120の内壁面に
は、レーザの照射によって樹脂層106を形成する樹脂
が炭化して形成された炭化物等の異物が付着している。
このため、ヴィア穴120の内壁面に、過マンガン酸カ
リウム等のエッチング溶液による残渣除去を充分に施す
ことが必要である。かかる残渣除去が不充分の場合は、
銅箔116を給電層とする電解めっきによって、ヴィア
穴120に金属を充分に充填できないことがある。他
方、ヴィア穴120の残渣除去を充分に施すことによっ
て、電解めっきによりヴィア穴120内に金属を充分に
充填できるが、配線基板の生産性を低下させる。かかる
図8に示す方法に対し、図9に示す方法によれば、ドラ
イフィルム202を用い、レーザ等を用いることなく凹
部204を形成しているため、形成した凹部204の残
渣除去を簡単化できる。しかし、図9に示す方法では、
図8に示す方法に比較して、その工程が長く複雑であ
り、研磨工程[図9(e)]を含むため、最終的に得ら
れる配線基板の厚さを薄くすることは困難である。
The via 108 or the post 206 of the resin substrate obtained by the method shown in FIG. 8 or 9 has a smaller diameter than the via formed by using the through hole formed in the resin plate by the drill. You can However, in the method shown in FIG. 8, the resin layer 106 is formed by laser irradiation on the inner wall surface of the via hole 120 formed by irradiating the laser from the other surface side of the single-sided copper clad plate shown in FIG. 8A. Foreign substances such as carbides formed by carbonizing the resin are attached.
Therefore, it is necessary to sufficiently remove the residue on the inner wall surface of the via hole 120 with an etching solution such as potassium permanganate. If such residue removal is insufficient,
Electrolytic plating using the copper foil 116 as a power supply layer may not sufficiently fill the via hole 120 with metal. On the other hand, by sufficiently removing the residue in the via hole 120, the metal can be sufficiently filled in the via hole 120 by electrolytic plating, but this reduces the productivity of the wiring board. In contrast to the method shown in FIG. 8, according to the method shown in FIG. 9, since the recesses 204 are formed using the dry film 202 without using a laser or the like, it is possible to easily remove the residue of the formed recesses 204. . However, in the method shown in FIG.
Compared with the method shown in FIG. 8, the process is long and complicated, and includes a polishing process [FIG. 9 (e)], so that it is difficult to reduce the thickness of the finally obtained wiring board.

【0007】また、図8及び図9に示す方法では、ヴィ
ア穴120又は凹部204に電解めっきで金属を充填す
る際に、ヴィア穴120又は凹部204へのめっき液の
循環速度(金属イオンの循環速度)は、ヴィア穴120
又は凹部204の開口径が小径となるほど低下し、ヴィ
ア穴120又は凹部204内への金属充填速度が遅くな
る。このため、ヴィア穴120又は凹部204内への金
属充填速度の観点から、形成できるヴィア穴120又は
凹部204の開口径に限界が生じ、形成できるヴィア1
08の径には限界が存在する。一方、近年、配線基板に
おいても、配線パターン等の高密度化が進展しており、
微細なヴィアの工業的な製造方法の提案が要望されてい
る。そこで、本発明の課題は、微細なヴィアが形成され
た配線基板を工業的に生産し得る配線基板の製造方法を
提供することにある。
Further, in the method shown in FIGS. 8 and 9, when the via hole 120 or the recess 204 is filled with metal by electrolytic plating, the circulation speed of the plating solution to the via hole 120 or the recess 204 (circulation of metal ions) Speed) is via hole 120
Alternatively, the smaller the opening diameter of the concave portion 204 is, the smaller it is, and the metal filling speed into the via hole 120 or the concave portion 204 becomes slower. Therefore, from the viewpoint of the metal filling speed into the via hole 120 or the concave portion 204, there is a limit to the opening diameter of the via hole 120 or the concave portion 204 that can be formed.
There is a limit to the diameter of 08. On the other hand, in recent years, the density of wiring patterns has been increasing in wiring boards as well.
It is desired to propose an industrial manufacturing method for fine vias. Then, the subject of this invention is providing the manufacturing method of the wiring board which can industrially produce the wiring board in which the fine via was formed.

【0008】[0008]

【課題を解決するための手段】本発明者は、前記課題を
解決すべく検討した結果、レーザによって樹脂板を貫通
して形成した貫通孔は、その内壁面等の汚れが、レーザ
によって形成したヴィア穴120に比較して極めて少な
いこと、及び貫通孔内に電解めっきを施す際に、貫通孔
内のめっき液を容易に更新できることを見出し、本発明
に到達した。すなわち、本発明は、樹脂板を貫通して形
成されたヴィアの一端側が、前記樹脂板の一面側に形成
された配線パターンに接合されている配線基板を製造す
る際に、該樹脂板を貫通する貫通孔の内壁面を含む全表
面に形成した薄金属層を給電層とする電解めっきによっ
て、前記貫通孔を金属により充填してヴィアを形成する
と共に、前記樹脂板の一面側に、前記樹脂板の他面側に
形成した金属層よりも厚い金属層を形成し、次いで、前
記樹脂板の他面側に形成した金属層が除去されたとき、
前記樹脂板の一面側に所定の厚さの金属層が残存するよ
うに、前記樹脂板の両面側に形成した金属層にエッチン
グを施した後、前記樹脂板の一面側に残存した金属層に
パターニングを施し、配線パターンを形成することを特
徴とする配線基板の製造方法にある。
Means for Solving the Problems As a result of studies to solve the above-mentioned problems, the present inventor has found that a through hole formed by penetrating a resin plate by a laser has a stain formed on the inner wall surface by the laser. The inventors have found that the number is extremely smaller than that of the via holes 120, and that the plating solution in the through holes can be easily updated when electrolytic plating is performed in the through holes, and thus the present invention has been reached. That is, according to the present invention, when manufacturing a wiring board in which one end side of a via formed through a resin plate is joined to a wiring pattern formed on one surface side of the resin plate, the via is penetrated through the resin plate. By filling the through hole with metal to form a via by electrolytic plating using a thin metal layer formed on the entire surface including the inner wall surface of the through hole as a power supply layer, the resin is provided on one surface side of the resin plate. Forming a metal layer thicker than the metal layer formed on the other side of the plate, and then removing the metal layer formed on the other side of the resin plate,
After etching the metal layers formed on both sides of the resin plate so that a metal layer having a predetermined thickness remains on the one side of the resin plate, the metal layer remaining on the one side of the resin plate A method of manufacturing a wiring board is characterized by forming a wiring pattern by patterning.

【0009】かかる本発明において、貫通孔をレーザに
よって形成することにより、最終的に微細なヴィアを形
成でき、薄金属層を無電解めっきで形成することによ
り、微細な貫通孔の内壁面にも薄金属層を形成できる。
この薄金属層を給電層とする電解めっきを、樹脂板の一
面側の電流密度が他面側の電流密度よりも高くして行う
ことによって、樹脂板の一面側と他面側とで厚さの異な
る金属層を一工程で形成できる。また、樹脂板の他面側
に露出するヴィアの他端側に、はんだや導電性ペースト
等のろう材から成る接合部を形成することによって、ヴ
ィアを多層に積層してスタックドヴィアを容易に形成で
きる。或いは、樹脂板の他面側に露出するヴィアの他端
側に、はんだボール等のろう材から成る接続端子を形成
することによって、実装基板等への実装を容易にでき
る。更に、樹脂板の一面側に配線パターンが形成されて
いると共に、前記樹脂板を貫通するヴィアが形成された
複数枚の樹脂基板を、多層に積層された配線パターンが
ヴィアで電気的に相互に接続されるように積層すること
によって、多層の配線基板を容易に得ることができる。
In the present invention, by forming the through holes with a laser, fine vias can be finally formed, and by forming the thin metal layer by electroless plating, the inner wall surface of the fine through holes can also be formed. A thin metal layer can be formed.
By performing electrolytic plating using this thin metal layer as a power supply layer with the current density on one side of the resin plate higher than the current density on the other side, the thickness of the resin plate on one side and the other side can be increased. Different metal layers can be formed in one step. Also, by forming a joint portion made of a brazing material such as solder or conductive paste on the other end side of the via exposed on the other surface side of the resin plate, the vias can be laminated in multiple layers to facilitate stacked vias. Can be formed. Alternatively, mounting on a mounting substrate or the like can be facilitated by forming a connection terminal made of a brazing material such as a solder ball on the other end side of the via exposed on the other surface side of the resin plate. Further, a wiring pattern is formed on one surface side of the resin plate, and a plurality of resin substrates having vias penetrating through the resin plate are electrically connected to each other by the wiring patterns laminated in multiple layers. By stacking so as to be connected, a multilayer wiring board can be easily obtained.

【0010】本発明においては、樹脂板を貫通して形成
した貫通孔を利用してヴィアを形成する。かかる貫通孔
を樹脂板の一面側から他面側に貫通した際に、貫通孔の
形成中に発生した削りカス等が、樹脂板の他面側に吹出
すため、貫通孔内に残留する削りカス等の残留量を、削
りカス等が残留し易い凹部であるヴィア穴120に比較
して極めて少なくでき、貫通孔内の残渣除去を簡単化で
きる。また、貫通孔内に電解めっきによって金属を充填
してヴィアを形成する際に、貫通孔に対しては、凹部に
比較してめっき液の液回りがよく、貫通孔内のめっき液
は、凹部内のめっき液に比較して容易に更新されるた
め、凹部の開口径よりも小径の貫通孔であっても金属を
充填でき、微細なヴィアを形成できる。しかも、この際
に、貫通孔の全内壁面に金属層が形成されるため、貫通
孔内を金属で充填して成るヴィアを従来よりも短時間で
形成でき、貫通孔内の残渣除去の簡単化と相俟って配線
基板の生産性を向上できる。
In the present invention, the via is formed by utilizing the through hole formed through the resin plate. When the through hole is penetrated from one surface side to the other surface side of the resin plate, shavings generated during the formation of the through hole are blown to the other surface side of the resin plate. The residual amount of dust and the like can be made extremely smaller than that of the via hole 120, which is a recess where shavings and the like tend to remain, and the removal of the residue in the through hole can be simplified. Further, when forming a via by filling a metal into the through-hole by electrolytic plating, the plating solution in the through-hole has better liquid flow compared to the recess, and the plating solution in the through-hole is Since it is easily renewed as compared with the plating solution in the inside, even a through hole having a diameter smaller than the opening diameter of the recess can be filled with metal and fine vias can be formed. Moreover, at this time, since the metal layer is formed on the entire inner wall surface of the through hole, the via formed by filling the inside of the through hole with metal can be formed in a shorter time than before, and removal of residues in the through hole is easy. The productivity of the wiring board can be improved in combination with the realization.

【0011】[0011]

【発明の実施の形態】本発明に係る配線基板の製造方法
の一例を図1に示す。先ず、樹脂板10に貫通孔12,
12・・を形成する[図1(a)(b)の工程]。この
樹脂板10としては、配線基板に用いられている樹脂
板、例えばエポキシ樹脂やポリイミド樹脂から成る樹脂
板を用いることができる。かかる樹脂板10が、熱硬化
性樹脂によって形成されている場合には、樹脂板10の
形状が保持できる程度に半硬化させた樹脂板も用いるこ
とができる。また、樹脂板10としては、ガラスクロス
等の絶縁性材料から成る補強材で補強された樹脂板を好
適に使用できる。この様な、樹脂板10に貫通孔12を
形成するには、公知の方法を採用できるが、レーザによ
って貫通孔12を形成することが、直径が30μm程度
の微細な貫通孔12を成できるため好ましい。ところ
で、レーザで貫通孔12を形成する際には、図8(b)
に示す如く、ヴィア穴120を形成する場合よりもレー
ザ出力を高出力に設定でき、レーザの照射によって樹脂
板10を形成する樹脂が炭化して形成された炭化物等の
異物は、貫通孔12が形成された際に、貫通孔12から
吹出すため、貫通孔12の内壁面等に付着する異物を極
めて少量とすることができる。このため、形成された貫
通孔12の内壁面等に付着する異物を、過マンガン酸カ
リウム等のエッチング溶液による除去(残渣除去)を、
図8に示す方法の場合ほど充分に行うことを要しない
が、簡単な残渣除去を施すことが好ましい。
FIG. 1 shows an example of a method of manufacturing a wiring board according to the present invention. First, the resin plate 10 has through holes 12,
12 ... are formed [steps of FIGS. 1 (a) and 1 (b)]. As the resin plate 10, a resin plate used for a wiring board, for example, a resin plate made of epoxy resin or polyimide resin can be used. When the resin plate 10 is formed of a thermosetting resin, a resin plate semi-cured to the extent that the shape of the resin plate 10 can be retained can be used. As the resin plate 10, a resin plate reinforced with a reinforcing material made of an insulating material such as glass cloth can be preferably used. A known method can be used to form the through holes 12 in the resin plate 10 as described above. However, forming the through holes 12 by a laser can form fine through holes 12 having a diameter of about 30 μm. preferable. By the way, when forming the through hole 12 with a laser, as shown in FIG.
As shown in FIG. 5, the laser output can be set to a higher output than in the case where the via hole 120 is formed, and foreign matter such as a carbide formed by carbonizing the resin forming the resin plate 10 by laser irradiation is generated in the through hole 12. When formed, it blows out from the through hole 12, so that the amount of foreign matter adhering to the inner wall surface of the through hole 12 can be made extremely small. Therefore, the foreign matter attached to the inner wall surface or the like of the formed through hole 12 is removed (residue removal) by an etching solution such as potassium permanganate.
Although it does not need to be performed sufficiently as in the case of the method shown in FIG. 8, it is preferable to perform simple residue removal.

【0012】貫通孔12,12・・を形成した樹脂板1
0には、各貫通孔12の内壁面を含む樹脂板10の全表
面に無電解めっきによって、薄金属層14を形成する
[図1(c)の工程]。この薄金属層14としては、銅
から成る薄金属層とすることが好ましい。次いで、薄金
属層14を給電層とする電解めっきによって、薄金属層
14の全表面に金属層16を形成し、貫通孔12を金属
で充填してヴィア18を形成する[図1(d)の工
程]。この様に、貫通孔12の内壁面全周に形成した薄
金属層14を給電層とする電解めっきによれば、図8
(b)のヴィア穴120又は図9(b)の凹部204に
電解めっきで金属を充填する場合の如く、ヴィア穴12
0又は凹部204の底面に露出する銅箔116又はアル
ミ板200から順次金属を充填する場合に比較して、金
属の充填速度を極めて速くできる。かかる金属層16と
しては、薄金属層14と同一金属とすることが好まし
く、特に、銅から成る金属層とすることが好ましい。こ
の電解めっきの際に、樹脂板10を浸漬しためっき液を
充分に攪拌することが好ましい。攪拌によって、貫通孔
12のめっき液の更新を迅速に行うことができ、貫通孔
12内の金属の充填速度を向上できる。
Resin plate 1 having through holes 12, 12 ...
For 0, the thin metal layer 14 is formed on the entire surface of the resin plate 10 including the inner wall surface of each through hole 12 by electroless plating [step of FIG. 1 (c)]. The thin metal layer 14 is preferably a thin metal layer made of copper. Then, a metal layer 16 is formed on the entire surface of the thin metal layer 14 by electrolytic plating using the thin metal layer 14 as a power feeding layer, and the through holes 12 are filled with metal to form vias 18 (FIG. 1D). Process]. As described above, according to the electrolytic plating in which the thin metal layer 14 formed on the entire inner wall surface of the through hole 12 is used as the power feeding layer, the electrolytic plating shown in FIG.
As in the case of filling the via hole 120 of FIG. 9B or the recess 204 of FIG. 9B with metal by electrolytic plating, the via hole 12
The filling speed of the metal can be made extremely high as compared with the case where the metal is sequentially filled from the copper foil 116 exposed on the bottom surface of the concave portion 204 or the aluminum plate 200. The metal layer 16 is preferably made of the same metal as the thin metal layer 14, and particularly preferably made of copper. At the time of this electrolytic plating, it is preferable to sufficiently stir the plating solution in which the resin plate 10 is immersed. By stirring, the plating solution in the through hole 12 can be quickly updated, and the filling speed of the metal in the through hole 12 can be improved.

【0013】貫通孔12を金属で充填してヴィア18を
形成した後、樹脂板10の一面側のみに電解めっきを施
す[図1(e)の工程]。かかる片側電解めっきによっ
て、樹脂板10の一面側に形成された金属層20を、樹
脂板10の他面側に形成された金属層16よりも厚く形
成できる。この様に、樹脂板10の両面側に形成した金
属層20,16に、硫酸、塩酸、過酸化水素、蟻酸、塩
化第二銅及び塩化第二鉄のうち、少なくとも一種を含む
エッチングを施し、金属層16を除去して樹脂板10の
他面側を露出する[図1(f)の工程]。このエッチン
グの際に、樹脂板10の一面側に形成された金属層20
にもエッチングが施されるが、金属層20は金属層16
よりも厚いため、金属層16が除去されて樹脂板10の
他面側が露出したとき、金属層20は樹脂層10の一面
側に厚さを減らして残留している。
After filling the through holes 12 with metal to form the vias 18, electrolytic plating is applied only to one surface side of the resin plate 10 [step of FIG. 1 (e)]. By such one-sided electroplating, the metal layer 20 formed on one surface side of the resin plate 10 can be formed thicker than the metal layer 16 formed on the other surface side of the resin plate 10. Thus, the metal layers 20 and 16 formed on both sides of the resin plate 10 are subjected to etching containing at least one of sulfuric acid, hydrochloric acid, hydrogen peroxide, formic acid, cupric chloride and ferric chloride, The metal layer 16 is removed to expose the other surface side of the resin plate 10 [step of FIG. 1 (f)]. During this etching, the metal layer 20 formed on the one surface side of the resin plate 10
Although the metal layer 20 is also etched,
Since the metal layer 16 is thicker than the above, when the metal layer 16 is removed and the other surface side of the resin plate 10 is exposed, the metal layer 20 remains on the one surface side of the resin layer 10 with a reduced thickness.

【0014】その後、樹脂層10の一面側に残留してい
る金属層20にパターニングを施すことにより、樹脂層
10の一面側に、ヴィア18,18・・に接続されてい
る配線パターン22,22・・を形成することによっ
て、配線基板30を得ることができる[図1(g)の工
程]。この工程で採用するパターニングとしては、公知
の方法を採用できる。例えば、金属層20上に感光性の
レジストを塗布して形成したレジスト層に感光・現像を
施し、形成する配線パターンに倣ってレジスト層を残留
する。次いで、残留したレジスト層をマスクにして金属
層20にエッチングを施すことによって、所望パターン
の配線パターン22,22・・を形成できる。この様に
して得られた複数枚の配線基板30,30・・を積層す
ることによって、図6に示す多層配線基板を得ることが
できる。
Thereafter, by patterning the metal layer 20 remaining on the one surface side of the resin layer 10, the wiring patterns 22, 22 connected to the vias 18, 18, ... On the one surface side of the resin layer 10. By forming .., the wiring board 30 can be obtained [step of FIG. 1 (g)]. As a patterning adopted in this step, a known method can be adopted. For example, a resist layer formed by applying a photosensitive resist on the metal layer 20 is exposed to light and developed, and the resist layer is left according to the wiring pattern to be formed. Then, by etching the metal layer 20 using the remaining resist layer as a mask, the wiring patterns 22, 22 ... Of a desired pattern can be formed. By laminating the plurality of wiring boards 30, 30 ... Obtained in this way, the multilayer wiring board shown in FIG. 6 can be obtained.

【0015】ところで、図1(g)の工程を通過して得
られた配線基板30は、樹脂板10の一面側に配線パタ
ーン22,22・・が形成されているものであるが、多
層配線基板を形成する際には、樹脂板10の両面側に配
線パターン10等が形成された配線基板も用いられるこ
とがある。この様な、樹脂板10の両面側に配線パター
ン10等が形成された配線基板は、図1(d)に示す工
程において、電解めっきによって樹脂板10の両面側に
所定厚さの金属層16,16を形成した後、各金属層1
6にパターニングを施すことによって得ることができ
る。
By the way, the wiring board 30 obtained by passing through the process of FIG. 1 (g) has wiring patterns 22, 22 ... Formed on one surface side of the resin plate 10. When forming the substrate, a wiring substrate having the wiring pattern 10 and the like formed on both sides of the resin plate 10 may be used. Such a wiring board in which the wiring patterns 10 and the like are formed on both sides of the resin plate 10 has a metal layer 16 of a predetermined thickness on both sides of the resin plate 10 by electrolytic plating in the step shown in FIG. , 16 and then each metal layer 1
It can be obtained by patterning 6.

【0016】また、複数枚の配線基板30を積層して多
層配線基板を形成する際に、ヴィア18と他の配線基板
30に形成された配線パターン22との接合を良好にす
べく、図1(f)の工程での金属層16のエッチングに
よる除去によって、樹脂板10の他面側に露出するヴィ
ア18の他端側に、はんだや導電性ペースト等のろう材
から成る接合部24を形成することが好ましい[図1
(h)の工程]。この際に、ヴィア18を形成する金属
と接合部24を形成する金属とのマイグレーションを防
止すべく、ヴィア18の他端面にニッケル等のバリア層
をめっき等によって形成した後、はんだや導電性ペース
ト等のろう材から成る接合部24を形成することも好ま
しい。図1(h)の工程を通過して得られた複数枚の配
線基板30,30・・を多層に積層する際には、ヴィア
18と配線パターン22とを確実に接合できるため、図
2に示す様に、複数個のヴィア18,18・・が直列状
に積層されたスタックヴィアが形成された多層配線基板
を容易に形成できる。
Further, when a plurality of wiring boards 30 are laminated to form a multi-layer wiring board, the via 18 and the wiring pattern 22 formed on another wiring board 30 are joined together in a favorable manner as shown in FIG. By removing the metal layer 16 by etching in the step (f), a joint portion 24 made of a brazing material such as solder or conductive paste is formed on the other end side of the via 18 exposed on the other surface side of the resin plate 10. It is preferable that [Fig. 1
Step (h)]. At this time, in order to prevent migration of the metal forming the via 18 and the metal forming the joint portion 24, a barrier layer such as nickel is formed on the other end surface of the via 18 by plating or the like, and then solder or a conductive paste is formed. It is also preferable to form the joint portion 24 made of a brazing material such as. When a plurality of wiring boards 30, 30 ... Obtained through the step of FIG. 1 (h) are laminated in multiple layers, the via 18 and the wiring pattern 22 can be reliably joined together. As shown, it is possible to easily form a multilayer wiring board in which a stacked via in which a plurality of vias 18, 18, ... Are laminated in series is formed.

【0017】図1(g)に示す工程を通過して得られた
配線基板30は、図3に示す様に、単層配線基板40と
しても使用できる。図3に示す単層配線基板40は、樹
脂板10の一面側に形成された配線パターン22,22
・・に、他の電子部品の端子が当接されるパッドが形成
され、樹脂板10の他面側に露出するヴィア18,18
・・の各端面に、はんだボール等の外部接続端子28,
28・・が装着されている。かかる単層配線基板40で
は、樹脂板10の一面側が、他の電子部品の端子と接続
される配線パターン22,22・・の各パッドを除き保
護レジスト26で被覆されていると共に、樹脂板10の
他面側も、外部接続端子28,28・・の部分を除き保
護レジスト26で被覆されている。
The wiring board 30 obtained by passing through the steps shown in FIG. 1G can also be used as a single-layer wiring board 40 as shown in FIG. The single-layer wiring board 40 shown in FIG. 3 has wiring patterns 22, 22 formed on one surface side of the resin plate 10.
··· Vias 18, 18 on which pads for contacting terminals of other electronic parts are formed and exposed on the other surface side of the resin plate 10
..External connection terminals 28 such as solder balls on each end face
28 ... is attached. In the single-layer wiring board 40, one surface side of the resin plate 10 is covered with the protective resist 26 except for the pads of the wiring patterns 22, 22 ... Connected to the terminals of other electronic components, and the resin plate 10 is also covered. The other surface side is also covered with the protective resist 26 except for the external connection terminals 28, 28 ,.

【0018】また、図1(g)に示す工程を通過して得
られた配線基板30は、図4に示す様に、半導体装置用
の配線基板50としても使用できる。図4に示す半導体
装置用の配線基板50には、樹脂板10の一面側に形成
された配線パターン22,22・・の各パッドは、はん
だボール等の外部接続端子28,28・・が装着される
外部接続端子用パッドに用いられる。この樹脂板10の
一面側は、外部接続端子用パッドを除き保護レジスト2
6で被覆されている。更に、樹脂板10の他面側に露出
するヴィア18,18・・の各端面には、はんだ等のろ
う材から成るバンプ34,34・・が形成され、搭載さ
れる半導体素子32の電極端子が接合される。尚、搭載
された半導体素子32と樹脂板10の他面側との間隙に
は、アンダーフィル材等のシール樹脂36によってシー
ルされている。
The wiring board 30 obtained through the process shown in FIG. 1G can also be used as a wiring board 50 for a semiconductor device, as shown in FIG. On the wiring board 50 for the semiconductor device shown in FIG. 4, the external connection terminals 28, 28, ..., such as solder balls, are mounted on the pads of the wiring patterns 22, 22 ,. It is used as a pad for external connection terminals. The one surface of the resin plate 10 has a protective resist 2 except for pads for external connection terminals.
It is covered with 6. Further, bumps 34, 34, ... Made of a brazing material such as solder are formed on each end surface of the vias 18, 18 exposed on the other surface side of the resin plate 10, and electrode terminals of the semiconductor element 32 to be mounted are formed. Are joined. The gap between the mounted semiconductor element 32 and the other surface of the resin plate 10 is sealed with a sealing resin 36 such as an underfill material.

【0019】ところで、図1に示す工程では、貫通孔1
2を金属で充填してヴィア18を形成する工程[図1
(d)の工程]と、樹脂板10の一面側のみに電解めっ
きを施片面電解めっきによって、樹脂板10の一面側に
他面側に形成した金属層16よりも厚い金属層20を形
成する工程[図1(e)の工程]とを二工程に分けてい
た。しかし、この二工程を、図5に示す様に、樹脂板の
一面側の電流密度が他面側の電流密度よりも高くなるよ
うに、前記樹脂板の一面側及び他面側の各々に流す電流
値を制御して行う電解めっきによって、同一電解めっき
浴中で一工程で施すことができる。先ず、図5(a)に
示す様に、二個の電源装置として、電源1及び電源2を
用い、電解めっき槽40の電解めっき液42内に、電源
1及び電源2の各陽極に接続され陽極電極としての銅電
極板44a,44bを浸漬する。この銅電極板44a,
44bの間には、形成された貫通孔12,12・・の内
壁面を含む全表面に銅から成る金属層14が形成された
樹脂板10が配設され、薄金属層14を電源1及び電源
2の各陰極に接続されている。銅電極板44a,44b
と樹脂板10との間隔は、樹脂板10の両面側で等しい
距離としている。
By the way, in the process shown in FIG.
Filling 2 with metal to form via 18 [Fig. 1
Step (d)] and electrolytic plating is performed only on one surface side of the resin plate 10 to form a metal layer 20 thicker than the metal layer 16 formed on the other surface side on the one surface side of the resin plate 10 by single-sided electrolytic plating. The process [the process of FIG. 1 (e)] was divided into two processes. However, as shown in FIG. 5, these two steps are applied to each of the one surface side and the other surface side of the resin plate so that the current density on one surface side of the resin plate is higher than the current density on the other surface side. The electrolytic plating performed by controlling the electric current value can be performed in one step in the same electrolytic plating bath. First, as shown in FIG. 5 (a), a power source 1 and a power source 2 are used as two power source devices and are connected to respective anodes of the power source 1 and the power source 2 in the electrolytic plating solution 42 of the electrolytic plating tank 40. The copper electrode plates 44a and 44b as the anode electrodes are immersed. This copper electrode plate 44a,
A resin plate 10 having a metal layer 14 made of copper formed on the entire surface including the inner wall surfaces of the formed through holes 12, 12 ... Is disposed between the 44b, and the thin metal layer 14 is connected to the power source 1 and It is connected to each cathode of the power supply 2. Copper electrode plates 44a, 44b
The distance between the resin plate 10 and the resin plate 10 is equal on both sides of the resin plate 10.

【0020】図5(a)では、電源1の陽極と陰極との
間に流す電流値を、電源2の陽極と陰極との間に流す電
流値よりも大として電解銅めっきを開始する。この様
に、樹脂板10の一面側に流す電流値を、他面側に流す
電流値よりも大とするように、電源1と電源2とを制御
することによって、樹脂板10の一面側の電流密度を、
樹脂板10の他面側の電流密度よりも高くできる。かか
る電流密度差を維持しつつ電解銅めっきを施すことによ
って、図5(b)に示す様に、樹脂板10を貫通する貫
通孔12,12・・を銅金属で充填してヴィア18,1
8・・を形成し且つ電流密度が高い樹脂板10の一面側
に、他面側に形成した金属層16よりも厚い金属層20
を形成できる。
In FIG. 5 (a), electrolytic copper plating is started with the value of the current flowing between the anode and the cathode of the power source 1 being larger than the value of the current flowing between the anode and the cathode of the power source 2. In this way, by controlling the power source 1 and the power source 2 so that the value of the current flowing on one side of the resin plate 10 is larger than the value of the current flowing on the other side, the one side of the resin plate 10 Current density,
The current density on the other surface side of the resin plate 10 can be made higher. By performing electrolytic copper plating while maintaining such a current density difference, as shown in FIG. 5B, the through holes 12, 12 ... Penetrating the resin plate 10 are filled with copper metal and the vias 18, 1 are formed.
A metal layer 20 that is thicker than the metal layer 16 that is formed on one surface side of the resin plate 10 that has a high current density.
Can be formed.

【0021】図5(a)(b)では、電源1及び電源2
を用い、電源1の陽極と陰極との間に流す電流値を、電
源2の陽極と陰極との間に流す電流値よりも大として電
解銅めっきを施しているが、1個の電源を用い電解めっ
きしても、樹脂板10の一面側の電流密度を、樹脂板1
0の他面側の電流密度よりも高くできる。つまり、単一
の電源の陽極に接続された銅電極板44a,44bと、
同一の電源の陰極に接続された薄金属層14で全面が覆
われた樹脂板10との間隙を相違すること、例えば銅電
極44aと樹脂板10の一面側との間隔を、銅電極44
bと樹脂板10の他面側との間隔よりも狭くすることに
よって、樹脂板10の一面側の電流密度を、樹脂板10
の他面側の電流密度よりも高くできる。その結果、樹脂
板10の一面側に他面側に形成した金属層16よりも厚
い金属層20を一工程で形成できる
In FIGS. 5A and 5B, the power source 1 and the power source 2
, And the electrolytic copper plating is performed so that the current value flowing between the anode and the cathode of the power source 1 is larger than the current value flowing between the anode and the cathode of the power source 2, but one power source is used. Even with electrolytic plating, the current density on one side of the resin plate 10 is
The current density on the other surface side of 0 can be made higher. That is, the copper electrode plates 44a and 44b connected to the anode of the single power source,
The gap between the resin plate 10 and the entire surface covered with the thin metal layer 14 connected to the cathode of the same power source is different. For example, the gap between the copper electrode 44a and the one surface of the resin plate 10 is set to the copper electrode 44.
By making the distance between b and the other surface side of the resin plate 10 narrower, the current density on the one surface side of the resin plate 10 can be reduced.
It can be higher than the current density on the other surface side. As a result, the metal layer 20 thicker than the metal layer 16 formed on the one surface of the resin plate 10 on the other surface can be formed in one step.

【0022】[0022]

【発明の効果】本発明によれば、微細なヴィアが形成さ
れた配線基板を工業的に生産でき、配線基板の配線パタ
ーン等の高密度化に対応することができる。
According to the present invention, it is possible to industrially produce a wiring board on which fine vias are formed, and it is possible to cope with a high density of a wiring pattern or the like of the wiring board.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明に係る配線基板の製造方法の一例を説明
するための工程図である。
FIG. 1 is a process drawing for explaining an example of a method of manufacturing a wiring board according to the present invention.

【図2】図1に示す工程で得られた複数枚の配線基板を
積層して形成された多層配線基板の部分断面図である。
FIG. 2 is a partial cross-sectional view of a multilayer wiring board formed by laminating a plurality of wiring boards obtained in the step shown in FIG.

【図3】図1に示す工程で得られた配線基板を単層で用
いた単層配線基板の部分断面図である。
FIG. 3 is a partial cross-sectional view of a single-layer wiring board using the wiring board obtained in the step shown in FIG. 1 as a single layer.

【図4】図1に示す工程で得られた配線基板を用いた半
導体装置用の配線基板の断面図である。
FIG. 4 is a cross-sectional view of a wiring board for a semiconductor device using the wiring board obtained in the step shown in FIG.

【図5】図1(d)(e)で示す工程の他の例を説明す
る説明図である。
FIG. 5 is an explanatory diagram illustrating another example of the steps shown in FIGS. 1D and 1E.

【図6】多層配線基板の一例を示す部分断面図である。FIG. 6 is a partial cross-sectional view showing an example of a multilayer wiring board.

【図7】図6に示す多層配線基板を製造する製造方法を
説明する説明図である。
FIG. 7 is an explanatory view explaining a manufacturing method for manufacturing the multilayer wiring board shown in FIG. 6;

【図8】図6に示す配線基板を製造する従来方法の一例
を説明する工程図である。
8A to 8C are process diagrams illustrating an example of a conventional method for manufacturing the wiring board shown in FIG.

【図9】図6に示す配線基板を製造する従来方法の他の
例を説明する工程図である。
9A to 9C are process drawings for explaining another example of the conventional method for manufacturing the wiring board shown in FIG.

【符号の説明】[Explanation of symbols]

10 樹脂板 12 貫通孔 14 薄金属層 16,20 金属層 18 ヴィア 22 配線パターン 24 接合部 28 外部接続端子 34 バンプ 44a,44b 電極板 10 resin plate 12 through holes 14 Thin metal layer 16,20 Metal layer 18 Via 22 wiring pattern 24 joints 28 External connection terminal 34 bump 44a, 44b Electrode plate

───────────────────────────────────────────────────── フロントページの続き (51)Int.Cl.7 識別記号 FI テーマコート゛(参考) H05K 3/46 H01L 23/12 N Fターム(参考) 5E317 AA01 AA24 BB02 BB12 BB18 CC32 CC33 CC38 CC44 CC51 CD25 CD32 GG14 5E346 AA06 AA12 AA15 AA22 AA35 AA43 BB01 BB16 CC02 CC09 CC32 CC33 CC40 DD02 DD25 DD32 FF07 FF35 GG15 GG17 GG22 GG28 HH07 HH25 ─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. 7 Identification code FI theme code (reference) H05K 3/46 H01L 23/12 NF term (reference) 5E317 AA01 AA24 BB02 BB12 BB18 CC32 CC33 CC38 CC44 CC51 CD25 CD32 GG14 5E346 AA06 AA12 AA15 AA22 AA35 AA43 BB01 BB16 CC02 CC09 CC32 CC33 CC40 DD02 DD25 DD32 FF07 FF35 GG15 GG17 GG22 GG28 HH07 HH25

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 樹脂板を貫通して形成されたヴィアの一
端側が、前記樹脂板の一面側に形成された配線パターン
に接合されている配線基板を製造する際に、 該樹脂板を貫通する貫通孔の内壁面を含む全表面に形成
した薄金属層を給電層とする電解めっきによって、前記
貫通孔を金属により充填してヴィアを形成すると共に、
前記樹脂板の一面側に、前記樹脂板の他面側に形成した
金属層よりも厚い金属層を形成し、 次いで、前記樹脂板の他面側に形成した金属層が除去さ
れたとき、前記樹脂板の一面側に所定の厚さの金属層が
残存するように、前記樹脂板の両面側に形成した金属層
にエッチングを施した後、 前記樹脂板の一面側に残存した金属層にパターニングを
施し、配線パターンを形成することを特徴とする配線基
板の製造方法。
1. When manufacturing a wiring board in which one end side of a via formed through a resin plate is joined to a wiring pattern formed on one surface side of the resin plate, the via hole penetrates through the resin plate. By electrolytic plating using a thin metal layer formed on the entire surface including the inner wall surface of the through hole as a power supply layer, the through hole is filled with metal to form a via,
On one side of the resin plate, a metal layer thicker than the metal layer formed on the other side of the resin plate is formed, and then, when the metal layer formed on the other side of the resin plate is removed, After etching the metal layers formed on both sides of the resin plate so that a metal layer having a predetermined thickness remains on the one side of the resin plate, patterning on the metal layer remaining on the one side of the resin plate And a wiring pattern are formed, the method for manufacturing a wiring board.
【請求項2】 貫通孔を、レーザによって形成する請求
項1記載の配線基板の製造方法。
2. The method for manufacturing a wiring board according to claim 1, wherein the through hole is formed by laser.
【請求項3】 薄金属層を、無電解めっきで形成する請
求項1又は請求項2記載の配線基板の製造方法。
3. The method for manufacturing a wiring board according to claim 1, wherein the thin metal layer is formed by electroless plating.
【請求項4】 電解めっきを、樹脂板の一面側の電流密
度を他面側の電流密度よりも高くして行う請求項1〜3
のいずれか一項記載の配線基板の製造方法。
4. The electrolytic plating is carried out with the current density on one surface side of the resin plate being higher than the current density on the other surface side.
A method for manufacturing a wiring board according to any one of 1.
【請求項5】 樹脂板の他面側に露出するヴィアの他端
側に、はんだや導電性ペースト等のろう材から成る接合
部を形成する請求項1〜4のいずれか一項記載の配線基
板の製造方法。
5. The wiring according to claim 1, wherein a joint portion made of a brazing material such as solder or conductive paste is formed on the other end side of the via exposed on the other surface side of the resin plate. Substrate manufacturing method.
【請求項6】 樹脂板の他面側に露出するヴィアの他端
側に、はんだボール等のろう材から成る接続端子を形成
する請求項1〜4のいずれか一項記載の配線基板の製造
方法。
6. The wiring board manufacturing method according to claim 1, wherein a connecting terminal made of a brazing material such as a solder ball is formed on the other end side of the via exposed on the other surface side of the resin plate. Method.
【請求項7】 樹脂板の一面側に配線パターンが形成さ
れていると共に、前記樹脂板を貫通するヴィアが形成さ
れた複数枚の樹脂基板を、多層に積層された配線パター
ンがヴィアで電気的に相互に接続されるように積層する
請求項1〜5のいずれか一項記載の配線基板の製造方
法。
7. A wiring pattern is formed on one surface side of a resin plate, and a plurality of resin substrates having vias penetrating the resin plate are electrically laminated by a via wiring pattern. The method for manufacturing a wiring board according to claim 1, wherein the wiring boards are laminated so as to be connected to each other.
JP2002115163A 2002-04-17 2002-04-17 Method of manufacturing wiring board Pending JP2003309214A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2002115163A JP2003309214A (en) 2002-04-17 2002-04-17 Method of manufacturing wiring board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002115163A JP2003309214A (en) 2002-04-17 2002-04-17 Method of manufacturing wiring board

Publications (1)

Publication Number Publication Date
JP2003309214A true JP2003309214A (en) 2003-10-31

Family

ID=29396638

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2002115163A Pending JP2003309214A (en) 2002-04-17 2002-04-17 Method of manufacturing wiring board

Country Status (1)

Country Link
JP (1) JP2003309214A (en)

Cited By (10)

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JP2007227929A (en) * 2006-02-24 2007-09-06 Samsung Electro-Mechanics Co Ltd Printed circuit board having inner via hole and manufacturing method thereof
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Publication number Priority date Publication date Assignee Title
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JP2007227929A (en) * 2006-02-24 2007-09-06 Samsung Electro-Mechanics Co Ltd Printed circuit board having inner via hole and manufacturing method thereof
US8476534B2 (en) 2007-12-25 2013-07-02 Furukawa Electric Co., Ltd. Multilayer printed board and method for manufacturing the same
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JP2009158615A (en) * 2007-12-25 2009-07-16 Furukawa Electric Co Ltd:The Multilayer printed board, and its manufacturing method
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JP2011176317A (en) * 2010-02-25 2011-09-08 Samsung Electronics Co Ltd Printed circuit board, semiconductor package including the same and manufacturing method of them, and electric and electronic device including semiconductor package
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KR101678052B1 (en) * 2010-02-25 2016-11-22 삼성전자 주식회사 Printed circuit board(PCB) comprising one-layer wire pattern, semiconductor package comprising the PCB, electrical and electronic apparatus comprising the package, method for fabricating the PCB, and method for fabricating the package
JP2013538015A (en) * 2010-09-25 2013-10-07 インテル・コーポレーション Electrolytic surface finishing with gold or gold palladium in coreless substrate processing
US8415200B2 (en) 2010-10-11 2013-04-09 Samsung Electro-Mechanics Co., Ltd. Method for manufacturing semiconductor package
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JP2012084826A (en) * 2010-10-11 2012-04-26 Samsung Electro-Mechanics Co Ltd Method of manufacturing semiconductor package
WO2016194241A1 (en) 2015-05-31 2016-12-08 清川メッキ工業株式会社 Method for manufacturing wiring board
US9756736B2 (en) 2015-05-31 2017-09-05 Kiyokawa Plating Industry Co., Ltd Process for producing a wiring board
KR20180036805A (en) 2015-05-31 2018-04-09 기요카와 멕키 고교 가부시키가이샤 Process for producing a wiring board
US11230779B2 (en) * 2019-05-31 2022-01-25 Shinko Electric Industries Co., Ltd. Substrate plating method

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