JPH10303341A - Resin sealed type semiconductor device - Google Patents
Resin sealed type semiconductor deviceInfo
- Publication number
- JPH10303341A JPH10303341A JP10935597A JP10935597A JPH10303341A JP H10303341 A JPH10303341 A JP H10303341A JP 10935597 A JP10935597 A JP 10935597A JP 10935597 A JP10935597 A JP 10935597A JP H10303341 A JPH10303341 A JP H10303341A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- adhesive
- metal frame
- modulus
- young
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L24/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L24/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48464—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area also being a ball bond, i.e. ball-to-ball
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/35—Mechanical effects
- H01L2924/351—Thermal stress
Abstract
Description
【０００１】[0001]
【発明の属する技術分野】この発明は、樹脂封止型半導
体装置に関するものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a resin-sealed semiconductor device.
【０００２】[0002]
【従来の技術】図９に示す樹脂封止型半導体装置があ
る。この装置は、金属フレーム５０の上に接着剤５１を
介して回路基板５２が配置され、回路基板５２における
金属フレーム５０との対向面には回路パターン５３が形
成され、回路基板５２および金属フレーム５０が封止樹
脂５４にてモールドされている。つまり、回路基板５２
の表面には例えば印刷法により回路パターン５３が形成
されており、この回路基板５２を金属フレーム５０上に
接着剤５１を用いて固定し、更に樹脂５４で封止してい
る。2. Description of the Related Art There is a resin-sealed semiconductor device shown in FIG. In this device, a circuit board 52 is disposed on a metal frame 50 via an adhesive 51, and a circuit pattern 53 is formed on a surface of the circuit board 52 facing the metal frame 50. Are molded with the sealing resin 54. That is, the circuit board 52
A circuit pattern 53 is formed on the surface of the substrate by, for example, a printing method. The circuit board 52 is fixed on a metal frame 50 using an adhesive 51, and further sealed with a resin 54.
【０００３】この構造物においては回路パターン５３の
応力による破壊を防ぎ信頼性を確保することが要望され
ている。特に、固定する金属フレーム５０にＣｕ（銅）
を用い、回路基板５２をセラミック製とした場合、その
接着剤５１に接するように配置された回路パターン５３
は熱が加わった際に構造物の熱膨張率差により過大なる
熱応力を受けるので、この熱応力から回路パターン５３
を保護する必要がある。In this structure, there is a demand for preventing the circuit pattern 53 from being broken by stress and ensuring reliability. Particularly, the metal frame 50 to be fixed is made of Cu (copper).
When the circuit board 52 is made of ceramic, a circuit pattern 53 arranged in contact with the adhesive 51 is used.
Receives an excessive thermal stress due to a difference in the thermal expansion coefficient of the structure when heat is applied.
Need to be protected.
【０００４】より詳しく説明すると、図９に示す状態か
ら温度変化により図１０に示すように、金属フレーム５
０と回路基板５２とが伸長し、かつ、金属フレーム５０
の方が回路基板５２よりも大きく伸長した場合におい
て、接着剤５１および回路パターン５３は金属フレーム
５０と回路基板５２との熱膨張率の差により過大なる熱
応力を受ける。More specifically, as shown in FIG. 10, the metal frame 5 shown in FIG.
0 and the circuit board 52 extend, and
Is larger than the circuit board 52, the adhesive 51 and the circuit pattern 53 receive excessive thermal stress due to the difference in the coefficient of thermal expansion between the metal frame 50 and the circuit board 52.
【０００５】なお、これを回避するための一手法とし
て、応力緩和樹脂層を予め回路パターン５３上に形成す
る方法があるが、上記構造体では必ずしも十分とは言え
ない。As one method for avoiding this, there is a method in which a stress relaxation resin layer is formed in advance on the circuit pattern 53, but the above structure is not always sufficient.
【０００６】[0006]
【発明が解決しようとする課題】そこで、この発明の目
的は、回路パターンの応力によるダメージ等を緩和する
ことができる樹脂封止型半導体装置を提供することにあ
る。SUMMARY OF THE INVENTION An object of the present invention is to provide a resin-encapsulated semiconductor device capable of reducing damage due to stress in a circuit pattern.
【０００７】[0007]
【課題を解決するための手段】請求項１に記載の発明
は、金属フレームと回路基板との間に配置される接着剤
のヤング率を、１５０ｋｇ／ｍｍ2 以下としたことを特
徴している。According to a first aspect of the present invention, the adhesive disposed between the metal frame and the circuit board has a Young's modulus of 150 kg / mm 2 or less. .
【０００８】この構成を採用することにより、温度変化
により金属フレームの熱膨張率と回路基板の熱膨張率の
差により回路パターンに対して応力が加わろうとする
が、接着剤のヤング率を１５０ｋｇ／ｍｍ2 以下として
いるので、回路パターンに対する応力が緩和される。そ
の結果、回路パターンへのダメージ等を緩和することが
できる。By employing this structure, stress is applied to the circuit pattern due to the difference between the coefficient of thermal expansion of the metal frame and the coefficient of thermal expansion of the circuit board due to a change in temperature, but the Young's modulus of the adhesive is reduced to 150 kg /. Since it is not more than mm 2, stress on the circuit pattern is reduced. As a result, damage to the circuit pattern can be reduced.
【０００９】ここで、請求項２に記載のように、前記接
着剤のヤング率を０．２ｋｇ／ｍｍ 2 以上、１５０ｋｇ
／ｍｍ2 以下とすると、実用上好ましいものとなる。ま
た、請求項３に記載のように、前記接着剤における封止
樹脂との密着力を、０．４ｋｇ／ｍｍ2 以上とすると、
実用上好ましいものとなる。Here, as described in claim 2, the contact
The Young's modulus of the adhesive is 0.2kg / mm Two150 kg
/ MmTwoThe following is preferable for practical use. Ma
And sealing in the adhesive as claimed in claim 3.
0.4kg / mm adhesion to resinTwoThen,
This is practically preferable.
【００１０】請求項４に記載の発明は、金属フレームと
回路基板との間に配置される接着剤での母材の中にバル
クヤング率低減手段を設けたことを特徴している。この
構成を採用することにより、温度変化により金属フレー
ムの熱膨張率と回路基板の熱膨張率の差により回路パタ
ーンに対して応力が加わろうとするが、接着剤での母材
の中に配置されているバルクヤング率低減手段にて回路
パターンに対する応力が緩和される。その結果、回路パ
ターンへのダメージ等を緩和することができる。The invention according to claim 4 is characterized in that a bulk Young's modulus reducing means is provided in a base material made of an adhesive disposed between the metal frame and the circuit board. By adopting this configuration, stress is applied to the circuit pattern due to the difference between the coefficient of thermal expansion of the metal frame and the coefficient of thermal expansion of the circuit board due to temperature changes, but is arranged in the base material with the adhesive. The stress applied to the circuit pattern is reduced by the bulk Young's modulus reducing means. As a result, damage to the circuit pattern can be reduced.
【００１１】ここで、請求項５に記載のように、前記バ
ルクヤング率低減手段を、前記金属フレームの熱膨張率
と前記回路基板の熱膨張率との間の熱膨張率を有する材
料よりなる添加材とすると、実用上好ましいものとな
る。The bulk Young's modulus reducing means is made of a material having a coefficient of thermal expansion between the coefficient of thermal expansion of the metal frame and the coefficient of thermal expansion of the circuit board. The use of an additive is practically preferable.
【００１２】請求項６に記載のように、前記添加材は、
薄板としてもよい。さらに、請求項７に記載のように、
前記バルクヤング率低減手段を、母材の中に散在させた
気泡とすると、実用上好ましいものとなる。[0012] As described in claim 6, the additive material comprises:
It may be a thin plate. Further, as described in claim 7,
It is practically preferable that the bulk Young's modulus reducing means be air bubbles scattered in a base material.
【００１３】[0013]
（第１の実施の形態）以下、この発明を具体化した第１
の実施の形態を図面に従って説明する。(First Embodiment) Hereinafter, a first embodiment of the present invention will be described.
An embodiment will be described with reference to the drawings.
【００１４】図１には、本実施の形態における樹脂封止
型半導体装置の平面図を示し、図２には図１のII−II断
面図を示す。Ｃｕ製金属フレーム１の上には接着剤２を
介してセラミック製回路基板３が接合されるとともに接
着剤４を介して回路基板５が接合され、混成集積回路装
置となっている。接着剤２，４はエポキシ系の樹脂を用
いており、一般的に用いられるエポキシ接着剤はヤング
率が２８０〜４００ｋｇ／ｍｍ2 程度であるが、本実施
形態においては、接着剤２，４のヤング率が０．２〜１
５０ｋｇ／ｍｍ2 となっている。このように、接着剤
２，４は軟エポシキ材を用い、かつ、ヤング率を０．２
ｋｇ／ｍｍ2 以上、１５０ｋｇ／ｍｍ2 以下とし、低ヤ
ング率化している。より具体的には、主剤としてダイマ
ー酸変性ジグリシジルエステル、硬化剤としてジアミノ
ジフェニルメタン、可とう性付与剤としてポリプロピレ
ングリコールを用い、ヤング率３ｋｇ／ｍｍ2 を達成し
ている。FIG. 1 is a plan view of a resin-sealed semiconductor device according to the present embodiment, and FIG. 2 is a sectional view taken along line II-II of FIG. A ceramic circuit board 3 is joined on the Cu metal frame 1 via an adhesive 2 and a circuit board 5 is joined via an adhesive 4 to form a hybrid integrated circuit device. The adhesives 2 and 4 use an epoxy-based resin, and a generally used epoxy adhesive has a Young's modulus of about 280 to 400 kg / mm 2 . Young's modulus is 0.2-1
It is 50 kg / mm 2 . Thus, the adhesives 2 and 4 use a soft epoxy material and have a Young's modulus of 0.2.
kg / mm 2 or more and 150 kg / mm 2 or less to reduce the Young's modulus. More specifically, dimer acid-modified diglycidyl ester is used as a main agent, diaminodiphenylmethane is used as a curing agent, and polypropylene glycol is used as a flexibility-imparting agent, and a Young's modulus of 3 kg / mm 2 is achieved.
【００１５】回路基板３と回路基板５とはボンディング
ワイヤ６にて電気的に接続されている。また、回路基板
３とリード端子７ａ，７ｂ，７ｃ，７ｄとはボンディン
グワイヤ８ａ，８ｂ，８ｃ，８ｄにて電気的に接続され
ている。図３に示すように、回路基板３における金属フ
レーム１との対向面には、例えば回路パターン９，１０
が形成されている。即ち、図４に示すように回路基板３
における金属フレーム１との対向面においては導電パタ
ーン１１，１２が延設され、両方の導電パターン１１，
１２の間には厚膜抵抗パターン１３が配置されている。
また、回路基板３における金属フレーム１との対向面に
おいては導電パターン１４，１５が延設され、両方の導
電パターン１４，１５の間には厚膜抵抗パターン１６が
配置されている。The circuit board 3 and the circuit board 5 are electrically connected by bonding wires 6. The circuit board 3 and the lead terminals 7a, 7b, 7c, 7d are electrically connected by bonding wires 8a, 8b, 8c, 8d. As shown in FIG. 3, for example, circuit patterns 9 and 10 are provided on the surface of the circuit board 3 facing the metal frame 1.
Are formed. That is, as shown in FIG.
The conductive patterns 11 and 12 are extended on the surface facing the metal frame 1 in the above.
A thick film resistor pattern 13 is arranged between the two.
In addition, conductive patterns 14 and 15 extend on a surface of the circuit board 3 facing the metal frame 1, and a thick-film resistance pattern 16 is disposed between the two conductive patterns 14 and 15.
【００１６】さらに、図１，２に示すように、回路基板
３，５，金属フレーム１，リード端子７ａ，７ｂ，７
ｃ，７ｄ，ボンディングワイヤ６，８ａ〜８ｄは封止樹
脂１７にてモールドされている。ここで、図２に示すよ
うに、金属フレーム１の下方での封止樹脂１７の厚さｔ
１は薄くなっており、ヒートシンクの機能を有してい
る。つまり、回路基板３，５に形成された回路は通電を
伴う駆動により発熱し、その熱は回路基板３，５から下
方の金属フレーム１側に伝播し、金属フレーム１の下方
での薄い封止樹脂１７を通して大気に放熱される。Further, as shown in FIGS. 1 and 2, circuit boards 3, 5, metal frame 1, lead terminals 7a, 7b, 7
c, 7 d and bonding wires 6, 8 a to 8 d are molded with a sealing resin 17. Here, as shown in FIG. 2, the thickness t of the sealing resin 17 below the metal frame 1
Numeral 1 is thin and has the function of a heat sink. That is, the circuits formed on the circuit boards 3 and 5 generate heat by driving with energization, and the heat propagates from the circuit boards 3 and 5 to the lower metal frame 1 side, and the thin sealing under the metal frame 1. The heat is radiated to the atmosphere through the resin 17.
【００１７】なお、封止樹脂１７にてモールドされる領
域は、回路基板３，５において全部、金属フレーム１に
おいて全部または一部である。製造の際には、図５に示
すように所定の形状を有するリードフレーム２０を用意
し、その上に回路基板３，５を配置するとともにワイヤ
６，８ａ，８ｂ，８ｃ，８ｄにてボンディングする。引
き続き、封止樹脂１７にてモールドし、リードフレーム
２０の所定位置Ｃ１，Ｃ２をカットする。その結果、図
１，２に示す樹脂封止型半導体装置を得る。The area molded with the sealing resin 17 is the whole of the circuit boards 3 and 5 and the whole or a part of the metal frame 1. At the time of manufacturing, as shown in FIG. 5, a lead frame 20 having a predetermined shape is prepared, circuit boards 3 and 5 are arranged thereon, and bonding is performed by wires 6, 8a, 8b, 8c and 8d. . Subsequently, molding is performed with the sealing resin 17 and predetermined positions C1 and C2 of the lead frame 20 are cut. As a result, a resin-sealed semiconductor device shown in FIGS.
【００１８】図１，２のモールド封止構造において、接
着剤２，４は回路基板３，５の固着に加えて封止樹脂１
７との密着性もその構造物の応力状態に関与する。つま
り、接着剤２，４は封止樹脂１７との界面が密着した方
がよい。図３において接着剤２（４）と封止樹脂１７と
の界面部ａにおいて、接着剤２（４）での封止樹脂１７
との密着力は０．４ｋｇ／ｍｍ2 以上となっている。In the mold sealing structure shown in FIGS. 1 and 2, the adhesives 2 and 4 are used to seal the circuit boards 3 and 5 and the sealing resin 1.
7 also contributes to the stress state of the structure. In other words, it is better that the adhesives 2 and 4 are in close contact with the interface with the sealing resin 17. In FIG. 3, at the interface a between the adhesive 2 (4) and the sealing resin 17, the sealing resin 17 with the adhesive 2 (4) is used.
Is 0.4 kg / mm 2 or more.
【００１９】図６には エポキシ系接着剤２，４のヤン
グ率と回路パターン９，１０に加わる剪断応力の測定結
果を示す。つまり、図９に示すように、Ｃｕ製金属フレ
ーム５０の上に接着剤５１を介してセラミック製回路基
板５２が配置されている場合において、温度変化により
例えば図１０に示すように、金属フレーム５０と回路基
板５２とが伸長し、かつ、金属フレーム５０の方が回路
基板５２よりも大きく伸長した際に、接着剤５１には剪
断応力Ｆが加わる。この時の接着剤５１のヤング率と剪
断応力Ｆとの関係を図６に示す。FIG. 6 shows the measurement results of the Young's modulus of the epoxy adhesives 2 and 4 and the shear stress applied to the circuit patterns 9 and 10. That is, as shown in FIG. 9, when the ceramic circuit board 52 is disposed on the Cu metal frame 50 with the adhesive 51 interposed therebetween, due to the temperature change, for example, as shown in FIG. When the metal frame 50 expands more than the circuit board 52 and the metal frame 50 expands more than the circuit board 52, a shear stress F is applied to the adhesive 51. FIG. 6 shows the relationship between the Young's modulus of the adhesive 51 and the shear stress F at this time.
【００２０】図６において、接着剤のヤング率が４００
ｋｇ／ｍｍ2 の場合には剪断応力が１．５ｋｇ／ｍｍ2
であったが、接着剤のヤング率を１５０ｋｇ／ｍｍ2 以
下とすることにより、剪断応力を厚膜破壊限界値の１．
０ｋｇ／ｍｍ2 以下とすることができる。また、接着剤
のヤング率の下限は、回路基板３，５の加工組付時の工
程を考慮すると、０．２ｋｇ／ｍｍ2 以上とする必要が
ある。In FIG. 6, the adhesive has a Young's modulus of 400.
kg / mm 2 , the shear stress is 1.5 kg / mm 2
However, by setting the Young's modulus of the adhesive to 150 kg / mm 2 or less, the shearing stress was reduced to a value of 1.
0 kg / mm 2 or less. Further, the lower limit of the Young's modulus of the adhesive needs to be 0.2 kg / mm 2 or more in consideration of the process at the time of processing and assembling the circuit boards 3 and 5.
【００２１】このように本実施の形態は下記の特徴を有
する。 （イ）金属フレーム１と回路基板３，５との間に配置さ
れる接着剤２，４のヤング率を、１５０ｋｇ／ｍｍ2 以
下としたので、温度変化により金属フレーム１の熱膨張
率と回路基板３，５の熱膨張率の差により回路パターン
９，１０に対して応力が加わろうとするが、接着剤２，
４のヤング率が１５０ｋｇ／ｍｍ2 以下となっているの
で、回路パターン９，１０に対する応力が緩和される。
よって、回路パターン９，１０へのダメージを緩和して
回路の信頼性を確保できる。 （ロ）接着剤２，４のヤング率を０．２ｋｇ／ｍｍ2 以
上、１５０ｋｇ／ｍｍ2以下とすると、前述したように
実用上好ましいものとなる。 （ハ）接着剤２，４における封止樹脂１７との密着力
を、０．４ｋｇ／ｍｍ2 以上とすると、実用上好ましい
ものとなる。 （第２の実施の形態）次に、第２の実施の形態を、第１
の実施の形態との相違点を中心に説明する。As described above, this embodiment has the following features. (A) Since the Young's modulus of the adhesives 2, 4 disposed between the metal frame 1 and the circuit boards 3, 5 is set to 150 kg / mm 2 or less, the thermal expansion coefficient of the metal frame 1 and the circuit The circuit patterns 9 and 10 try to apply stress due to the difference in the coefficient of thermal expansion between the substrates 3 and 5, but the adhesives 2 and
Since the Young's modulus of No. 4 is 150 kg / mm 2 or less, the stress on the circuit patterns 9 and 10 is reduced.
Therefore, damage to the circuit patterns 9 and 10 can be reduced, and the reliability of the circuit can be ensured. (Ii) a Young's modulus of the adhesive 2, 4 0.2 kg / mm 2 or more, when 150 kg / mm 2 or less, which is preferable in practical as described above. (C) When the adhesive force of the adhesives 2 and 4 to the sealing resin 17 is 0.4 kg / mm 2 or more, it is practically preferable. (Second Embodiment) Next, a second embodiment will be described with reference to the first embodiment.
The following description focuses on the differences from this embodiment.
【００２２】図７には、第１の実施の形態の図３に代わ
る本実施の形態における樹脂封止型半導体装置（混成集
積回路装置）を示す。図７において図３と同様の構成を
なす部材については同一の符号を付すことによりその説
明は省略する。FIG. 7 shows a resin-encapsulated semiconductor device (hybrid integrated circuit device) according to the present embodiment, which replaces FIG. 3 of the first embodiment. 7, members having the same configuration as in FIG. 3 are given the same reference numerals, and description thereof is omitted.
【００２３】図７において、接着剤２，４は、母材とし
てのエポキシ樹脂３０の中にバルクヤング率低減手段と
しての薄板３１が添加されている。バルクヤング率低減
用薄板３１は、金属フレーム１の熱膨張率と回路基板
３，５の熱膨張率との間の熱膨張率を有する材料よりな
る添加材である。具体的には、セラミック製回路基板
３，５およびＣｕ製金属フレーム１を用いた場合には、
セラミック板の熱膨張率が７ｐｐｍ／℃であり、Ｃｕ板
の熱膨張率が１７ｐｐｍ／℃であるので、その中間熱膨
張率をもつＦｅ製薄板（熱膨張率；１１ｐｐｍ／℃）を
バルクヤング率低減用薄板３１として用いる。または、
セラミック製回路基板３，５と同一材料のセラミック製
薄板をバルクヤング率低減用薄板３１として用いる。あ
るいは、軟樹脂製薄板をその低ヤング率によりバルクヤ
ング率を下げる目的でバルクヤング率低減用薄板３１と
して用いる。In FIG. 7, the adhesives 2 and 4 are obtained by adding a thin plate 31 as a bulk Young's modulus reducing means to an epoxy resin 30 as a base material. The bulk Young's modulus reducing thin plate 31 is an additive made of a material having a coefficient of thermal expansion between the coefficient of thermal expansion of the metal frame 1 and the coefficients of thermal expansion of the circuit boards 3 and 5. Specifically, when the ceramic circuit boards 3 and 5 and the Cu metal frame 1 are used,
Since the coefficient of thermal expansion of the ceramic plate is 7 ppm / ° C. and the coefficient of thermal expansion of the Cu plate is 17 ppm / ° C., the thin sheet made of Fe having an intermediate coefficient of thermal expansion (coefficient of thermal expansion; 11 ppm / ° C.) is used as the bulk Young's modulus. Used as the thin plate 31 for reduction. Or
A ceramic thin plate made of the same material as the ceramic circuit boards 3 and 5 is used as the bulk Young's modulus reducing thin plate 31. Alternatively, a soft resin thin plate is used as the bulk Young's modulus reducing thin plate 31 for the purpose of lowering the bulk Young's modulus by its low Young's modulus.
【００２４】このようにして、接着剤２，４の全体のヤ
ング率であるバルクヤング率を、エポキシ樹脂３０の中
に薄板３１を添加することにより低減し、回路パターン
９，１０に加わる応力を低減して応力緩和を図ってい
る。即ち、マクロ的にみた場合の接着剤のヤング率（バ
ルクヤング率）の低減を、薄板３１の添加により実現し
ている。In this way, the bulk Young's modulus, which is the total Young's modulus of the adhesives 2 and 4, is reduced by adding the thin plate 31 to the epoxy resin 30, and the stress applied to the circuit patterns 9 and 10 is reduced. Reduced to reduce stress. That is, a reduction in the Young's modulus (bulk Young's modulus) of the adhesive when viewed macroscopically is realized by the addition of the thin plate 31.
【００２５】例えば、薄板３１としてＦｅ板を用いた場
合には、Ｆｅ板は熱膨張率α＝１１ｐｐｍ、ヤング率Ｅ
＝２１６１０ｋｇ／ｍｍ2 であるので、Ｆｅ板を接着剤
中に添加しない場合には図６での接着剤のヤング率が４
００ｋｇ／ｍｍ2 であり剪断応力が１．５ｋｇ／ｍｍ2
であるが、Ｆｅ板を接着剤中に添加することにより、剪
断応力を０．７ｋｇ／ｍｍ2 （図６でのＡ点）にするこ
とができ、厚膜破壊限界値の１．０ｋｇ／ｍｍ2 以下と
することができる。For example, when an Fe plate is used as the thin plate 31, the Fe plate has a thermal expansion coefficient α = 11 ppm and a Young's modulus E
= 21610 kg / mm 2 , the Young's modulus of the adhesive in FIG.
00kg / mm 2 and is shear stress is 1.5kg / mm 2
However, by adding the Fe plate to the adhesive, the shear stress can be reduced to 0.7 kg / mm 2 (point A in FIG. 6), and the thick film breaking limit value of 1.0 kg / mm 2 is obtained. It can be 2 or less.
【００２６】また、薄板３１としてアルミナセラミック
板を用いた場合には、セラミック板は熱膨張率α＝７ｐ
ｐｍ、ヤング率Ｅ＝３１６００ｋｇ／ｍｍ2 であるの
で、セラミック板を接着剤中に添加しない場合には図６
での接着剤のヤング率が４００ｋｇ／ｍｍ2 であり剪断
応力が１．５ｋｇ／ｍｍ2 であるが、セラミック板を接
着剤中に添加することにより、剪断応力を０．２ｋｇ／
ｍｍ2 （図６でのＢ点）にすることができ、厚膜破壊限
界値の１．０ｋｇ／ｍｍ2 以下とすることができる。When an alumina ceramic plate is used as the thin plate 31, the ceramic plate has a thermal expansion coefficient α = 7p
pm, Young's modulus E = 3,1600 kg / mm 2 , and when no ceramic plate is added to the adhesive, FIG.
The adhesive has a Young's modulus of 400 kg / mm 2 and a shear stress of 1.5 kg / mm 2 , but by adding a ceramic plate to the adhesive, the shear stress is reduced to 0.2 kg / mm 2.
mm 2 (point B in FIG. 6), which can be less than the thick film breakdown limit value of 1.0 kg / mm 2 or less.
【００２７】このように本実施の形態は、下記の特徴を
有する。 （イ）接着剤２，４での母材であるエポキシ樹脂３０の
中にバルクヤング率低減手段としての薄板３１を添加し
たので、温度変化により金属フレーム１の熱膨張率と回
路基板３，５の熱膨張率の差により回路パターン９，１
０に対して応力が加わろうとするが、接着剤２，４での
母材の中に配置されている薄板３１にてバルクヤング率
が低減されており、回路パターン９，１０に対する応力
が緩和される。よって、回路パターン９，１０へのダメ
ージを緩和して回路の信頼性を確保できる。 （ロ）特に、バルクヤング率低減手段として、金属フレ
ーム１の熱膨張率と回路基板３，５の熱膨張率との間の
熱膨張率を有する材料よりなる添加材としての薄板３１
を用いると、実用上好ましいものとなる。 （第３の実施の形態）次に、第３の実施の形態を、第２
の実施の形態との相違点を中心に説明する。As described above, this embodiment has the following features. (A) Since the thin plate 31 as a means for reducing the bulk Young's modulus was added to the epoxy resin 30 as the base material of the adhesives 2 and 4, the coefficient of thermal expansion of the metal frame 1 and the circuit boards 3 and 5 Circuit patterns 9 and 1
However, the bulk Young's modulus is reduced by the thin plate 31 arranged in the base material with the adhesives 2 and 4, and the stress on the circuit patterns 9 and 10 is reduced. You. Therefore, damage to the circuit patterns 9 and 10 can be reduced, and the reliability of the circuit can be ensured. (B) In particular, as a means for reducing the bulk Young's modulus, a thin plate 31 as an additive made of a material having a coefficient of thermal expansion between the coefficients of thermal expansion of the metal frame 1 and the circuit boards 3 and 5.
Is preferable for practical use. (Third Embodiment) Next, a third embodiment will be described with reference to a second embodiment.
The following description focuses on the differences from this embodiment.
【００２８】図８には、図７に代わる本実施の形態にお
ける樹脂封止型半導体装置（混成集積回路装置）を示
す。図８において図３と同様の構成をなす部材について
は同一の符号を付すことによりその説明は省略する。FIG. 8 shows a resin-encapsulated semiconductor device (hybrid integrated circuit device) according to the present embodiment instead of FIG. 8, members having the same configuration as in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted.
【００２９】図８において、接着剤２，４は、母材とし
てのエポキシ樹脂４０の中にバルクヤング率低減手段と
しての気泡４１を散在させたものを用いている。具体的
には、エポキシ樹脂に中空球フィラー（マイクロカプセ
ル）を混入したものを用いている。中空球フィラーはそ
の直径が２０〜８０μｍ程度の微粒体であり、液状のエ
ポキシ樹脂と適量の中空球フィラーとを混合させて接着
剤として用いる。中空球フィラーとしては、例えば、日
本フィライト社製ＤＵ−８０を用いる。In FIG. 8, adhesives 2 and 4 are formed by dispersing bubbles 41 as a means for reducing bulk Young's modulus in epoxy resin 40 as a base material. Specifically, epoxy resin mixed with hollow sphere fillers (microcapsules) is used. The hollow sphere filler is a fine particle having a diameter of about 20 to 80 μm, and is used as an adhesive by mixing a liquid epoxy resin and an appropriate amount of the hollow sphere filler. As the hollow sphere filler, for example, DU-80 manufactured by Nippon Philite Co., Ltd. is used.
【００３０】このようにして、接着剤２，４の全体のヤ
ング率であるバルクヤング率を、エポキシ樹脂４０の中
に気泡４１を散在することにより低減し、回路パターン
９，１０に加わる応力を低減して応力緩和を図ってい
る。In this way, the bulk Young's modulus, which is the total Young's modulus of the adhesives 2 and 4, is reduced by dispersing the bubbles 41 in the epoxy resin 40, and the stress applied to the circuit patterns 9, 10 is reduced. Reduced to reduce stress.
【００３１】このように本実施の形態は、下記の特徴を
有する。 （イ）金属フレーム１と回路基板３，５との間に配置さ
れる接着剤２，４におけるバルクヤング率を低減すべ
く、母材であるエポキシ樹脂４０の中に気泡４１を散在
させたので、実用上好ましいものとなる。As described above, this embodiment has the following features. (A) Since bubbles 41 are scattered in the epoxy resin 40 as a base material in order to reduce the bulk Young's modulus of the adhesives 2 and 4 disposed between the metal frame 1 and the circuit boards 3 and 5, This is practically preferable.
【００３２】尚、上記実施形態ではエポキシ系の接着剤
を用いているが、これに限らず、例えばシリコン系でも
よく、要するにヤング率が１５０ｋｇ／ｍｍ2 以下であ
ればよい。In the above embodiment, an epoxy-based adhesive is used. However, the present invention is not limited to this. For example, a silicon-based adhesive may be used. In short, the Young's modulus may be 150 kg / mm 2 or less.
【図１】 実施の形態における樹脂封止型半導体装置の
平面図。FIG. 1 is a plan view of a resin-sealed semiconductor device according to an embodiment.
【図２】 図１のII−II断面図。FIG. 2 is a sectional view taken along line II-II of FIG.
【図３】 樹脂封止型半導体装置の一部拡大断面図。FIG. 3 is a partially enlarged cross-sectional view of a resin-sealed semiconductor device.
【図４】 回路基板の表面に形成された回路パターンを
示す平面図。FIG. 4 is a plan view showing a circuit pattern formed on the surface of the circuit board.
【図５】 樹脂封止型半導体装置の製造工程を説明する
ための平面図。FIG. 5 is a plan view for explaining a manufacturing process of the resin-encapsulated semiconductor device.
【図６】 接着剤のヤング率に対する剪断応力の測定結
果を示す図。FIG. 6 is a view showing a measurement result of a shear stress with respect to a Young's modulus of an adhesive.
【図７】 第２の実施の形態での樹脂封止型半導体装置
の一部拡大断面図。FIG. 7 is a partially enlarged cross-sectional view of a resin-sealed semiconductor device according to a second embodiment.
【図８】 第３の実施の形態での樹脂封止型半導体装置
の一部拡大断面図。FIG. 8 is a partially enlarged cross-sectional view of a resin-sealed semiconductor device according to a third embodiment.
【図９】 樹脂封止型半導体装置の断面図。FIG. 9 is a cross-sectional view of a resin-sealed semiconductor device.
【図１０】 樹脂封止型半導体装置の断面図。FIG. 10 is a cross-sectional view of a resin-sealed semiconductor device.
１…金属フレーム、２…接着剤、３…回路基板、４…接
着剤、５…回路基板、９…回路パターン、１０…回路パ
ターン、１７…封止樹脂、３０…エポキシ樹脂、３１…
薄板、４０…エポキシ樹脂、４１…気泡DESCRIPTION OF SYMBOLS 1 ... metal frame, 2 ... adhesive, 3 ... circuit board, 4 ... adhesive, 5 ... circuit board, 9 ... circuit pattern, 10 ... circuit pattern, 17 ... sealing resin, 30 ... epoxy resin, 31 ...
Thin plate, 40: epoxy resin, 41: air bubble
───────────────────────────────────────────────────── フロントページの続き (72)発明者 柴田 真二 愛知県刈谷市昭和町１丁目１番地 株式会 社デンソー内 ────────────────────────────────────────────────── ─── Continuing from the front page (72) Inventor Shinji Shibata 1-1-1 Showa-cho, Kariya-shi, Aichi Prefecture Inside DENSO Corporation
Claims (7)
基板が配置されるとともに、前記回路基板における金属
フレームとの対向面に回路パターンが形成され、さらに
前記回路基板および金属フレームの全部または一部が封
止樹脂にてモールドされた樹脂封止型半導体装置におい
て、 前記接着剤のヤング率を、１５０ｋｇ／ｍｍ2 以下とし
たことを特徴とする樹脂封止型半導体装置。1. A circuit board is arranged on a metal frame via an adhesive, a circuit pattern is formed on a surface of the circuit board facing the metal frame, and all or all of the circuit board and the metal frame are formed. A resin-sealed semiconductor device, a part of which is molded with a sealing resin, wherein the adhesive has a Young's modulus of 150 kg / mm 2 or less.
ｍｍ2 以上、１５０ｋｇ／ｍｍ2 以下とした請求項１に
記載の樹脂封止型半導体装置。2. The adhesive according to claim 1, wherein said adhesive has a Young's modulus of 0.2 kg /
2. The resin-encapsulated semiconductor device according to claim 1, wherein the thickness is not less than mm 2 and not more than 150 kg / mm 2 .
が、０．４ｋｇ／ｍｍ2 以上とした請求項１に記載の樹
脂封止型半導体装置。3. The resin-encapsulated semiconductor device according to claim 1, wherein an adhesive force of the adhesive with a sealing resin is 0.4 kg / mm 2 or more.
基板が配置されるとともに、前記回路基板における金属
フレームとの対向面に回路パターンが形成され、さらに
前記回路基板および金属フレームの全部または一部が封
止樹脂にてモールドされた樹脂封止型半導体装置におい
て、 前記接着剤での母材の中にバルクヤング率低減手段を設
けたことを特徴とする樹脂封止型半導体装置。4. A circuit board is disposed on a metal frame via an adhesive, a circuit pattern is formed on a surface of the circuit board facing the metal frame, and all or all of the circuit board and the metal frame are formed. A resin-encapsulated semiconductor device, a part of which is molded with a sealing resin, wherein a bulk Young's modulus reducing means is provided in a base material of the adhesive.
属フレームの熱膨張率と前記回路基板の熱膨張率との間
の熱膨張率を有する材料よりなる添加材である請求項４
に記載の樹脂封止型半導体装置。5. The bulk Young's modulus reducing means is an additive made of a material having a coefficient of thermal expansion between the coefficient of thermal expansion of the metal frame and the coefficient of thermal expansion of the circuit board.
3. The resin-sealed semiconductor device according to claim 1.
載の樹脂封止型半導体装置。6. The resin-encapsulated semiconductor device according to claim 5, wherein the additive is a thin plate.
中に散在させた気泡である請求項４に記載の樹脂封止型
半導体装置。7. The resin-encapsulated semiconductor device according to claim 4, wherein said bulk Young's modulus reducing means is bubbles scattered in a base material.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10935597A JP3845947B2 (en) | 1997-04-25 | 1997-04-25 | Resin-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP10935597A JP3845947B2 (en) | 1997-04-25 | 1997-04-25 | Resin-sealed semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH10303341A true JPH10303341A (en) | 1998-11-13 |
| JP3845947B2 JP3845947B2 (en) | 2006-11-15 |
Family
ID=14508134
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP10935597A Expired - Lifetime JP3845947B2 (en) | 1997-04-25 | 1997-04-25 | Resin-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3845947B2 (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7230320B2 (en) | 2003-02-18 | 2007-06-12 | Hitachi, Ltd. | Electronic circuit device with reduced breaking and cracking |
| US7531852B2 (en) | 2004-06-14 | 2009-05-12 | Denso Corporation | Electronic unit with a substrate where an electronic circuit is fabricated |
| US7843700B2 (en) | 2004-04-14 | 2010-11-30 | Denso Corporation | Semiconductor device |
-
1997
- 1997-04-25 JP JP10935597A patent/JP3845947B2/en not_active Expired - Lifetime
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7230320B2 (en) | 2003-02-18 | 2007-06-12 | Hitachi, Ltd. | Electronic circuit device with reduced breaking and cracking |
| US7843700B2 (en) | 2004-04-14 | 2010-11-30 | Denso Corporation | Semiconductor device |
| US8179688B2 (en) | 2004-04-14 | 2012-05-15 | Denso Corporation | Semiconductor device |
| US7531852B2 (en) | 2004-06-14 | 2009-05-12 | Denso Corporation | Electronic unit with a substrate where an electronic circuit is fabricated |
Also Published As
| Publication number | Publication date |
|---|---|
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