JPH10301681A - Interface device, its control method and information processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain an interface device, its control method and an information processor which cope with physical restriction of a package which accompanies making a system multiple bits by reducing the number of output pins of a gate array and also make signal processing efficient. SOLUTION: In a gate array 101, a clock outputting means 130 generates and outputs fast and slow independent clocks, and also a serial data outputting means 120 converts status data into serial data. The serial data are converted into parallel data by dividing the serial data after conversion into two clocks which are a fast clock and a slow clock and processing them by using a serial- parallel converting means 120.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an interface device and a control method thereof, and more particularly, to an information processing device such as a printer for controlling an output signal when a Centronics interface is used.

[0002]

2. Description of the Related Art FIG. 5 shows an example of the configuration of a conventional Centronics interface.

[0005] The printer P is connected to a host computer H using a Centronics interface, and performs data transfer. In this case, an output signal of the printer P is output from a connector 302 to a cable 303 from a gate array 301 constituting a hardware portion of the system.
Is transmitted to the host computer H via

On the printer P side, reference numeral 300 denotes a main controller board on which a gate array 301 is mounted. The gate array 301 directly outputs an output signal of the Centronics interface in a parameter state. Then, a circuit inside the gate array 301 independently operates each output signal to perform handshake and status notification with the host computer H. That is, each output signal output from the gate array 301 is transmitted through the connector 302 and the cable 303.
The status of the printer P is notified by outputting the status of the signal to the host computer H. As described above, each output signal is output in parallel from the gate array 301 having the built-in Centronics interface circuit.

[0005]

However, in the above prior art, the centronics interface is a parallel output, and the number of control signals as output signals is larger than that of the serial interface.
The ratio of the input / output pins to the whole increases. In recent years, in particular, the system CPU, RAM, and data bus of ROM,
Multi-bit address bus (for example, 16 bits → 32b
It), it has become necessary to increase the number of input / output pins of the package of the gate array 301, but reducing the number of input / output pins due to physical constraints of the package has become an issue. .

Therefore, the output pins of the gate array 301 are serialized to reduce the number of pins.
It is conceivable to output a control signal of a Centronics interface by performing parallel conversion in a circuit provided outside the gate array 301.

However, since the number of control signals of the Centronics interface is large, the serial-to-parallel conversion simply takes a long time to perform serial-to-parallel conversion processing, and a high-speed response to the host computer H is expected. Can not.

In other words, among the output signals shown in FIG. 5, that is, the control signals, signals requiring a high-speed response with the host computer (for example, BUSY and ACK signals)
Or a signal that can be responded at a low speed (for example,
r, Fault signals), but these signals are not properly used. Therefore, high-speed processing and, consequently, the number of input / output pins of the gate array cannot be reduced. Inability to address physical constraints.

Therefore, an object of the present invention is to process the output signal of the Centronics interface roughly into a signal requiring a high-speed response (handshake signal) and a signal requiring only a low-speed response (status signal). An interface device, a control method thereof, and an information processing device capable of reducing the number of output pins of a gate array, addressing physical constraints of a package accompanying multi-bit system, and improving signal processing efficiency. To provide.

[0010]

SUMMARY OF THE INVENTION The present invention relates to an interface device in a slave device for exchanging signals with a master device. The interface device is provided in an interface output control unit and converts a control signal into serial data. Serial data output means for converting and outputting the serial data, clock output means for creating and outputting a plurality of clocks, and the serial data and the plurality of serial data output from the interface output control unit, which are provided in an external connection unit. And a serial-to-parallel conversion means for converting serial data into parallel data by performing processing by dividing the clock into a plurality of systems for each clock, thereby constituting an interface device.

Here, the serial-parallel conversion means may include high-speed conversion means for converting serial data to parallel data by high-speed processing, and low-speed conversion means for converting serial data to parallel data by low-speed processing. The high-speed conversion means is configured with a smaller number of bits for converting to parallel data than the low-speed conversion means.

The serial data output means sends one system of serial data as data shared by the high-speed conversion means and the low-speed conversion means, and outputs serial data of a plurality of systems to the high-speed conversion means and the high-speed conversion means. Each of them can be sent independently to the low-speed conversion means.

The present invention is also a method of controlling an interface in a slave device for exchanging signals with a master device, wherein an interface output control unit converts a control signal into serial data. Output and generate and output a plurality of clocks, and in the external connection unit, the serial data and the plurality of clocks output from the interface output control unit are input and divided into a plurality of systems for each clock. Then, the serial data can be converted into parallel data by performing the processing.

When converting the serial data into parallel data, the serial data is converted by high-speed processing.
It can be converted by slow processing.

In the conversion by the high-speed processing, the number of bits to be converted into parallel data can be reduced as compared with the conversion by the low-speed processing.

One system of serial data output from the interface output control unit can be input as data shared by the high-speed conversion unit and the low-speed conversion unit in the external connection unit. Further, serial data of a plurality of systems output from the interface output control unit can be independently input to the high-speed conversion unit and the low-speed conversion unit in the external connection unit.

[0017] The interface output control section may be configured by being incorporated in a Centronics interface.

According to the present invention, there is provided a printer for exchanging signals with a host computer via an interface, wherein the interface device according to the present invention is used as the interface, and the printer is created by the interface. By transmitting a control signal to the host computer, an information processing apparatus can be configured.

[0019]

Embodiments of the present invention will be described below in detail with reference to the drawings.

The first embodiment of the present invention will be described with reference to FIGS.
It will be described based on.

FIG. 1 shows an example of the configuration of a Centronics interface of an information processing apparatus (hereinafter, referred to as a printer P) connected to a host computer H. In addition,
In this example, of the configuration of the Centronics interface in the printer P, only the configuration on the output side is shown, and the configuration on the input side similar to the conventional one is omitted.

100 is a main controller board,
It manages the processing of the printer P composed of a microprocessor system including memories (ROM, RAM). On this main controller board 100, a gate array 101 for performing signal processing of a Centronics interface is mounted. This gate array 101 has a control signal (BUS
Y, ACK, Select...) Are output as serial data, and a clock output unit 130 that generates high-speed and low-speed clocks is provided.

Reference numeral 200 denotes a connector board. A connector 204 for connecting to a host computer H of a Centronics interface is mounted on the connector board 200, and a circuit that performs serial-parallel conversion of a serialized control signal (Centronics output signal) output from the gate array 101. 210 are implemented.

The high-speed shift register 201 is a shift register, and holds a handshake signal (BUSY, ACK signal, etc.) of the Centronics interface. The control signal (serial data) output from the gate array 101 is subjected to serial-to-parallel conversion when a high-speed shift clock (clock signal) is input, and the high-speed shift register 201 is output.
Holds the handshake signal of the Centronics interface.

The low-speed shift register 202 is a shift register and holds a status signal (Error, Select signal, etc.) of the Centronics interface. The control signal (serial data) output from the gate array 101 is subjected to serial-to-parallel conversion when a low-speed shift clock (clock signal) is input, and the status signal of the Centronics interface is sent to the low-speed shift register 202. Is held.

The meaning of the shift clock and the high speed and the low speed used in the shift registers 201 and 202 in the present invention means that the number of bits is small (Q0, Q1) in the serial / parallel conversion processing in the shift registers 201 and 202. 2 bits) processing is large in number of bits (Q
This is based on the fact that the time required for parallel conversion is shorter than that of the (2 bits to 8 bits of 7 bits) processing. Therefore, here
Rather than performing parallel conversion due to the difference in clock speed, a high-speed register or a low-speed register is determined according to the difference in the number of bits to be parallel-converted.

FIG. 2 shows an example of a serial / parallel conversion process of the control output of the Centronics interface of the present embodiment.

The high-speed shift clock is supplied to the gate array 1
01 and is input to the clock input terminal (CLK) of the high-speed shift register 201. The low-speed shift clock is output by the gate array 101, and a clock input terminal (CLK) of the low-speed shift register 202.
Is input to Control signal data output from the gate array 101 is serial data common to the high-speed shift register 201 and the low-speed shift register 202.
The value of this control signal (Centronics interface output signal) is output serially. The value of this control signal is sequentially shifted by the shift register 201,
202. The set pulse output from the gate array 101 is a control signal for the latch 203. With this set pulse, the values D0 to D0 input to the input terminals
D8 is held and output inside the latch.

Here, Q0 and Q1 are high-speed shift registers 201, and Q2 to Q8 are low-speed shift registers 202.
Are the values to be retained and output, respectively. In addition, Z0 to Z8
Is a value held and output by the latch 203. The control signal output from the latch 203 is connected to the connector 204,
The data is output to the host computer H via the cable 205.

Here, the timing chart of FIG. 2 will be described.

This timing chart shows the flow of processing from the state where the control signals Z0 to Z8 output from the latch 203 hold all 0 values as initial values to the time when all the held values are changed to 1. .

At the initial stage, the values held in all of Q0 to Q8 are 0. The values held in all of Z0 to Z8 are 0.

At timing t501, the value of the signal data is changed from 0 to 1. Then, in order to change all the Centronics output signals to 1, 1 is continuously output.

The shift register holds serial data for each clock input. That is, in the high-speed shift register 201, the held values move from Q0 to Q1 and serial data input to Q0 are performed at every rising edge of the clock input.

In the low-speed shift register 202,
Q7 → Q8, Q6 → Q7, Q5 → Q6, Q4 → Q5, Q
The movement of the held values of 3 → Q4, Q2 → Q3, serial data input → Q2 is performed at every rising of the clock input.

At timings t502 and t503,
At the rise of the clock pulse of the high-speed shift register 201, the values of the signal data are sequentially held in the high-speed shift register 201. Then, the values of Q0 and Q1 are set.

At timings t504 to t510,
At the rise of the clock pulse of the low-speed shift register 202, the values of the signal data are sequentially held in the low-speed shift register 202. Then, the values of Q2 to Q8 are set.

At timing t511, the set pulse signal becomes 1. At this timing, the latch 203 sets D0 to D0.
The value input to D8 is held internally and output to Z0 to Z8. The values of Z0 to Z8 simultaneously change from 0 to 1.

In this way, it is possible to manipulate the value of the output signal of the Centronics interface. The above processing is processing from serial conversion of the gate array 101 to parallel conversion and manipulation of a signal output to the cable 205.

In this embodiment, since the shift clock for the shift register for performing the serial-parallel conversion is provided in two systems (but not limited to these two systems), the shift register for the high-speed response for the handshake signal is provided. 20
1 and the low-speed response shift register 202 for the status signal can be independently operated.

FIG. 3 shows an example of the processing of the present embodiment, and shows processing for operating a handshake signal for high-speed processing.

In the Centronics interface,
The BUSY and nACK signals are used as handshake signals for data transfer. Therefore, the host computer H
It is necessary to perform a high-speed response in order to increase the efficiency of data transfer to and from the device.

In this embodiment, since the signal for high-speed response is controlled by an independent shift clock, only the handshake signal is serial-parallel converted at the time of handshake, and the status signal which is a group of low-speed response is not operated. It is possible to control. As described above, the response to the host computer H can be performed at a high speed by serial-to-parallel conversion of only the output signals (the control signals of the BUSY and nACK signals) of the high-speed response group.

The timing chart of FIG. 3 shows a process for continuously controlling the BUSY signal output from Z0 and the nACK signal output from Z1.

At timings t601 and t602, signal data values are sequentially stored in Q0 and Q1 of the high-speed shift register 201 at the rise of the high-speed shift clock. The value held for both Q0 and Q1 changes from 0 to 1.

At timing t603, the set pulse signal becomes 1. At this timing, the latch 203 sets D0
To the input terminals D8 to D8.
To Z8. In this processing, the value held by the low-speed shift register 202 does not change because it is not operated.
Since the D0 and D1 inputs of the latch 203 change from 0 to 1, the Z0 and Z1 outputs change from 0 to 1. That is, BUSY (Z0) changes from 0 to 1 and nACK
(Z1) changes from 0 to 1.

At timings t604 and t605, at the rising edge of the high-speed shift clock, the signal data values are sequentially changed to Q0 and Q0 of the high-speed shift register 201.
It is stored in Q1. Q0 holds a value of 1 → 0 → 1
In addition, the value held in Q1 changes from 1 to 0.

At timing t606, the set pulse signal becomes 1. At this timing, the latch 203 sets D0
ＤD8 are internally stored and output to Z0 to Z8. In this processing, the value held by the shift register low-speed operation 202 does not change because it is not operated. Latch 203
Since D0 remains 1 and D1 changes to 0, the values held by the latch 203 are Z0 → 1, Z1 →
It becomes 0. That is, BUSY (Z0) remains 1, and nACK (Z1) changes from 1 to 0.

In the above processing, it is possible to control the BUSY signal output from 0 to 1 and the nACK signal output from 0 to 1 and 0, respectively.

As described above, by controlling only the handshake signal for high-speed response as compared with the case where all control signals (centronics output signals) are controlled, a high-speed response processing to the host computer H can be performed. It can be performed.

Next, a second embodiment of the present invention will be described with reference to FIG.
It will be described based on.

In the above-described example, the control signal data is shared for the high-speed response and the low-speed response. However, the same processing can be performed even in a configuration having independent signal data like the shift clock. it can.

FIG. 4 shows a configuration example of the Centronics interface in that case. In this example, the gate array 10
1 is a high-speed signal data,
The signal data for low speed has a configuration independent of two systems.

In this configuration, the pins output from the gate array 101, that is, the main controller board 100
However, the number of signal lines connecting the connector and the connector board 200 is increased by one, so that the high-speed shift register 201 and the low-speed shift register 202 can be controlled in parallel.

[0055]

As described above, according to the present invention, the output signal of the Centronics interface is serially converted at the pin output of the gate array to parallel conversion by an external circuit. Can be reduced as compared with the conventional configuration.

Also, since a plurality of serial signal clocks are provided, the pin output of the gate array becomes serial, and even in a configuration in which parallel conversion is performed by an external circuit, handshaking with the host computer can be performed at high speed. .

Further, by reducing the output signals of the centronics interface of the gate array, in the configuration in which the main board on which the gate array is mounted and the connector board on which the connector for connecting the external device of the centronics interface is mounted are separated. This makes it possible to reduce the number of signals of cables connecting the boards.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration example of a Centronics interface according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a serial / parallel conversion process of an output signal of a Centronics interface.

FIG. 3 is a timing chart showing a processing example of operating a handshake high-speed signal.

FIG. 4 is a block diagram illustrating a configuration example of a Centronics interface according to a second embodiment of the present invention.

FIG. 5 is a block diagram showing a configuration example of a conventional Centronics interface.

[Explanation of symbols]

 Reference Signs List 101 Interface output control unit 120 Serial data output unit 130 Clock output unit 200 External connection unit 201 High speed conversion unit (serial / parallel conversion unit) 202 Low speed conversion unit (serial / parallel conversion unit)

Claims (13)

[Claims] 1. An interface device in a slave device for exchanging signals with a master device, wherein the serial device is provided in an interface output control unit and converts a control signal into serial data and outputs the data. An output unit, a clock output unit that creates and outputs a plurality of clocks, and is provided in an external connection unit, and receives the serial data and the plurality of clocks output from the interface output control unit, and receives each clock. An interface device comprising: serial / parallel conversion means for converting serial data into parallel data by dividing the data into a plurality of systems and performing processing. 2. The serial-to-parallel conversion means includes high-speed conversion means for converting serial data to parallel data by high-speed processing, and low-speed conversion means for converting serial data to parallel data by low-speed processing. The interface device according to claim 1. 3. The interface apparatus according to claim 2, wherein said high-speed conversion means has a smaller number of bits for converting to parallel data than said low-speed conversion means. 4. The interface device according to claim 2, wherein said serial data output means sends one system of serial data as data shared by said high-speed conversion means and said low-speed conversion means. 5. The interface device according to claim 2, wherein said serial data output means sends serial data of a plurality of systems to said high-speed conversion means and said low-speed conversion means independently of each other. 6. The interface device according to claim 1, wherein the interface output control unit is incorporated in a Centronics interface. 7. A method of controlling an interface in a slave device that exchanges signals with a master device, wherein an interface output control unit converts a control signal into serial data and outputs the data. A plurality of clocks are created and output, and the serial data and the plurality of clocks output from the interface output control unit are input to an external connection unit, and divided into a plurality of systems for each clock for processing. A method of controlling an interface, comprising: converting serial data into parallel data by performing the conversion. 8. The interface control method according to claim 7, wherein, when converting the serial data into parallel data, the serial data is converted by high-speed processing and converted by low-speed processing. 9. The interface control method according to claim 8, wherein the conversion by the high-speed processing has a smaller number of bits to be converted into parallel data than the conversion by the low-speed processing. 10. The serial data of one system output from the interface output control unit is input as data shared by the high-speed conversion unit and the low-speed conversion unit in the external connection unit. 10. The method for controlling an interface according to 8 or 9. 11. The serial data of a plurality of systems output from the interface output control unit is independently input to the high-speed conversion unit and the low-speed conversion unit in the external connection unit. 10. The method for controlling an interface according to 8 or 9. 12. The interface control method according to claim 7, wherein said interface output control unit is incorporated in a Centronics interface. 13. A printer that exchanges signals with a host computer via an interface, wherein the interface is the interface device according to claim 1 and is created by the interface. An information processing device for transmitting a control signal to the host computer.