CN113539343B - Multi-path output method, device and equipment of shift register and storage medium - Google Patents

Multi-path output method, device and equipment of shift register and storage medium Download PDF

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CN113539343B
CN113539343B CN202110860599.6A CN202110860599A CN113539343B CN 113539343 B CN113539343 B CN 113539343B CN 202110860599 A CN202110860599 A CN 202110860599A CN 113539343 B CN113539343 B CN 113539343B
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clock signal
output
control data
cluster
low level
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CN113539343A (en
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梁辉
孔令波
高恩宇
苏帆
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Beijing Weina Starry Sky Technology Co ltd
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Beijing MinoSpace Technology Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C19/00—Digital stores in which the information is moved stepwise, e.g. shift registers
    • G11C19/28—Digital stores in which the information is moved stepwise, e.g. shift registers using semiconductor elements
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/382—Information transfer, e.g. on bus using universal interface adapter
    • G06F13/385—Information transfer, e.g. on bus using universal interface adapter for adaptation of a particular data processing system to different peripheral devices
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/38—Universal adapter
    • G06F2213/3852—Converter between protocols

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  • General Engineering & Computer Science (AREA)
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Abstract

The application provides a multi-output method, a multi-output device, a multi-output equipment and a multi-output storage medium of a shift register, which are applied to the technical field of electronics, wherein the method comprises the following steps: when the first clock signal is changed from low level to high level, the shift register sends control data to the storage register; the output end of the storage register sends the control data to the clock input end of the D trigger cluster; when the second clock signal is changed from the low level to the high level, the clock input end of the D trigger cluster sends the control data to the output end of the D trigger cluster; when the third clock signal transitions from the low level to the high level, the D flip-flop output terminal transmits the control data to the external component device. The beneficial effect of this application mainly lies in: the selected serial shift register receives the multi-bit control data, and then outputs the received control data through the output end of the D trigger cluster, so that the serial-parallel conversion function is realized, the working efficiency of the integrated circuit is improved, and the occupancy rate of an output interface is reduced.

Description

Multi-path output method, device and equipment of shift register and storage medium
Technical Field
The present application relates to the field of electronic technologies, and in particular, to a method, an apparatus, a device, and a storage medium for multiplexing a shift register.
Background
With the development of Integrated Circuits (ICs), there is a clear trend of producing ultra-small, highly reliable, high-speed and low power, and the complexity of the integrated circuits is gradually increased due to the improvement of integration density, such as logic cells for fabrication, to improve the design efficiency of application specific integrated circuits, which are regarded as important factors affecting the performance of the integrated circuits by integrating flip-flops performing memory functions into one chip.
Because the satellite ground station measurement and control equipment is numerous, a large number of input/output (I/O) interfaces are needed for measuring and controlling external component equipment of the satellite ground station, independent output interfaces are respectively used for controlling on-off and heating equipment such as a satellite sensor, a gyroscope, a momentum wheel, a magnetic rod, a monitoring camera, a sensor and the like at the present stage, a large number of input/output (I/O) interfaces are occupied for outputting control data, 64 paths of output interfaces are greatly wasted, and the working efficiency is limited.
Disclosure of Invention
In view of this, an embodiment of the present application provides a method for outputting multiple channels of a shift register, where a serial shift register is selected to receive multiple bits of control data, and then the received control data is output through an output end of a D flip-flop cluster, so as to implement a serial-to-parallel conversion function, improve the working efficiency of an integrated circuit, and reduce the occupancy rate of an output interface.
In a first aspect, an embodiment of the present application provides a method for multiplexing outputs of a shift register, where the method includes:
the upper computer control end responds to a technician operation instruction and sends a first clock signal to the clock input end of the shift register, wherein the first clock signal is a multi-stage delay signal;
when a first clock signal transits from a low level to a high level, the shift register transmits control data into the storage register;
the output end of the storage register sends control data to the clock input end of a D trigger cluster, and the D trigger cluster consists of 8D triggers;
the upper computer control end responds to a technician operation instruction and sends a second clock signal to the clock input end of the D trigger cluster, wherein the second clock signal is a multi-stage delay signal;
when the second clock signal is changed from low level to high level, the clock input end of the D trigger cluster sends control data to the output end of the D trigger cluster;
the upper computer control end responds to an operation instruction of a technician and sends a third clock signal to the clock input end of the D trigger cluster, wherein the third clock signal is a multi-stage delay signal;
the output of the D flip-flop cluster transmits the control data to an external component device when the third clock signal transitions from a low level to a high level.
In some embodiments, the sending the first clock signal to the input end of the shift register clock by the upper computer control end in response to the technician operation instruction includes:
a DC/DC chip in the upper computer control end outputs 3.3V voltage to supply power to a power supply VCC pin of the shift register;
and responding to an operation instruction of a technician, and sending the first clock signal to the clock input end of the shift register by any output pin of the upper computer control end.
In some embodiments, the shift register sends the control data into the storage register when the first clock signal transitions from a low level to a high level, including:
when the first clock signal transits from the low level to the high level, the shift register transmits the control data to the output terminal Q of the storage register1Performing the following steps;
responding to an operation instruction of a technician, and sending the first clock signal to the clock input end of the shift register again by the upper computer control end;
when the retransmitted first clock signal transits from a low level to a high level, the output terminal Q of the storage register1Shifting control data to the output Q of the memory register2And storing the control data generated this time to the output end Q of the storage register1Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register for the third time by the upper computer control end;
when the first clock signal transmitted for the third time is transited from the low level to the high level, the output end Q of the storage register2Shifting control data to the output Q of the memory register3And storing the control data generated this time to the output end Q of the storage register2Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register for the fourth time by the upper computer control end;
when the first clock signal of the fourth transmission is transited from the low level to the high level, the output end Q of the storage register3Shifting control data to inputs of a memory registerOutput end Q4And storing the control data generated this time to the output end Q of the storage register3Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the fifth time;
when the fifth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register4Shifting control data to the output Q of the memory register5And storing the control data generated this time to the output end Q of the storage register4Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the sixth time;
when the sixth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register5Shifting control data to the output Q of the memory register6And storing the control data generated this time to the output end Q of the storage register5Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the seventh time;
when the seventh transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register6Shifting control data to the output Q of the memory register7And storing the control data generated this time to the output end Q of the storage register6Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the eighth time;
when the eighth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register7Shifting control data to the output Q of the memory register8And storing the control data generated this time to the output end Q of the storage register7In (1).
In some embodiments, the output of the storage register sends the control data to a clock input of a D flip-flop cluster, the D flip-flop cluster consisting of 8D flip-flops, comprising:
a DC/DC chip in the upper computer control end outputs 3.3V voltage to a power pin of a D trigger cluster, an enabling end of the D trigger cluster is directly grounded, and the D trigger cluster is effective in low level;
output Q of the memory register1-Q8Clock input terminal D for transmitting control data to D flip-flop cluster1-D8Wherein the output Q of the memory register1-Q8Respectively connected with clock input ends D of D flip-flop clusters1-D8And conducting.
In some embodiments, when the second clock signal transitions from a low level to a high level, the clock input of the D flip-flop cluster sending control data to the output of the D flip-flop cluster, comprising:
when the second clock signal is at a low level, the clock input end of the D trigger cluster is communicated with the output end of the D trigger cluster;
the upper computer control end sends a second clock signal to the clock input end of the D trigger cluster again;
the second clock signal is changed from low level to high level, the clock input end of the D trigger cluster sends the control data in the storage register to the output end of the D trigger cluster, and the output end Q of the D trigger cluster1Q8 each comprise 8 outputs.
In some embodiments, when the third clock signal transitions from a low level to a high level, the output of the D flip-flop cluster transmits the control data to an external component device, including:
the upper computer control end sends a third clock signal to an output end Q of the D trigger cluster1-Q8；
When the third clock signal goes from low level to high level, the output end Q of the D trigger1-Q8Sends control data toAnd the output end of any D trigger is connected with a plurality of external component devices.
In a second aspect, an embodiment of the present application provides a multi-output apparatus for a shift register, including:
the upper computer control end responds to a technician operation instruction and sends a first clock signal to the clock input end of the shift register, and the first clock signal is a multi-stage delay signal;
a first transmitting module which transmits control data to the storage register when the first clock signal transitions from a low level to a high level;
the output end of the storage register sends control data to the clock input end of a D trigger cluster, and the D trigger cluster consists of 8D triggers;
the upper computer control end responds to a technician operation instruction and sends a second clock signal to the clock input end of the D trigger cluster, and the second clock signal is a multi-stage delay signal;
the third sending module is used for sending the control data to the output end of the D trigger cluster by the clock input end of the D trigger cluster when the second clock signal is changed from the low level to the high level;
the upper computer control end responds to an operation instruction of a technician and sends a third clock signal to the clock input end of the D trigger cluster, and the third clock signal is a multi-stage delay signal;
and the fourth sending module is used for sending the control data to the external component device by the output end of the D flip-flop cluster when the third clock signal is changed from the low level to the high level.
In some embodiments, the third sending module comprises:
the first trigger connection unit is used for connecting the clock input end of the D trigger cluster with the output end of the D trigger cluster when the second clock signal is at a low level;
the upper computer control end sends a second clock signal to the clock input end of the D trigger cluster again;
a flip-flop sending unit, where the second clock signal changes from a low level to a high level, a clock input end of the D flip-flop cluster sends control data in the storage register to an output end of the D flip-flop cluster, and an output end Q of the D flip-flop cluster1Q8 each comprise 8 outputs.
In a third aspect, an embodiment of the present application provides a computer device, including a memory, a processor, and a computer program stored on the memory and executable on the processor, where the processor implements the steps of the method for multiplexing the shift register according to any one of claims 1 to 6 when executing the computer program.
In a fourth aspect, the present application provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the steps of the method for multiplexing the shift register.
The beneficial effect of this application mainly lies in: according to the application, the control end of the upper computer shifts the received control data to the multi-path storage register through the first clock signal serial shift register, so that the serial-parallel conversion function is realized, and the driving capability of the integrated circuit is improved; the control data which are serially shifted into the storage register are sent to a D trigger cluster through a second clock signal, the D trigger cluster not only can store the control data, but also has a shifting function, and the digital codes corresponding to the control data are sequentially sent to a last output end from a first bit according to the second clock signal, so that the working mode of serial input and serial output of the D trigger cluster is realized; the third clock signal is sent to the clock input end of the D trigger cluster, when the third clock signal is changed from a low level to a high level, any output end of the D trigger output end sends control data to the receiving end of the external component device through the PIN interface, and the on or off of various measuring devices of the aerospace ground station is remotely controlled; according to the method and the device, the serial shift register is selected to receive the multi-bit control data, and then the received control data is output through the D trigger cluster output end, so that the serial-parallel conversion function is realized, the working efficiency of the integrated circuit is improved, the power consumption of a chip is reduced, and the utilization rate of clock signals is improved.
In order to make the aforementioned objects, features and advantages of the present application more comprehensible, preferred embodiments accompanied with figures are described in detail below.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are required to be used in the embodiments will be briefly described below, it should be understood that the following drawings only illustrate some embodiments of the present application and therefore should not be considered as limiting the scope, and for those skilled in the art, other related drawings can be obtained from the drawings without inventive effort.
Fig. 1 shows a flow chart of a method for multiplexing output of a shift register according to an embodiment of the present application.
Fig. 2 is a schematic diagram illustrating a flow of storage register transmission control data provided in an embodiment of the present application.
Fig. 3 shows a schematic diagram illustrating a flow of sending control data at a clock input end of a D flip-flop cluster according to an embodiment of the present application.
Fig. 4 shows a schematic flow chart of receiving control data by an external component device according to an embodiment of the present application.
Fig. 5 shows a schematic diagram of a shift register provided in an embodiment of the present application.
Fig. 6 shows a schematic diagram of a D flip-flop provided in an embodiment of the present application.
Fig. 7 shows a schematic structural diagram of a demultiplexer of a shift register according to an embodiment of the present application.
Fig. 8 shows a schematic structural diagram of a computer device provided in an embodiment of the present application.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some embodiments of the present application, but not all embodiments. The components of the embodiments of the present application, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations and, thus, the following detailed description of the embodiments of the present application, which is provided in the figures, is not intended to limit the scope of the claimed application, but is merely representative of selected embodiments of the application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Because the satellite ground station measurement and control equipment is numerous, a large number of input/output (I/O) interfaces are needed for controlling the external component equipment of the satellite ground station, for the measurement and control system of the satellite ground station, the input/output interfaces are precious, and a large number of interfaces are utilized to be not compensated, therefore, a serial shift register is selected to receive multi-bit data, the received data is output through an independent input/output interface, the serial-parallel conversion function is realized, the working efficiency of an integrated circuit is improved, the power consumption of a chip is reduced, and the utilization rate of clock signals is improved.
The method comprises the steps that a control end of an upper computer responds to an operation instruction of a technician and sends a first clock signal to a clock input end of a shift register, wherein the first clock signal is a multi-stage delay signal; when the first clock signal is changed from low level to high level, the shift register sends control data to the storage register; the output end of the storage register sends the control data to the clock input end of the D trigger cluster; the upper computer control end responds to a technician operation instruction and sends a second clock signal to the clock input end of the D trigger cluster, wherein the second clock signal is a multi-stage delay signal; when the second clock signal is changed from the low level to the high level, the clock input end of the D trigger cluster sends the control data to the output end of the D trigger cluster; the upper computer control end responds to an operation instruction of a technician and sends a third clock signal to the clock input end of the D trigger cluster, wherein the third clock signal is a multi-stage delay signal; when the third clock signal transitions from the low level to the high level, the D flip-flop output terminal transmits the control data to the external component device. Specifically, the upper computer control end sends a first clock signal to be conducted with the clock input end of the shift register, when the first clock signal is converted from a low level to a high level, a rising edge is completed, control data are sent to the storage register from the shift register, and the received control data are shifted to the multi-path storage register through the first clock signal serial shift register, so that the serial-parallel conversion function is realized, and the driving capability of the integrated circuit is improved; sending the second clock signal to a clock input end of the D trigger cluster, and when the second clock signal is changed from a low level to a high level, sending the control data to an output end of the D trigger cluster by the clock input end of the D trigger cluster; the control data serially shifted into the storage register is sent to the D trigger cluster through a second clock signal, the clock input end of the D trigger cluster is communicated with the output end of the D trigger cluster, the D trigger cluster not only can store the control data, but also has a shifting function, and the digital codes corresponding to the control data are sequentially sent to the last output end from the first bit according to the second clock signal, so that the working modes of serial input and serial output of the D trigger cluster are realized; sending a third clock signal to a clock input end of the D trigger cluster, finishing a rising edge when the third clock signal is changed from a low level to a high level, and sending control data to a receiving end of external component equipment by any output end of the D trigger output end through a PIN interface so as to realize remote control on the starting or the closing of various measuring equipment of the aerospace ground station; in addition, for a measurement and control system of a satellite ground station, an input/output interface is precious, and a large number of interfaces are utilized and cannot be consumed, so that the serial shift register is selected to receive multi-bit control data, the received control data are output through the output end of the D trigger cluster, the serial-parallel conversion function is realized, the working efficiency of an integrated circuit is improved, the power consumption of a chip is reduced, and the utilization rate of clock signals is improved.
Some embodiments of the present application will be described in detail below with reference to the accompanying drawings. The embodiments described below and the features of the embodiments can be combined with each other without conflict.
Fig. 1 is a schematic flowchart illustrating a method for multiplexing output of a shift register according to an embodiment of the present disclosure; as shown in fig. 1, the multiplexing of the shift register specifically includes the following steps:
and step S10, the upper computer control end responds to the operation instruction of the technician and sends a first clock signal to the clock input end of the shift register, wherein the first clock signal is a multi-stage delay signal.
In the specific implementation of step S10, in response to an operation instruction of a technician, any output pin of the CPU at the control end of the upper computer is connected to the clock input end of the shift register, and sends the first clock signal to the clock input end of the shift register.
In step S20, the shift register sends control data to the storage register when the first clock signal transitions from the low level to the high level.
In the specific implementation of step S20, the upper computer control end sends the first clock signal a low level, any output pin of the upper computer control end is connected to the data input end of the shift register, and the shift register sends the control data to the storage register when the first clock signal changes to a high level after a delay of tens of microseconds.
And step S30, the output end of the storage register sends the control data to the clock input end of the D trigger cluster, and the D trigger cluster consists of 8D triggers.
In step S30, when the method is implemented, the output Q of the storage register is stored1-Q8Clock input end D of D flip-flop cluster1-D8Parallel arranged, storing the output Q of the register1-Q8Clock input terminal D for transmitting control data to D flip-flop cluster1-D8The clock input end of the D flip-flop cluster is used for receiving 8 paths of control data output by the storage register, and the D flip-flop cluster is composed of 8D flip-flops.
And step S40, the upper computer control end responds to the operation instruction of the technician and sends a second clock signal to the clock input end of the D trigger cluster, wherein the second clock signal is a multi-stage delay signal.
In specific implementation, in response to an operation instruction of a technician, any output pin of the upper computer control terminal sends the second clock signal to the clock input terminal of the D flip-flop cluster, and the upper computer control terminal is conducted with the clock input terminal of the D flip-flop cluster.
Step S50 the clock input terminal of the D flip-flop cluster sends the control data to the output terminal of the D flip-flop cluster when the second clock signal transitions from the low level to the high level.
When the step S50 is implemented specifically, any output pin of the upper computer control end sends a low level to the second clock signal, the clock input end of the D flip-flop cluster is connected to the output end of the D flip-flop cluster, any output pin of the upper computer control end sends a high level to the second clock signal, the second clock signal completes a rising edge, and the clock input end D of the D flip-flop cluster1-D8Output Q for sending control data to D flip-flop cluster1-Q8。
And step S60, the upper computer control end responds to an operation instruction of a technician and sends a third clock signal to the clock input end of the D trigger cluster, wherein the third clock signal is a multi-stage delay signal.
In the specific implementation of step S60, in response to an operation instruction of a technician, any output pin of the upper computer control end sends a third clock signal to the clock input end of the D flip-flop cluster, and the clock input end D of the D flip-flop cluster1-D8And the output Q of the memory register1-Q8 is turned on, and the clock input of the D flip-flop cluster is used for receiving the output Q of the memory register1Control data sent by Q8.
In step S70, when the third clock signal transitions from the low level to the high level, the output terminal of the D flip-flop cluster transmits the control data to the external component device.
In step S70, when the method is implemented, any output pin of the upper computer control end sends a third clock signal to the output end Q of the D flip-flop cluster1-Q8When the third clock signal goes from low level to high level, one is completedOutput Q of a rising edge, D flip-flop cluster1-Q8Sends the control data to the external component device, wherein the output Q of the D flip-flop cluster1The Q8 comprises 8 outputs, and 64 outputs are connected with external component equipment for controlling the on or off of the external equipment.
In a possible implementation, in step S10, the sending, by the upper computer control terminal, the first clock signal to the input terminal of the shift register clock in response to the technician operation instruction includes:
and 101, outputting a 3.3V voltage to a power supply VCC pin of the shift register by a DC/DC chip in the upper computer control end for power supply.
Step 102, responding to an operation instruction of a technician, sending a first clock signal to a clock input end of the shift register by any output pin of the upper computer control end.
In the specific implementation of steps 101 and 102, the upper computer control terminal selects a direct current power supply 5V voltage for power supply, the 5V voltage outputs 3.3V voltage to the power supply VCC pin of the shift register through the DC/DC chip, the enable terminal G of the shift register is connected to ground, the data clear terminal MR of the shift register is at a low level, and in response to an operation instruction of a technician, any output pin of the upper computer control terminal sends a first clock signal to the clock input terminal of the shift register, wherein the DC/DC chip is connected in series with a divider resistor R.
In a possible implementation, in the step S20, when the first clock signal changes from a low level to a high level, the shift register sends the control data to the storage register, which includes the following steps:
step 201, when the first clock signal changes from low level to high level, the shift register sends the control data to the output end Q of the storage register1Performing the following steps;
step 202, responding to an operation instruction of a technician, and sending the first clock signal to the clock input end of the shift register again by the upper computer control end;
step 203, when the retransmitted first clock signal is changed from a low level to a high level, the stepOutput Q of the memory register1Shifting control data to the output Q of the memory register2And storing the control data generated this time to the output end Q of the storage register1Performing the following steps;
step 204, responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the third time;
step 205, when the first clock signal transmitted for the third time changes from low level to high level, the output end Q of the storage register2Shifting control data to the output Q of the memory register3And storing the control data generated this time to the output end Q of the storage register2Performing the following steps;
step 206, responding to an operation instruction of a technician, the upper computer control end sends a first clock signal to the clock input end of the shift register for the fourth time;
step 207, when the first clock signal of the fourth transmission changes from low level to high level, the output end Q of the storage register3Shifting control data to the output Q of the memory register4And storing the control data generated this time to the output end Q of the storage register3Performing the following steps;
step 208, responding to an operation instruction of a technician, sending a first clock signal to a clock input end of the shift register by the upper computer control end for the fifth time;
step 209, when the fifth transmitted first clock signal changes from low level to high level, the output Q of the storage register4Shifting control data to the output Q of the memory register5And storing the control data generated this time to the output end Q of the storage register4Performing the following steps;
step S2010, responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the sixth time;
in step 2011, when the first clock signal sent at the sixth time transitions from low to high, the output terminal of the storage register is assertedQ5Shifting control data to the output Q of the memory register6And storing the control data generated this time to the output end Q of the storage register5Performing the following steps;
step 2012, responding to the operation instruction of the technician, the upper computer control end sends the first clock signal to the clock input end of the shift register for the seventh time;
step 2013, when the first clock signal sent for the seventh time is changed from low level to high level, the output end Q of the storage register6Shifting control data to the output Q of the memory register7And storing the control data generated this time to the output end Q of the storage register6Performing the following steps;
step 2014, in response to the operation instruction of the technician, the upper computer control end sends the first clock signal to the clock input end of the shift register for the eighth time;
step 2015, when the first clock signal sent for the eighth time is changed from low level to high level, the output Q of the storage register is connected to the output Q of the storage register7Shifting control data to the output Q of the memory register8And storing the control data generated this time to the output end Q of the storage register7Performing the following steps;
in the specific implementation of steps 201, 202, 203, 204, 205, 206, 207, 208, 209, 2010, 2011, 2012, 2013, 2014, 2015, when the first clock signal is at a low level, the data input terminal of the shift register is conducted with the clock input terminal of the storage register and the output terminal of the storage register, and when the first clock signal is at a high level, the shift register shifts the control data to the output terminal Q of the storage register1In response to an operation instruction of a technician, the upper computer control end sends the first clock signal to the clock input end of the shift register again; when the retransmitted first clock signal transits from a low level to a high level, the output terminal Q of the storage register1Shifting control data to the output Q of the memory register2And storing the control data generated this time to the output end Q of the storage register1Performing the following steps; responding to operating instructions of a technicianThe upper computer control end sends a first clock signal to the clock input end of the shift register for the third time; when the first clock signal transmitted for the third time is transited from the low level to the high level, the output end Q of the storage register2Shifting control data to the output Q of the memory register3And storing the control data generated this time to the output end Q of the storage register2Performing the following steps; responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register for the fourth time by the upper computer control end; when the first clock signal of the fourth transmission is transited from the low level to the high level, the output end Q of the storage register3Shifting control data to the output Q of the memory register4And storing the control data generated this time to the output end Q of the storage register3Performing the following steps; responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the fifth time; when the fifth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register4Shifting control data to the output Q of the memory register5And storing the control data generated this time to the output end Q of the storage register4Performing the following steps; responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the sixth time; when the sixth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register5Shifting control data to the output Q of the memory register6And storing the control data generated this time to the output end Q of the storage register5Performing the following steps; responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the seventh time; when the seventh transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register6Shifting control data to the output Q of the memory register7And storing the control data generated this time to the output end Q of the storage register6Performing the following steps; responding to technician's operating instructions, up-ratingThe control end sends a first clock signal to the clock input end of the shift register for the eighth time; when the eighth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register7Shifting control data to the output Q of the memory register8And storing the control data generated this time to the output end Q of the storage register7The operating principle of the shift register is shown in fig. 5.
In one possible implementation, fig. 2 shows a schematic diagram of a flow of storage register transmission control data provided by an embodiment of the present application; in the step S30, the step of sending the control data to the clock input end of the D flip-flop cluster by the output end of the storage register specifically includes the following steps:
step S301, a DC/DC chip in the upper computer control end outputs 3.3V voltage to a power pin of the D trigger cluster, an enabling end of the D trigger cluster is directly grounded, and the D trigger cluster is effective in low level.
Step S302, the output end Q of the storage register1-Q8Clock input terminal D for transmitting control data to D flip-flop cluster1-D8Wherein the output Q of the memory register1-Q8Respectively connected with clock input ends D of D flip-flop clusters1-D8And conducting.
When the steps S301 and S302 are specifically implemented, the DC/DC chip in the upper computer control terminal outputs 3.3V voltage to the power pin of the D flip-flop, the upper computer control terminal is connected to the D flip-flop, the enable input terminal of the D flip-flop is directly grounded, the data clear terminal of the D flip-flop is active at low level, the output terminal of the storage register is connected to the clock input terminal of the D flip-flop cluster, and the clock input terminal D of the D flip-flop cluster is connected to the clock input terminal D1-D8Output Q for receiving a memory register1-Q8According to the control data in the method, the DC/DC chip is connected with a divider resistor R in series, and the voltage of 5V at the control end of the upper computer is reduced to 3.3V.
In a possible implementation, in step S40, the sending, by the upper computer control end, a second clock signal to the clock input end of the D flip-flop cluster in response to the technician operation instruction, where the second clock signal is a multi-stage delay signal, and the method includes:
and 40, in specific implementation, responding to an operation instruction of a technician, sending a second clock signal to a clock input end of the D trigger cluster by the upper computer control end, and conducting the upper computer control end and the D trigger cluster.
In a possible implementation scheme, fig. 3 shows a schematic diagram of a flow of sending control data at a clock input end of a D flip-flop cluster provided in an embodiment of the present application; in the step S50, when the second clock signal changes from the low level to the high level, the clock input terminal of the D flip-flop cluster sends the control data to the output terminal of the D flip-flop cluster, which specifically includes the following steps:
in step S501, when the second clock signal is at a low level, the clock input end of the D flip-flop cluster is connected to the output end of the D flip-flop cluster.
Step S502, the upper computer control end sends the second clock signal to the clock input end of the D flip-flop cluster again.
Step S503, the second clock signal is changed from low level to high level, the clock input end of the D flip-flop cluster sends the control data in the storage register to the output end of the D flip-flop cluster, wherein the output end Q of the D flip-flop cluster1Q8 each comprise 8 outputs.
In specific implementation of steps S501, S502, and S503, any output pin of the control end of the upper computer sends the second clock signal to the clock input end D of the D flip-flop cluster1-D8The upper computer control end outputs a low level to the second clock signal, responds to the second clock signal, and the clock input end D of the D trigger cluster1-D8And the output Q of the D flip-flop cluster1-Q8 is turned on, and in response to an operation instruction of a technician, any output pin of the control terminal of the upper computer sends the second clock signal to change from low level to high level again, the second clock signal completes one rising edge, and the clock input terminal D of the D flip-flop cluster1-D8Output end Q for transmitting control data in storage register to D trigger cluster1-Q8。
For example:when the second clock signal CP received by the clock input terminal of the D flip-flop cluster is 1 (1 is high), D2＝Q1I.e. clock input D of D flip-flop2And the output Q of the D flip-flop cluster1Turning on, under the action of the second clock signal, the clock input end of the D flip-flop cluster shifts the control data received from the storage register in right direction, otherwise, when the second clock signal CP is equal to 0, D shifts the control data in right direction1＝Q1，D2＝Q2，Under the action of the second clock signal, the output end Q of the D flip-flop cluster2And Q1And performing left shift, controlling the data to be shifted to the right when CP is 1, and controlling the data to be shifted to the left when CP is 0, so as to realize the working mode of serial input and serial output of the D flip-flop cluster, wherein the principle of the D flip-flop is shown in fig. 6.
In addition, the D trigger cluster is composed of 8D triggers, the D trigger cluster not only can store control data, but also has a shift function, the shift function is an important function in digital circuits and computers, the data end of each D trigger is cleared before use, and the digital codes corresponding to the control data are sequentially sent to the output end of the last bit from the first bit according to the second clock signal of the pulse.
In a possible implementation, in step S60, the sending, by the upper computer control end, a third clock signal to the clock input end of the D flip-flop cluster in response to an operation instruction of a technician, where the third clock signal is a multi-stage delay signal, and includes:
in step 60, in specific implementation, in response to an operation instruction of a technician, the upper computer control end sends a third clock signal to the clock input end D of the D flip-flop cluster1-D8Clock input terminal of D flip-flop cluster and output terminal Q of D flip-flop cluster1-Q8 is on and the third clock control signal is used to control the output Q of the D flip-flop cluster1-control data output of Q8.
In one possible implementation, fig. 4 shows a schematic flow chart of receiving control data by an external component device according to an embodiment of the present application; in the step S70, when the third clock signal changes from the low level to the high level, the output terminal of the D flip-flop cluster sends the control data to the external component device, which specifically includes the following steps:
step S701, the upper computer control end sends a third clock signal to an output end Q of the D trigger cluster1-Q8。
Step S702, when the third clock signal goes from low level to high level, the output end Q of the D flip-flop cluster1-Q8Any output end of the D trigger cluster sends the control data to the external component equipment, wherein the output end of any D trigger cluster is connected with the multiple external component equipment.
When the steps S701 and S702 are implemented specifically, the upper computer control end sends the third clock signal to the output end Q of the D flip-flop1-Q8In response to the third clock signal, the D flip-flop output Q1-Q8Is connected with external component equipment through a PIN interface, wherein, the output end Q of the D trigger1-Q8Each PIN interface comprises 8 output PIN interfaces which are connected with 64 external component devices; when the control end of the upper computer sends a process of changing from low level to high level to the third clock signal, the output end Q of the D trigger1-Q8D flip-flop output end Q after finishing rising edge once1-Q8Any output end of the control module sends the control data to a receiving end of external component equipment through a PIN interface, and opening or closing of various measuring equipment of the aerospace ground station is remotely controlled.
For example: the upper computer control end sends the process of converting the low level into the high level to the output end Q of the D trigger through a third clock signal4The output end of the other D flip-flops is still 0, namely 000, Q4＝0001, the upper computer control end sends the process of converting the third clock signal from the low level to the high level to the output end Q of the D trigger3Output terminal, Q3＝1、Q41, and Q2＝Q10; after the high level is converted from the low level by the third clock signal for four times, Q is obtained4 Q3Q2 Q1＝1101, if the output end of the D flip-flop cluster is 1, transmitting the control data to the receiving end of the external component device through the PIN interface, and simultaneously turning onAnd starting the corresponding external component equipment.
Fig. 7 is a schematic diagram illustrating a structure of a multi-output device of a shift register according to an embodiment of the present application, where as shown in fig. 7, the device includes:
a first signal module 801, where the upper computer control end responds to a technician operation instruction and sends a first clock signal to the clock input end of the shift register, where the first clock signal is a multi-stage delay signal;
a first sending module 802, when the first clock signal changes from low level to high level, the upper computer control end sends the control data in the shift register to the storage register;
a second sending module 803, where the output end of the storage register sends the control data of the control end of the upper computer to the clock input end of the D flip-flop cluster, and the D flip-flop cluster is composed of 8D flip-flops;
a second signal module 804, where the upper computer control end responds to a technician operation instruction and sends a second clock signal to the clock input end of the D flip-flop cluster, where the second clock signal is a multi-stage delay signal;
a third sending module 805, configured to send the control data to the output end of the D flip-flop cluster through the clock input end of the D flip-flop cluster when the second clock signal changes from the low level to the high level;
a third signal module 806, where the upper computer control end responds to an operation instruction of a technician, and sends a third clock signal to the clock input end of the D flip-flop cluster, where the third clock signal is a multi-stage delay signal;
the fourth transmitting module 807 transmits the control data to the external component device at the D flip-flop output terminal when the third clock signal transitions from the low level to the high level.
The apparatus provided in the embodiments of the present application may be specific hardware on a device, or software or firmware installed on a device, etc. The device provided by the embodiment of the present application has the same implementation principle and technical effect as the foregoing method embodiments, and for the sake of brief description, reference may be made to the corresponding contents in the foregoing method embodiments where no part of the device embodiments is mentioned. It is clear to those skilled in the art that, for convenience and brevity of description, the specific working processes of the foregoing systems, apparatuses and units may refer to the corresponding processes in the foregoing method embodiments, and are not described herein again.
Corresponding to the method for multiplexing the shift register in fig. 1, the embodiment of the present application further provides a computer device 90, as shown in fig. 8, the device includes a memory 901, a processor 902, and a computer program stored in the memory 901 and executable on the processor 902, wherein the above method is implemented when the above computer program is executed by the above processor 902.
The upper computer control end responds to a technician operation instruction and sends a first clock signal to the clock input end of the shift register, wherein the first clock signal is a multi-stage delay signal;
when the first clock signal is changed from low level to high level, the shift register sends control data to the storage register;
the output end of the storage register sends control data to the clock input end of a D trigger cluster, and the D trigger cluster consists of 8D triggers;
the upper computer control end responds to a technician operation instruction and sends a second clock signal to the clock input end of the D trigger cluster, wherein the second clock signal is a multi-stage delay signal;
when the second clock signal is changed from the low level to the high level, the clock input end of the D trigger cluster sends the control data to the output end of the D trigger cluster;
the upper computer control end responds to an operation instruction of a technician and sends a third clock signal to the clock input end of the D trigger cluster, wherein the third clock signal is a multi-stage delay signal;
when the third clock signal transitions from a low level to a high level, the output of the D flip-flop cluster transmits the control data to the external component device.
Corresponding to the method for multiplexing the shift register in fig. 1, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored, where the computer program is executed by a processor to perform the following steps:
the upper computer control end responds to a technician operation instruction and sends a first clock signal to the clock input end of the shift register, wherein the first clock signal is a multi-stage delay signal;
when the first clock signal is changed from low level to high level, the shift register sends control data to the storage register;
the output end of the storage register sends control data to the clock input end of a D trigger cluster, and the D trigger cluster consists of 8D triggers;
the upper computer control end responds to a technician operation instruction and sends a second clock signal to the clock input end of the D trigger cluster, wherein the second clock signal is a multi-stage delay signal;
when the second clock signal is changed from the low level to the high level, the clock input end of the D trigger cluster sends the control data to the output end of the D trigger cluster;
the upper computer control end responds to an operation instruction of a technician and sends a third clock signal to the clock input end of the D trigger cluster, wherein the third clock signal is a multi-stage delay signal;
when the third clock signal transitions from a low level to a high level, the output of the D flip-flop cluster transmits the control data to the external component device.
In the embodiments of the present application, when being executed by a processor, the computer program may further execute other machine-readable instructions to perform other methods described in the present application, and for specific implementation steps and principles, reference is made to the above description, which is not repeated herein in detail.
In the embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other ways. The above-described embodiments of the apparatus are merely illustrative, and for example, the division of the units is only one logical division, and there may be other divisions when actually implemented, and for example, a plurality of units or components may be combined or integrated into another system, or some features may be omitted, or not executed. In addition, the shown or discussed mutual coupling or direct coupling or communication connection may be an indirect coupling or communication connection of devices or units through some communication interfaces, and may be in an electrical, mechanical or other form.
The units described as separate parts may or may not be physically separate, and parts displayed as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units can be selected according to actual needs to achieve the purpose of the solution of the embodiment.
In addition, functional units in the embodiments provided in the present application may be integrated into one processing unit, or each unit may exist alone physically, or two or more units are integrated into one unit.
The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application or portions thereof that substantially contribute to the prior art may be embodied in the form of a software product stored in a storage medium and including instructions for causing a computer device (which may be a personal computer, a server, or a network device) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus once an item is defined in one figure, it need not be further defined and explained in subsequent figures, and moreover, the terms "first", "second", "third", etc. are used merely to distinguish one description from another and are not to be construed as indicating or implying relative importance.
Finally, it should be noted that: the above-mentioned embodiments are only specific embodiments of the present application, and are used for illustrating the technical solutions of the present application, but not limiting the same, and the scope of the present application is not limited thereto, and although the present application is described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: any person skilled in the art can modify or easily conceive the technical solutions described in the foregoing embodiments or equivalent substitutes for some technical features within the technical scope disclosed in the present application; such modifications, changes or substitutions do not depart from the spirit and scope of the present disclosure, which should be construed in light of the above teachings. Are intended to be covered by the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims (10)

1. A method for multiplexing output from a shift register, the method comprising:
the upper computer control end responds to a technician operation instruction and sends a first clock signal to the clock input end of the shift register, wherein the first clock signal is a multi-stage delay signal;
when a first clock signal transits from a low level to a high level, the shift register transmits control data into the storage register;
the output end of the storage register sends control data to the clock input end of a D trigger cluster, and the D trigger cluster consists of 8D triggers;
the upper computer control end responds to a technician operation instruction and sends a second clock signal to the clock input end of the D trigger cluster, wherein the second clock signal is a multi-stage delay signal;
when the second clock signal is changed from low level to high level, the clock input end of the D trigger cluster sends control data to the output end of the D trigger cluster;
the upper computer control end responds to an operation instruction of a technician and sends a third clock signal to the clock input end of the D trigger cluster, wherein the third clock signal is a multi-stage delay signal;
the output of the D flip-flop cluster transmits the control data to an external component device when the third clock signal transitions from a low level to a high level.
2. The method of claim 1, wherein sending a first clock signal from the host computer control terminal to the input of the shift register clock in response to a technician operation command comprises:
a DC/DC chip in the upper computer control end outputs 3.3V voltage to supply power to a power supply VCC pin of the shift register;
and responding to an operation instruction of a technician, and sending the first clock signal to the clock input end of the shift register by any output pin of the upper computer control end.
3. The method of claim 1, wherein the shift register sends control data into the storage register when the first clock signal transitions from a low level to a high level, comprising:
when the first clock signal transits from the low level to the high level, the shift register transmits the control data to the output terminal Q of the storage register1Performing the following steps;
responding to an operation instruction of a technician, and sending the first clock signal to the clock input end of the shift register again by the upper computer control end;
when the retransmitted first clock signal transits from a low level to a high level, the output terminal Q of the storage register1Shifting control data to the output Q of the memory register2And storing the control data generated this time to the output end Q of the storage register1Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register for the third time by the upper computer control end;
when the first clock signal transmitted for the third time is transited from the low level to the high level, the output end Q of the storage register2Shifting control data to the output Q of the memory register3And storing the control data generated this time to the output end Q of the storage register2Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register for the fourth time by the upper computer control end;
when the first clock signal of the fourth transmission is transited from the low level to the high level, the output end Q of the storage register3Shifting control data to the output Q of the memory register4And storing the control data generated this time to the output end Q of the storage register3Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the fifth time;
when the fifth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register4Shifting control data to the output Q of the memory register5And storing the control data generated this time to the output end Q of the storage register4Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the sixth time;
when the sixth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register5Shifting control data to the output Q of the memory register6And storing the control data generated this time to the output end Q of the storage register5Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the seventh time;
when the seventh transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register6Shifting control data to the output Q of the memory register7And storing the control data generated this time to the output end of the storage registerQ6Performing the following steps;
responding to an operation instruction of a technician, and sending a first clock signal to a clock input end of the shift register by the upper computer control end for the eighth time;
when the eighth transmitted first clock signal transits from the low level to the high level, the output terminal Q of the storage register7Shifting control data to the output Q of the memory register8And storing the control data generated this time to the output end Q of the storage register7In (1).
4. The method of claim 1, wherein the output of the storage register sends control data to a clock input of a cluster of D flip-flops, the cluster of D flip-flops comprising 8D flip-flops, comprising:
a DC/DC chip in the upper computer control end outputs 3.3V voltage to a power pin of a D trigger cluster, an enabling end of the D trigger cluster is directly grounded, and the D trigger cluster is effective in low level;
output Q of the memory register1-Q8Clock input terminal D for transmitting control data to D flip-flop cluster1-D8Wherein the output Q of the memory register1-Q8Respectively connected with clock input ends D of D flip-flop clusters1-D8And conducting.
5. The method of claim 1, wherein the clock input of the D flip-flop cluster sending control data to the output of the D flip-flop cluster when the second clock signal transitions from a low level to a high level, comprising:
when the second clock signal is at a low level, the clock input end of the D trigger cluster is communicated with the output end of the D trigger cluster;
the upper computer control end sends a second clock signal to the clock input end of the D trigger cluster again;
the second clock signal is changed from low level to high level, and the clock input end of the D flip-flop cluster is used for storing a registerThe intermediate control data are sent to the output end of the D trigger cluster, wherein the output end Q of the D trigger cluster1Q8 each comprise 8 outputs.
6. The method of claim 1, wherein the output of the D flip-flop cluster sends the control data to an external component device when a third clock signal transitions from a low level to a high level, comprising:
the upper computer control end sends a third clock signal to the output end Q of the D trigger1-Q8；
When the third clock signal goes from low level to high level, the output end Q of the D trigger1-Q8Any output end of the D flip-flop sends the control data to the external component equipment, wherein the output end of any D flip-flop is connected with the multiple paths of external component equipment.
7. A demultiplexer for a shift register, the apparatus comprising:
the first signal module is used for responding to an operation instruction of a technician by an upper computer control end and sending a first clock signal to a clock input end of the shift register, wherein the first clock signal is a multi-stage delay signal;
a first transmitting module for transmitting control data to the storage register by the shift register when a first clock signal transits from a low level to a high level;
the second sending module is used for sending the control data to the clock input end of a D trigger cluster by the output end of the storage register, and the D trigger cluster consists of 8D triggers;
the second signal module is used for responding to an operation instruction of a technician by the control end of the upper computer and sending a second clock signal to the clock input end of the D trigger cluster, wherein the second clock signal is a multi-stage delay signal;
the third sending module is used for sending the control data to the output end of the D trigger cluster by the clock input end of the D trigger cluster when the second clock signal is changed from the low level to the high level;
the third signal module is used for responding to an operation instruction of a technician by the control end of the upper computer and sending a third clock signal to the clock input end of the D trigger cluster, wherein the third clock signal is a multi-stage delay signal;
and the fourth sending module is used for sending the control data to the external component device by the output end of the D flip-flop cluster when the third clock signal is changed from the low level to the high level.
8. The apparatus of claim 7, wherein the third sending module comprises:
the first trigger connection unit is used for connecting the clock input end of the D trigger cluster with the output end of the D trigger cluster when the second clock signal is at a low level;
the trigger second connection unit is used for sending a second clock signal to the clock input end of the D trigger cluster again by the control end of the upper computer;
a flip-flop sending unit, configured to change the second clock signal from a low level to a high level, where a clock input end of the D flip-flop cluster sends the control data in the storage register to an output end of the D flip-flop cluster, and an output end Q of the D flip-flop cluster1Q8 each comprise 8 outputs.
9. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the steps of the method of any of the preceding claims 1 to 6 are implemented by the processor when executing the computer program.
10. A computer-readable storage medium, having stored thereon a computer program which, when being executed by a processor, is adapted to carry out the steps of the method according to any one of claims 1 to 6.
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