CN110310590A - A kind of control chip of LED display drive system - Google Patents
A kind of control chip of LED display drive system Download PDFInfo
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- CN110310590A CN110310590A CN201910523013.XA CN201910523013A CN110310590A CN 110310590 A CN110310590 A CN 110310590A CN 201910523013 A CN201910523013 A CN 201910523013A CN 110310590 A CN110310590 A CN 110310590A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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- Computer Hardware Design (AREA)
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- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The embodiment of the invention discloses a kind of control chips of LED display drive system, belong to field of LED drive technology.It controls chip and is equipped with combinatorial shifting register, the combinatorial shifting register includes level signal input pin, at least two 2-bit shift registers, clock signal input pin and data-out pin: the 2-bit shift register is equipped with DIR pin, CLK pin, DIN pin and first control signal output pin and second control signal output pin, the DIR pins in parallel of each 2-bit shift register is simultaneously connected with the level input pin, the level signal input pin is used to control the first control signal output pin by reception high level or low level signal and whether the control signal of second control signal output pin output is identical, to realize the selection for the operating mode for controlling chip.Using the embodiment of the present invention, the purpose of different working modes can be supported by realizing a control chip.
Description
Technical field
The present embodiments relate to field of LED drive technology more particularly to a kind of control cores of LED display drive system
Piece.
Background technique
LED (light emitting diode, light emitting diode) is a kind of New Solid semiconductor light source, is answered extensively
In lighting circuit, backlight module or display panel.LED drive chip is to drive LED luminous or the normal work of LED module component
The power supply of work adjusts electronic device.According to the control core for the LED drive system that different application demands needs to have different editions
Piece, such as common 4 channel control chip and 8 channels control chip, and in the prior art, the control chip of particular version can only be supported
A kind of operating mode, such as can only support 4 channel patterns or 8 channel patterns, so that the design cost of control chip and production
Higher cost.
Summary of the invention
In view of this, a kind of control chip for being designed to provide LED display drive system of the embodiment of the present invention, with
The control chip for solving the particular version of the prior art can only support a kind of operating mode, so that LED display drive system
Control the design cost and the higher problem of production cost of chip.
It is as follows that the embodiment of the present invention solves technical solution used by above-mentioned technical problem:
Control chip described in a kind of control chip of LED display drive system is provided and is equipped with combinatorial shifting register, institute
Stating combinatorial shifting register includes level signal input pin, at least two 2-bit shift registers, clock signal input pin
And data-out pin:
The 2-bit shift register is equipped with DIR pin, CLK pin, DIN pin and first control signal output pin
It is connect with second control signal output pin, the DIR pins in parallel of each 2-bit shift register and with the level input pin
Logical, the CLK pin of each 2-bit shift register is in parallel and connects in the clock signal input pin, each 2-bit shift LD
The DIN pin serial connection of device is simultaneously connected with the data-out pin；
Wherein, the level signal input pin is used to control first control by receiving high level or low level signal
Whether the control signal of signal output pin and second control signal output pin output processed is identical, to realize control chip
The selection of operating mode.
Preferably, the 2-bit shift register includes the first d type flip flop and the second d type flip flop, and each d type flip flop is equal
Equipped with D pin, ck pin, Q pin and set pin:
The set pin of first d type flip flop 201 with after the set pins in parallel of second d type flip flop 202 with it is described
The DIR pin of 2-bit shift register connects；
After the ck pins in parallel of the ck pin of first d type flip flop 201 and second d type flip flop 202 with the 2-
The CLK pin of bit shift register connects；
The D pin of first d type flip flop 201 is connect with the DIN pin of the 2-bit shift register；
The Q pin of first d type flip flop 201 is moved with the D pin of second d type flip flop 202 and the 2-bit respectively
The first control signal output pin of bit register connects；
The Q pin of second d type flip flop 202 is exported with the second control signal of the 2-bit shift register respectively
Pin is connected with data output pins.
Preferably, the combinatorial shifting register is set there are four 2-bit shift register.
Preferably, the level signal input pin reception high level signal, the first of each 2-bit shift register
It is different from the control signal that second control signal output pin exports to control signal output pin, the control chip operation mode
For 8 channels operation modes.
5, the control chip of LED display drive system as claimed in claim 4, which is characterized in that the level letter
Number input pin receives high level signal by powering on voltage.
Preferably, the level signal input pin reception low level signal, the first of each 2-bit shift register
It is identical as the control signal that second control signal output pin exports to control signal output pin, the control chip operation mode
For 4 channels operation modes.
Preferably, the level signal input pin receives low level signal by ground connection.
Preferably, the control chip further includes buffer, multichannel timing generates and control unit and gate control unit:
The shift register is generated with the buffer and the multichannel timing by bit line and is connected to control unit；
The multichannel timing generation is connected to by bit line with the gate control unit with control unit；
The multichannel timing, which is generated, is equipped with chip select functionality multiplexing pins with control unit, and the chip select functionality multiplexing pins are used
In receiving high level or low level signal, to select the operating mode of the control chip.
Preferably, the LED display driving circuit is additionally provided with protection circuit, the protection circuit respectively with the caching
Device, the generation of multichannel timing are connect with control unit and gate control unit.
The control chip of the LED display drive system of the embodiment of the present invention, equipped with the combination of channel selecting can be supported to move
Bit register, the shift register are provided with level signal input pin, at least two 2-bit shift registers, clock signal
Input pin and data-out pin, and the received level signal of level signal input pin and clock signal input pin connect
The clock signal of receipts inputs each 2-bit shift register parallel, and the received data-signal of data-out pin serially inputs each 2-
Bit shift register, the first control signal output pin and second control signal output pin root of each 2-bit shift register
Signal is controlled according to the received level signal of each 2-bit shift register, clock signal and data-signal parallel output, when the electricity
When ordinary mail input pin receives high level signal, the first control signal output pin and second control signal output pin
The control signal of output is different, when receiving low level signal, the first control signal output pin and second control signal
The control signal of output pin output is identical, so that the purpose of different working modes can be supported by realizing a control chip,
Reduce design cost and production cost.
Detailed description of the invention
Fig. 1 is that a kind of modular structure of the control chip for LED display drive system that the embodiment of the present invention one provides is shown
It is intended to；
Fig. 2 is the modular structure signal of the combinatorial shifting register in Fig. 1；
Fig. 3 is the modular structure schematic diagram of the 2-bit shift register in Fig. 2.
Realization, functional characteristics and the advantage of purpose of the embodiment of the present invention will be done furtherly referring to attached drawing in conjunction with the embodiments
It is bright.
Specific embodiment
In order to be clearer and more clear technical problem to be solved of the embodiment of the present invention, technical solution and beneficial effect,
Below in conjunction with drawings and examples, the embodiment of the present invention is further elaborated.It should be appreciated that tool described herein
Body embodiment is only used to explain the embodiment of the present invention, is not intended to limit the present invention embodiment.
The embodiment of the present invention one provides a kind of control chip suitable for LED display drive system, referring to Fig. 1,
Control chip includes combinatorial shifting register 101, buffer 102, multichannel timing generates and control unit 103, gate control unit
104 and protection circuit 105.
The combinatorial shifting register 101 include level signal input pin, at least two 2-bit shift registers, when
Clock signal input pin and data-out pin:
The 2-bit shift register is equipped with DIR pin, CLK pin, DIN pin and first control signal output pin
It is connect with second control signal output pin, the DIR pins in parallel of each 2-bit shift register and with the level input pin
Logical, the CLK pin of each 2-bit shift register is in parallel and connects in the clock signal input pin, each 2-bit shift LD
The DIN pin serial connection of device is simultaneously connected with the data-out pin；
Wherein, the level signal input pin is used to control first control by receiving high level or low level signal
Whether the control signal of signal output pin and second control signal output pin output processed is identical, to realize control chip
The selection of operating mode.
In practical application, the data of each 2-bit shift register, which are transmitted, receives CLOCK signal by clock signal input pin
Afterwards parallel transmission give each 2-bit shift register realize, when sequentially inputting clock signal (CLK) of certain frequency, data by
DIN foot sequence is sent into register.
Referring to Fig. 2, being the feasible scheme of one combinatorial shifting register of the present embodiment.Combination in the scheme moves
Bit register 200 includes 4 2-bit shift registers.Each 2-bit shift register be equipped with DIR pin, CLK pin,
DIN pin and first control signal output pin CTRL0 and second control signal output pin CTRL1, in which:
2-bit shift register 201,2-bit shift register 202,2-bit shift register 203 and 2-bit displacement are posted
The DIR pin of storage 204 is connect with level signal input pin, to realize the parallel input of level signal；
2-bit shift register 201,2-bit shift register 202,2-bit shift register 203 and 2-bit displacement are posted
The CLK pin of storage 204 is connect with clock signal input pin, realizes the parallel input of clock signal；
2-bit shift register 201,2-bit shift register 202,2-bit shift register 203 and 2-bit displacement are posted
The DIN pin serial connection of storage 204 is simultaneously connected with the data-out pin, realizes the serial input of data.
Aforementioned 2-bit shift register 201,2-bit shift register 202,2-bit shift register 203 and 2-bit are moved
The DIN pin serial connection of bit register 204 is simultaneously connected with the data-out pin, is referred to:
The logical data-out pin of the DIN pin connection shift register 200 of 2-bit shift register 201, data output
Pin connects the DIN pin of 2-bit shift register 202, and the data output pins of 2-bit shift register 202 connect 2-bit
The data output pins of the DIN pin of shift register 203,2-bit shift register 203 connect 2-bit shift register 204
DIN pin.
Referring to Fig. 3, for the modular structure schematic diagram of each 2-bit shift register in Fig. 2.
2-bit shift register 300 includes that the first d type flip flop 301 and the second d type flip flop 302, each d type flip flop are all provided with
There are D pin, ck pin, Q pin and set pin:
The set pin of first d type flip flop 301 with after the set pins in parallel of second d type flip flop 302 with it is described
The DIR pin of 2-bit shift register connects；
After the ck pins in parallel of the ck pin of first d type flip flop 301 and second d type flip flop 302 with the 2-
The CLK pin of bit shift register connects；
The D pin of first d type flip flop 301 is connect with the DIN pin of the 2-bit shift register；
The Q pin of first d type flip flop 301 is moved with the D pin of second d type flip flop 302 and the 2-bit respectively
The first control signal output pin of bit register connects；
The Q pin of second d type flip flop 302 is exported with the second control signal of the 2-bit shift register respectively
Pin is connected with data output pins.
In this way, when the D pin of first trigger 301 receives high level signal, the Q pin of the first trigger 301
The control signal CTRL0 of output is different from the control signal CTRL1 output that the Q pin of the second trigger 302 exports, i.e. 2-bit
The first control signal output pin of shift register is different from the control signal that second control signal output pin exports.
When the D pin of first trigger 301 receives low level signal, the Q pin output of the first trigger 301
Control signal CTRL0 with the and the output of the Q pin of trigger 302 control signal CTRL1 output phase it is same, i.e. 2-bit is shifted and is posted
The first control signal output pin of storage is identical as the control signal that second control signal output pin exports.
By taking the combinatorial shifting register of Fig. 2 as an example, 4 2-bit shift registers are provided with, when its level signal inputs
Pin receives high level signal, and the first control signal output pin and second control signal of each 2-bit shift register export
The control signal of pin output is different, then controlling chip operation mode is 8 channels operation modes；When its level signal input pin
Receive low level signal, the first control signal output pin and second control signal output pin of each 2-bit shift register
The control signal of output is identical, then controlling chip operation mode is 4 channels operation modes.
In practical application, the level signal input pin for controlling chip can receive high level letter by powering on voltage
Number, low level signal is received by ground connection.
With continued reference to Fig. 1, the combinatorial shifting register 101 is produced by bit line and the buffer 102 and multichannel timing
Life is connected to control unit 103；
The multichannel timing is generated to be connected to by bit line with the gate control unit 104 with control unit 103；
The multichannel timing, which is generated, is equipped with chip select functionality multiplexing pins with control unit 103, and the chip select functionality multiplexing is drawn
Foot is for receiving high level or low level signal, to select the operating mode of the driving circuit；
The protection circuit 105 generates and control unit 103 and gate control with the buffer 102, multichannel timing respectively
Unit 102 connects.
The protection circuit 105 of the present embodiment may include:
Abnormality detection sub-circuit is protected for output channel voltage short-circuit protection and chip over-temperature；
Output channel voltage short-circuit protection sub-circuit, for being examined in real time to the voltage of output channel (OUT0~OUT7)
It surveys, when the voltage is lower than 0.1V, it is believed that the channel enters short-circuit condition, immediately turns off the channel and locks, and needs to open again
Dynamic power supply can just release；
Chip over-temperature protects sub-circuit, and for when chip temperature is more than 135 DEG C, triggering overheat protector module, output is high
Level (remains low level) when normal work, output channel is turned off, so that temperature be made to decline.When temperature drops to 115 DEG C
When, output channel reopens；
Delay protection sub-circuit, for realizing delay protection mechanism, effect is being opened 8 tunnels (or 4 tunnels) output channel
Transient voltage overshoot when opening and turning off is shielded, and protection circuit erroneous judgement is prevented.Usually using cascade guider come real
The now delay judgement of about 50nm.That is, after the on or off 50nm of output channel, what protective module detected
State is just considered as effective status.
In the present embodiment, abnormality detection sub-circuit and delay protection sub-circuit are combined, and are exported after internal logic operation
Enable signal was also used for control cascade signal (DOUT) both for controlling output channel.
The physical circuit of the protection circuit 105 of the present embodiment can be related to according to actual needs, can also be using existing
Some protection circuits, are not repeating herein.
Please continue to refer to Fig. 1, the main pin of control chip is illustrated:
DIN receives outer input data, connect with the data-out pin of combinatorial shifting register 101；BK is enable end,
High level is effective, and low level turns off output channel；CLK pin receive external timing signal and combinatorial shifting register 101 when
Clock signal input pin realizes that displacement send number and generates timing；DIR pin is model selection (piece choosing) foot, is posted with combinatorial shifting
The level signal input pin of storage 101 connects, for selecting 8 channels or 4 channel output modes.
The control chip of the present embodiment, equipped with the combinatorial shifting register that can support channel selecting, which is set
Level signal input pin, at least two 2-bit shift registers, clock signal input pin and data-out pin have been set,
And the received level signal of level signal input pin and the received clock signal of clock signal input pin input respectively parallel
2-bit shift register, the received data-signal of data-out pin serially input each 2-bit shift register, and each 2-bit is moved
The first control signal output pin and second control signal output pin of bit register are received according to each 2-bit shift register
Level signal, clock signal and data-signal parallel output control signal, when the level signal input pin receives high electricity
When ordinary mail, the control signal that the first control signal output pin is exported with second control signal output pin is different, when
When receiving low level signal, the control signal of the first control signal output pin and the output of second control signal output pin
It is identical, to realize the purpose that a control chip supports different working modes, reduce design cost and production cost.
Above by reference to the preferred embodiment of the Detailed description of the invention embodiment of the present invention, not thereby limit to the embodiment of the present invention
Interest field.Those skilled in the art do not depart from made any modification in the scope and spirit of the embodiment of the present invention, equally replace
It changes and improves, it should all be within the interest field of the embodiment of the present invention.
Claims (9)
1. a kind of control chip of LED display drive system, which is characterized in that the control chip is deposited equipped with combinatorial shifting
Device, the combinatorial shifting register include that level signal input pin, at least two 2-bit shift registers, clock signal are defeated
Enter pin and data-out pin:
The 2-bit shift register is equipped with DIR pin, CLK pin, DIN pin and first control signal output pin and the
Two control signal output pins, the DIR pins in parallel of each 2-bit shift register are simultaneously connected with the level input pin, respectively
The CLK pin of 2-bit shift register is in parallel and connects in the clock signal input pin, each 2-bit shift register
DIN pin serial connection is simultaneously connected with the data-out pin；
Wherein, the level signal input pin is used to control the first control letter by receiving high level or low level signal
Whether number output pin and the control signal of second control signal output pin output are identical, to realize the work of control chip
The selection of mode.
2. the control chip of LED display drive system as described in claim 1, which is characterized in that the 2-bit shift LD
Device includes the first d type flip flop and the second d type flip flop, and each d type flip flop is equipped with D pin, ck pin, Q pin and set pin:
After the set pins in parallel of the set pin of first d type flip flop 201 and second d type flip flop 202 with the 2-bit
The DIR pin of shift register connects；
It is moved after the ck pins in parallel of the ck pin of first d type flip flop 201 and second d type flip flop 202 with the 2-bit
The CLK pin of bit register connects；
The D pin of first d type flip flop 201 is connect with the DIN pin of the 2-bit shift register；
The Q pin of first d type flip flop 201 is posted with the D pin of second d type flip flop 202 and 2-bit displacement respectively
The first control signal output pin of storage connects；
The Q pin of the second d type flip flop 202 second control signal output pin with the 2-bit shift register respectively
It is connected with data output pins.
3. the control chip of LED display drive system as claimed in claim 1 or 2, which is characterized in that the combinatorial shifting
Register is set there are four 2-bit shift register.
4. the control chip of LED display drive system as claimed in claim 3, which is characterized in that the level signal is defeated
Enter pin and receive high level signal, the first control signal output pin of each 2-bit shift register and the second control are believed
The control signal of number output pin output is different, and the control chip operation mode is 8 channels operation modes.
5. the control chip of LED display drive system as claimed in claim 4, which is characterized in that the level signal is defeated
Enter pin and receives high level signal by powering on voltage.
6. the control chip of LED display drive system as claimed in claim 3, which is characterized in that the level signal is defeated
Enter pin and receive low level signal, the first control signal output pin of each 2-bit shift register and the second control are believed
The control signal of number output pin output is identical, and the control chip operation mode is 4 channels operation modes.
7. the control chip of LED display drive system as claimed in claim 6, which is characterized in that the level signal is defeated
Enter pin and low level signal is received by ground connection.
8. the control chip of LED display drive system as described in claim 1, which is characterized in that the control chip is also
It is generated and control unit and gate control unit including buffer, multichannel timing:
The shift register is generated with the buffer and the multichannel timing by bit line and is connected to control unit；
The multichannel timing generation is connected to by bit line with the gate control unit with control unit；
The multichannel timing, which is generated, is equipped with chip select functionality multiplexing pins with control unit, and the chip select functionality multiplexing pins are for connecing
High level or low level signal are received, to select the operating mode of the control chip.
9. the control chip of LED display drive system as claimed in claim 8, which is characterized in that the LED display drives
Dynamic circuit is additionally provided with protection circuit, and the protection circuit generates and control unit and grid with the buffer, multichannel timing respectively
Control unit connection.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201910523013.XA CN110310590A (en) | 2019-06-17 | 2019-06-17 | A kind of control chip of LED display drive system |
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| CN201910523013.XA CN110310590A (en) | 2019-06-17 | 2019-06-17 | A kind of control chip of LED display drive system |
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| CN112666444A (en) * | 2020-12-03 | 2021-04-16 | 思瑞浦微电子科技（苏州）股份有限公司 | Chip FT test method and system |
| CN112666444B (en) * | 2020-12-03 | 2024-06-04 | 思瑞浦微电子科技（苏州）股份有限公司 | Chip FT test method and system |
| CN113539343A (en) * | 2021-07-28 | 2021-10-22 | 北京微纳星空科技有限公司 | Multi-path output method, device and equipment of shift register and storage medium |
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