CN105390106A - Level conversion circuit and level conversion method of thin film transistor liquid crystal display panel - Google Patents
Level conversion circuit and level conversion method of thin film transistor liquid crystal display panel Download PDFInfo
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Abstract
The invention discloses a level conversion circuit and level conversion method of a thin film transistor liquid crystal display panel. The level conversion circuit includes a time sequence controller and a level converter electrically connected with the time sequence controller; the time sequence controller comprise a first pin; the time sequence controller transmits control signals to the level converter through the first pin; and the level converter includes a second pin electrically with the first pin; and the level converter receives the control signals through the second pin, processes the control signals, and outputs n driving signals which can drive the thin film transistor liquid crystal display panel, wherein n is a positive integer greater than or equal to 1. The invention also discloses a level conversion method of the thin film transistor liquid crystal display panel. With the level conversion circuit and level conversion method of the invention adopted, the number of pins between the time sequence controller and the level converter can be decreased, and therefore, a circuit structure can be simplified, and cost can be decreased.
Description
Technical field
The present invention relates to technical field of liquid crystal display, particularly relate to a kind of level shifting circuit of liquid crystal display panel of thin film transistor and a kind of level conversion method.
Background technology
TFT (ThinFilmTransistor, thin film transistor (TFT)) LCDs comprises TFT LCD panel, and for the driving circuit of drive TFT display panels.Driving circuit comprises the gate drivers of the gate line for drive TFT display panels, the data driver for the data line of drive TFT display panels, and the time schedule controller of driver' s timing for control gate driver and data driver.
A kind of TFT LCD panel adopts GOA (GateDriveOnArray, array base palte row cutting) framework.Be incorporated on thin-film transistor array base-plate by gate drivers, to realize lining by line scan to display panels.Adopt GOA framework to need on drives plate, to increase level transferring chip to carry out the level conversion of signal, carry out work to drive the TFT in display panels.The existing level shifting circuit for GOA framework display panels generally includes: one is located at the time schedule controller on drives plate, described time schedule controller for generation of with transmit control signal; One is located at the level transferring chip on drives plate, and described level transferring chip is for changing the level of the control signal sent by time schedule controller.Control signal after level conversion is input to gate drivers, and gate drivers drives the TFT in GOA framework display panels afterwards.But, for enabling the TFT in GOA framework display panels open line by line normally, need multiple control signal could realize the display effect of lining by line scan; And wherein each control signal needs to carry out communications by time schedule controller and pin corresponding to level transferring chip.Therefore, this will increase the number of pins of time schedule controller and level transferring chip, makes the structure of level shifting circuit become complicated, causes cost to increase.
Summary of the invention
In view of this, the invention provides a kind of level shifting circuit and level conversion method of liquid crystal display panel of thin film transistor, the number of pins between time schedule controller and level translator can be reduced.
A kind of level shifting circuit of liquid crystal display panel of thin film transistor, the level translator comprising time schedule controller and be electrically connected with described time schedule controller, described time schedule controller comprises the first pin, described time schedule controller is transmitted control signal to described level translator by described first pin, the first control signal high level lasting time of described control signal within a signal period or the first control signal low duration are T1, the second control signal high level lasting time within a signal period or the second control signal low duration are T2, the 3rd control signal high level lasting time within a signal period or the 3rd control signal low duration are T3, described level translator comprises the second pin be electrically connected with described first pin, described level translator receives the described control signal of described time schedule controller transmission by described second pin, and generate n drive singal according to described control signal, the drive singal high level lasting time of i-th drive singal within a signal period in n described drive singal equals described T1, drive singal low duration within a signal period equals described T2, or the drive singal high level lasting time within a signal period equals described T2, drive singal low duration within a signal period equals described T1, the high level of described i-th drive singal is the forward voltage of described thin film transistor (TFT), the low level of described i-th drive singal is the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th drive singal and the rising edge initial time of described control signal are spaced apart (i-1) * T3, wherein, n be more than or equal to 1 positive integer, i=1, 2, n.
Wherein, described level translator comprises logical transition circuit, described logical transition circuit by described second pin receive described time schedule controller send described control signal and described T1, T2 and T3 of decoding in described control signal; The first indicator signal comprising the information of described T1, T2 and T3 is generated according to described T1, T2 and T3.
Wherein, described level translator also comprises logic control circuit, described logic control circuit and described logical transition circuit are electrically connected, described logic control circuit receives described first indicator signal that described logical transition circuit sends, and generates n the second indicator signal according to the information of described T1, T2 and the T3 in described first indicator signal.
Wherein, the second indicator signal high level lasting time of i-th the second indicator signal within a signal period in n described second indicator signal equals described T1, the second indicator signal low duration within a signal period equals described T2, or the second indicator signal high level lasting time within a signal period equals described T2, the second indicator signal low duration within a signal period equals described T1, the high level absolute value of described i-th the second indicator signal is less than the absolute value of the forward voltage of described thin film transistor (TFT), the low level absolute value of described i-th the second indicator signal is less than the absolute value of the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th the second indicator signal and the rising edge initial time of described control signal are spaced apart (i-1) * T3.
Wherein, described level translator also comprises signal amplification circuit, described signal amplification circuit and described logic control circuit are electrically connected, described signal amplification circuit receives n described second indicator signal that described logic control circuit sends, and n described second indicator signal is amplified, generate n described drive singal.
A kind of level conversion method of liquid crystal display panel of thin film transistor, comprise: time schedule controller is transmitted control signal to level translator by the first pin on described time schedule controller, the first control signal high level lasting time of described control signal within a signal period or the first control signal low duration are T1, the second control signal high level lasting time within a signal period or the second control signal low duration are T2, the 3rd control signal high level lasting time within a signal period or the 3rd control signal low duration are T3, described level translator receives the described control signal of described time schedule controller transmission by the second pin on described level translator, and generate n drive singal according to described control signal, the drive singal high level lasting time of i-th drive singal within a signal period in n described drive singal equals described T1, drive singal low duration within a signal period equals described T2, or the drive singal high level lasting time within a signal period equals described T2, drive singal low duration within a signal period equals described T1, the high level of described i-th drive singal is the forward voltage of described thin film transistor (TFT), the low level of described i-th drive singal is the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th drive singal and the rising edge initial time of described control signal are spaced apart (i-1) * T3, wherein, n be more than or equal to 1 positive integer, i=1, 2, n.
Wherein, described level translator generates n described drive singal according to described control signal, comprising: described level translator decodes described T1, T2 and T3 in described control signal; Described level translator generates the first indicator signal comprising the information of described T1, T2 and T3 according to described T1, T2 and T3; Described level translator generates n described drive singal according to described first indicator signal.
Wherein, described level translator generates n described drive singal according to described first indicator signal, comprising: described level translator generates n the second indicator signal according to the information of described T1, T2 and the T3 in described first indicator signal; Described level translator generates n described drive singal according to n described second indicator signal.
Wherein, the second indicator signal high level lasting time of i-th the second indicator signal within a signal period in n described second indicator signal equals described T1, the second indicator signal low duration within a signal period equals described T2, or the second indicator signal high level lasting time within a signal period equals described T2, the second indicator signal low duration within a signal period equals described T1, the high level absolute value of described i-th the second indicator signal is less than the absolute value of the forward voltage of described thin film transistor (TFT), the low level absolute value of described i-th the second indicator signal is less than the absolute value of the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th the second indicator signal and the rising edge initial time of described control signal are spaced apart (i-1) * T3.
Wherein, described level translator generates n described drive singal according to n described second indicator signal, comprising: described level translator receives n described second indicator signal; Described level translator amplifies n described second indicator signal, generates n described drive singal.
Accompanying drawing explanation
In order to be illustrated more clearly in technical scheme of the present invention, be briefly described to the accompanying drawing used required in embodiment below, apparently, accompanying drawing in the following describes is only some embodiments of the present invention, for those of ordinary skill in the art, under the prerequisite not paying creative work, other accompanying drawing can also be obtained as these accompanying drawings.
Fig. 1 is the schematic diagram of the level shifting circuit of the liquid crystal display panel of thin film transistor that the embodiment of the present invention provides.
Fig. 2 is the sequential chart of a kind of embodiment of the level shifting circuit shown in Fig. 1.
Fig. 3 is the sequential chart of the another kind of embodiment of the level shifting circuit shown in Fig. 1.
Fig. 4 is the circuit module schematic diagram of the level translator shown in Fig. 1.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, be clearly and completely described the technical scheme in the embodiment of the present invention, obviously, described embodiment is only the present invention's part embodiment, instead of whole embodiments.Based on the embodiment in the present invention, those of ordinary skill in the art, not making the every other embodiment obtained under creative work prerequisite, belong to the scope of protection of the invention.
For ease of describing, can use such as here " ... under ", " ... below ", D score, " ... on ", " on " etc. space relative terms the relation of an element or feature and another (a bit) element or feature is as illustrated in the drawing described.Be appreciated that, when an element or layer be called as another element or layer " on ", " being connected to " or " being couple to " another element or layer time, it can directly on another element or layer, be directly connected to or be couple to another element or layer, or intervening elements or layer can be there is.
Being appreciated that terminology used here is only to describe specific embodiment, not really wanting to limit the present invention.When here using, clearly state unless context separately has, otherwise singulative " " and " being somebody's turn to do " are also intended to comprise plural form.Further, when using in this manual, term " comprises " and/or shows " comprising " existence of described feature, entirety, step, element and/or assembly, but does not get rid of other features one or more, entirety, step, element, assembly and/or its existence of combining or increase.Instructions subsequent descriptions is for implementing better embodiment of the present invention, and right described description is to illustrate for the purpose of rule of the present invention, and is not used to limit scope of the present invention.Protection scope of the present invention is when being as the criterion depending on the claims person of defining.
As shown in Figure 1, the level shifting circuit 200 of the embodiment of the present invention level translator 220 that comprises time schedule controller 210 and be electrically connected with this time schedule controller 210.
Time schedule controller 210 comprises the first pin 212, and time schedule controller 210 to be transmitted control signal CK1 to level translator 220 by described first pin 212.Level translator 220 comprises the second pin 226 be electrically connected with described first pin 212, level translator 220 is by described second pin 226 reception control signal CK1, and level conversion is carried out to control signal CK1, generating and export can n drive singal CKV1 ~ CKVn of drive TFT display panels, wherein, n be more than or equal to 1 positive integer.In the present embodiment, n equals 4.Be understandable that, in fact the present invention is not limited to this, and such as, n can also be 5,6,7,8 or other numerical value.
Therefore, level shifting circuit in the embodiment of the present invention, described time schedule controller and described level translator are respectively arranged with first pin and second pin, described first pin and described second pin electrical connection, a control signal is sent to described level translator by described time schedule controller, described level translator can be controlled and generate multiple drive singal, thus the number of pins decreased between time schedule controller and level translator, thereby simplify circuit structure, reduce cost.
As shown in Figure 2, in a kind of embodiment of the embodiment of the present invention, concrete, the first control signal high level lasting time of control signal CK1 within a signal period that described time schedule controller 210 sends is T1, the second control signal high level lasting time of control signal CK1 within a signal period is T2, control signal CK1 the 3rd control signal high level lasting time within a signal period is T3.For the drive circuit structure of concrete TFT LCD panel and/or the resolution of TFT LCD panel, the concrete numerical value of described T1, T2 and T3 can carry out relative set, and any one in T1, T2 and T3 can be zero.
Described level translator 220, to the control signal CK1 process received, generates one group of drive singal, such as, generates 4 drive singal CKV1 ~ CKV4.Wherein, the drive singal high level lasting time of i-th drive singal CKVi within a signal period equals described T1, and the drive singal low duration of described i-th drive singal CKVi within a signal period equals described T2.The high level of described i-th drive singal CKVi is the forward voltage VGH of TFT, and the low level of described i-th drive singal CKVi is the cut-off voltage VGL of TFT.The rising edge initial time of described i-th drive singal CKVi and the rising edge initial time of described control signal CK1 are spaced apart (i-1) * T3, i=1, and 2 ... n.Concrete, such as, as i=1, the drive singal high level lasting time of the 1st drive singal CKV1 within a signal period equals described T1, and the drive singal low duration of described 1st drive singal CKV1 within a signal period equals described T2.The high level of described 1st drive singal CKV1 is the forward voltage VGH of TFT, and the low level of described 1st drive singal CKV1 is the cut-off voltage VGL of TFT.The described rising edge initial time of the 1st drive singal CKV1 and the rising edge initial time of described control signal CK1 are spaced apart 0.Thus, level translator 220 according to signal parameter T1, T2 and the T3 in control signal CK1, can generate 4 drive singal CKV1 ~ CKV4.
As shown in Figure 3, in the another kind of embodiment of the embodiment of the present invention, different from the embodiment described above is, the first control signal low duration of control signal CK1 within a signal period that described time schedule controller 210 sends is T1, the second control signal low duration of control signal CK1 within a signal period is T2, control signal CK1 the 3rd control signal low duration within a signal period is T3.Same, for the drive circuit structure of concrete TFT LCD panel and/or the resolution of TFT LCD panel, the concrete numerical value of T1, T2 and T3 can carry out relative set, and any one in T1, T2 and T3 can be zero.
In the present embodiment, as shown in Figures 2 and 3, for T1, T2 and T3 simultaneously for the high level lasting time of control signal CK1 within a signal period or illustrate for the low duration of control signal CK1 within a signal period simultaneously, but in fact the present invention is not limited to this.Such as, T1 can also be the high level lasting time of control signal CK1 within a signal period, T2 can also be the low duration of control signal CK1 within a signal period, T3 can also be the high level lasting time of control signal CK1 within a signal period; Or T1 can also be the high level lasting time of control signal CK1 within a signal period, T2 can also be the low duration of control signal CK1 within a signal period, T3 can also be the low duration of control signal CK1 within a signal period; Or T1 can also be the low duration of control signal CK1 within a signal period, T2 can also be the high level lasting time of control signal CK1 within a signal period, T3 can also be the high level lasting time of control signal CK1 within a signal period; Or T1 can also be the low duration of control signal CK1 within a signal period, T2 can also be the high level lasting time of control signal CK1 within a signal period, T3 can also be the low duration of control signal CK1 within a signal period.
In the present embodiment, as shown in Figures 2 and 3, for the high level lasting time of described i-th drive singal CKVi within a signal period be T1, low duration is T2, initial time between i-th drive singal CKVi and the i-th+1 drive singal CKVi+1 postpones to illustrate for T3, but in fact the present invention is not limited to this.Such as, the high level lasting time of described i-th drive singal CKVi within a signal period can also be T2, low duration can also postpone to be T3 for T1, initial time between i-th drive singal CKVi and the i-th+1 drive singal CKVi+1; Or the high level lasting time of described i-th drive singal CKVi within a signal period can also be T2, low duration can also postpone to be T1 for T3, initial time between i-th drive singal CKVi and the i-th+1 drive singal CKVi+1; Or the high level lasting time of described i-th drive singal CKVi within a signal period can also be T1, low duration can also postpone to be T2 for T3, initial time between i-th drive singal CKVi and the i-th+1 drive singal CKVi+1; Or the high level lasting time of described i-th drive singal CKVi within a signal period can also be T3, low duration can also postpone to be T1 for T2, initial time between i-th drive singal CKVi and the i-th+1 drive singal CKVi+1; Or the high level lasting time of described i-th drive singal CKVi within a signal period can also be T3, low duration can also postpone to be T2 for T1, initial time between i-th drive singal CKVi and the i-th+1 drive singal CKVi+1.Concrete, such as, as i=1, the high level lasting time of the 1st drive singal CKV1 within a signal period can also be T2, low duration can also be T1, and the initial time between the 1st drive singal CKV1 and a 2nd drive singal CKV2 postpones for T3.
See also Fig. 4, in embodiments of the present invention, level translator 220 comprises:
Logical transition circuit 221, for being received the control signal CK1 that time schedule controller 210 sends by described second pin 226 on level translator 220, decode described T1, T2 and the T3 in described CK1, and comprise the first indicator signal of the information of described T1, T2 and T3 according to described T1, T2 and T3 generation and send described first indicator signal;
Logic control circuit 222, be electrically connected with described logical transition circuit 211, for receiving described first indicator signal that described logical transition circuit 221 sends, one group of second indicator signal is generated according to the information of described T1, T2 and T3 in described first indicator signal, as 4 the second indicator signal 0-CKV1 ~ 0-CKV4, and send described second indicator signal 0-CKV1 ~ 0-CKV4.Wherein, the signal parameter of described second indicator signal 0-CKV1 ~ 0-CKV4 is arranged according to described T1, T2 and T3.In the present embodiment, logic control circuit 222 generates 4 the second indicator signals, but in fact the present invention is not limited to this.In the present invention, the number of described second indicator signal that logic control circuit 222 generates equals the number of described drive singal, is namely all n, n be more than or equal to 1 positive integer.
Specifically, when described second indicator signal is n, such as, when being 4, wherein the second indicator signal high level lasting time of i-th the second indicator signal 0-CKVi within a signal period equals described T1, the second indicator signal low duration of described i-th the second indicator signal 0-CKVi within a signal period equals described T2; Or the second indicator signal high level lasting time of described i-th the second indicator signal 0-CKVi within a signal period equals described T2, the second indicator signal low duration of described i-th the second indicator signal 0-CKVi within a signal period equals described T1.The high level absolute value of described i-th the second indicator signal 0-CKVi is less than the absolute value of the forward voltage of described thin film transistor (TFT), the low level absolute value of described i-th the second indicator signal 0-CKVi is less than the absolute value of the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th the second indicator signal 0-CKVi and the rising edge initial time of described control signal CK1 are spaced apart (i-1) * T3, i=1,2 ... n.Concrete, such as, the second indicator signal high level lasting time of 1st the second indicator signal 0-CKV1 within a signal period equals described T1, and the second indicator signal low duration of described 1st the second indicator signal 0-CKV1 within a signal period equals described T2.The high level absolute value of described 1st the second indicator signal 0-CKV1 is less than the absolute value of the forward voltage of described thin film transistor (TFT), and the low level absolute value of described 1st the second indicator signal 0-CKV1 is less than the absolute value of the cut-off voltage of described thin film transistor (TFT).The described rising edge initial time of the 1st the second indicator signal 0-CKV1 and the rising edge initial time of described control signal CK1 are spaced apart 0.Now, 0-CKV1 ~ 0-CKV4 this organize the second indicator signal and can not be directly used in the TFT driven in display panels.
Signal amplification circuit 223, be electrically connected with described logic control circuit 222, for receiving described 4 the second indicator signal 0-CKV1 ~ 0-CKV4 that described logic control circuit 222 sends, and signal amplification is carried out with correspondence generation drive singal CKV1 ~ CKV4 to each indicator signal in described 4 the second indicator signal 0-CKV1 ~ 0-CKV4.Wherein, the cut-off voltage VGL that the forward voltage VGH that the high level of each drive singal in described drive singal CKV1 ~ CKV4 is thin film transistor (TFT), low level are thin film transistor (TFT).Thus, level translator 220 can process the control signal that time schedule controller 210 sends, and generates the drive singal of the TFT that can drive in display panels.
Above composition graphs 1 to Fig. 4, describes the level shifting circuit of the liquid crystal display panel of thin film transistor of the embodiment of the present invention in detail.Hereafter composition graphs 1 to Fig. 4 is described the level conversion method of the liquid crystal display panel of thin film transistor of the embodiment of the present invention.
The level conversion method of the liquid crystal display panel of thin film transistor that the embodiment of the present invention provides comprises the following steps:
Time schedule controller is transmitted control signal to level translator by the first pin on described time schedule controller, the first control signal high level lasting time of described control signal within a signal period or the first control signal low duration are T1, the second control signal high level lasting time within a signal period or the second control signal low duration are T2, and the 3rd control signal high level lasting time within a signal period or the 3rd control signal low duration are T3.
Described level translator receives the described control signal of described time schedule controller transmission by the second pin on described level translator, and generate n drive singal according to described control signal, the drive singal high level lasting time of i-th drive singal within a signal period in n described drive singal equals described T1, drive singal low duration within a signal period equals described T2, or the drive singal high level lasting time within a signal period equals described T2, drive singal low duration within a signal period equals described T1, the high level of described i-th drive singal is the forward voltage of described thin film transistor (TFT), the low level of described i-th drive singal is the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th drive singal and the rising edge initial time of described control signal are spaced apart (i-1) * T3, wherein, n be more than or equal to 1 positive integer, i=1, 2, n.
Therefore, the level conversion method of the liquid crystal display panel of thin film transistor of the embodiment of the present invention, time schedule controller sends a control signal by the first pin of on it to level translator, level translator receives described control signal by second pin of on it, thus time schedule controller can control described level translator generates multiple drive singal, thereby reduce the number of pins between time schedule controller and level translator, simplify circuit structure, reduce cost.
Optionally, described level translator generates n drive singal CKV1 ~ CKVn according to described control signal CK1, comprising:
Described level translator decodes described T1, T2 and T3 in described control signal;
Described level translator generates the first indicator signal comprising the information of described T1, T2 and T3 according to described T1, T2 and T3;
Described level translator generates n described drive singal according to described first indicator signal.
Optionally, described level translator generates n described drive singal CKV1 ~ CKVn according to described first indicator signal, comprising:
Described level translator generates n the second indicator signal according to the information of described T1, T2 and the T3 in described first indicator signal;
Described level translator generates n described drive singal according to n described second indicator signal.
Concrete, in n described second indicator signal 0-CKV1 ~ 0-CKVn the second indicator signal high level lasting time of i-th the second indicator signal 0-CKVi within a signal period equals described T1, the second indicator signal low duration of described i-th the second indicator signal 0-CKVi within a signal period equals described T2.Or the second indicator signal high level lasting time of described i-th the second indicator signal 0-CKVi within a signal period equals described T2, the second indicator signal low duration of described i-th the second indicator signal 0-CKVi within a signal period equals described T1.The high level absolute value of described i-th the second indicator signal 0-CKVi is less than the absolute value of the forward voltage of described thin film transistor (TFT), the low level absolute value of described i-th the second indicator signal 0-CKVi is less than the absolute value of the cut-off voltage of described thin film transistor (TFT), and the described rising edge initial time of i-th the second indicator signal 0-CKVi and the rising edge initial time of described control signal CK1 are spaced apart (i-1) * T3.Concrete, such as, the second indicator signal high level lasting time of 1st the second indicator signal 0-CKV1 within a signal period equals described T1, and the second indicator signal low duration of described 1st the second indicator signal 0-CKV1 within a signal period equals described T2.The high level absolute value of described 1st the second indicator signal 0-CKV1 is less than the absolute value of the forward voltage of described thin film transistor (TFT), and the low level absolute value of described 1st the second indicator signal 0-CKV1 is less than the absolute value of the cut-off voltage of described thin film transistor (TFT).The described rising edge initial time of the 1st the second indicator signal 0-CKV1 and the rising edge initial time of described control signal CK1 are spaced apart 0.
Optionally, described level translator generates n described drive singal CKV1 ~ CKVn according to n described second indicator signal 0-CKV1 ~ 0-CKVn, comprising:
Described level translator receives n described second indicator signal;
Described level translator amplifies n described second indicator signal, generates n described drive singal.
Be understandable that, each executive agent in the level conversion method of the embodiment of the present invention may correspond to the modules in the level shifting circuit 200 of the embodiment of the present invention, and the corresponding flow process of described level conversion method is operated by the above and other of the modules in level shifting circuit 200 respectively and/or function is achieved.For simplicity, do not repeat them here.
The above; be only the specific embodiment of the present invention; but protection scope of the present invention is not limited thereto; anyly be familiar with those skilled in the art in the technical scope that the present invention discloses; can expect amendment or the replacement of various equivalence easily, these amendments or replacement all should be encompassed within protection scope of the present invention.Therefore, protection scope of the present invention should be as the criterion with the protection domain of claim.
Claims (10)
1. the level shifting circuit of a liquid crystal display panel of thin film transistor, the level translator comprising time schedule controller and be electrically connected with described time schedule controller, it is characterized in that, described time schedule controller comprises the first pin, described time schedule controller is transmitted control signal to described level translator by described first pin, the first control signal high level lasting time of described control signal within a signal period or the first control signal low duration are T1, the second control signal high level lasting time within a signal period or the second control signal low duration are T2, the 3rd control signal high level lasting time within a signal period or the 3rd control signal low duration are T3,
Described level translator comprises the second pin be electrically connected with described first pin, described level translator receives the described control signal of described time schedule controller transmission by described second pin, and generate n drive singal according to described control signal, the drive singal high level lasting time of i-th drive singal within a signal period in n described drive singal equals described T1, drive singal low duration within a signal period equals described T2, or the drive singal high level lasting time within a signal period equals described T2, drive singal low duration within a signal period equals described T1, the high level of described i-th drive singal is the forward voltage of described thin film transistor (TFT), the low level of described i-th drive singal is the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th drive singal and the rising edge initial time of described control signal are spaced apart (i-1) * T3, wherein, n be more than or equal to 1 positive integer, i=1, 2, n.
2. according to the level shifting circuit described in claim 1, it is characterized in that, described level translator comprises logical transition circuit, described logical transition circuit by described second pin receive described time schedule controller send described control signal and described T1, T2 and T3 of decoding in described control signal; The first indicator signal comprising the information of described T1, T2 and T3 is generated according to described T1, T2 and T3.
3. according to the level shifting circuit described in claim 2, it is characterized in that, described level translator also comprises logic control circuit, described logic control circuit and described logical transition circuit are electrically connected, described logic control circuit receives described first indicator signal that described logical transition circuit sends, and generates n the second indicator signal according to the information of described T1, T2 and the T3 in described first indicator signal.
4. according to the level shifting circuit described in claim 3, it is characterized in that, the second indicator signal high level lasting time of i-th the second indicator signal within a signal period in n described second indicator signal equals described T1, the second indicator signal low duration within a signal period equals described T2, or the second indicator signal high level lasting time within a signal period equals described T2, the second indicator signal low duration within a signal period equals described T1, the high level absolute value of described i-th the second indicator signal is less than the absolute value of the forward voltage of described thin film transistor (TFT), the low level absolute value of described i-th the second indicator signal is less than the absolute value of the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th the second indicator signal and the rising edge initial time of described control signal are spaced apart (i-1) * T3.
5. according to the level shifting circuit described in claim 3 or 4, it is characterized in that, described level translator also comprises signal amplification circuit, described signal amplification circuit and described logic control circuit are electrically connected, described signal amplification circuit receives n described second indicator signal that described logic control circuit sends, and n described second indicator signal is amplified, generate n described drive singal.
6. a level conversion method for liquid crystal display panel of thin film transistor, is characterized in that, comprising:
Time schedule controller is transmitted control signal to level translator by the first pin on described time schedule controller, the first control signal high level lasting time of described control signal within a signal period or the first control signal low duration are T1, the second control signal high level lasting time within a signal period or the second control signal low duration are T2, and the 3rd control signal high level lasting time within a signal period or the 3rd control signal low duration are T3;
Described level translator receives the described control signal of described time schedule controller transmission by the second pin on described level translator, and generate n drive singal according to described control signal, the drive singal high level lasting time of i-th drive singal within a signal period in n described drive singal equals described T1, drive singal low duration within a signal period equals described T2, or the drive singal high level lasting time within a signal period equals described T2, drive singal low duration within a signal period equals described T1, the high level of described i-th drive singal is the forward voltage of described thin film transistor (TFT), the low level of described i-th drive singal is the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th drive singal and the rising edge initial time of described control signal are spaced apart (i-1) * T3, wherein, n be more than or equal to 1 positive integer, i=1, 2, n.
7. according to the level conversion method described in claim 6, it is characterized in that, described level translator generates n described drive singal according to described control signal, comprising:
Described level translator decodes described T1, T2 and T3 in described control signal;
Described level translator generates the first indicator signal comprising the information of described T1, T2 and T3 according to described T1, T2 and T3;
Described level translator generates n described drive singal according to described first indicator signal.
8. according to the level conversion method described in claim 7, it is characterized in that, described level translator generates n described drive singal according to described first indicator signal, comprising:
Described level translator generates n the second indicator signal according to the information of described T1, T2 and the T3 in described first indicator signal;
Described level translator generates n described drive singal according to n described second indicator signal.
9. according to Claim 8 described in level conversion method, it is characterized in that, the second indicator signal high level lasting time of i-th the second indicator signal within a signal period in n described second indicator signal equals described T1, the second indicator signal low duration within a signal period equals described T2, or the second indicator signal high level lasting time within a signal period equals described T2, the second indicator signal low duration within a signal period equals described T1, the high level absolute value of described i-th the second indicator signal is less than the absolute value of the forward voltage of described thin film transistor (TFT), the low level absolute value of described i-th the second indicator signal is less than the absolute value of the cut-off voltage of described thin film transistor (TFT), the rising edge initial time of described i-th the second indicator signal and the rising edge initial time of described control signal are spaced apart (i-1) * T3.
10. the level conversion method described according to Claim 8 or 9, is characterized in that, described level translator generates n described drive singal according to n described second indicator signal, comprising:
Described level translator receives n described second indicator signal;
Described level translator amplifies n described second indicator signal, generates n described drive singal.
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