CN102968970B - Driving device and driving method for display panel - Google Patents
Driving device and driving method for display panel Download PDFInfo
- Publication number
- CN102968970B CN102968970B CN201210430542.3A CN201210430542A CN102968970B CN 102968970 B CN102968970 B CN 102968970B CN 201210430542 A CN201210430542 A CN 201210430542A CN 102968970 B CN102968970 B CN 102968970B
- Authority
- CN
- China
- Prior art keywords
- signal
- grid
- grid line
- control signal
- delay
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Landscapes
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The invention discloses a driving device and driving method for a display panel. The driving device for the display panel comprises a time sequence controller, a grid driver and a logic driver. The logic driver is used for receiving grid control signals output by the time sequence controller, obtaining level signals on display panel grid lines, obtaining resistance-capacitance (RC) Delay signals, compensating the grid control signals by utilizing the RC Delay signals, and outputting the compensated grid control signals to the grid driver. The grid driver is used for generating grid driving signals according to the compensated grid control signals and outputting the grid control signals to the display panel grid lines. Due to the fact that the logic driver is added to obtain the RC Delay signals on the grid lines and compensate the grid control signals, the problem that data signals of a thin film transistor (TFT) corresponding to each line of grid line are confused due to RC Delay is effectively solved.
Description
Technical field
The present invention relates to display technique field, particularly relate to a kind of drive unit and driving method of display panel.
Background technology
TFT(Thin Film Transistor, Thin Film Transistor (TFT))-LCD(Liquid Crystal Display, a kind of liquid crystal display) form primarily of liquid crystal panel, gate drivers (also claiming gate driver circuit), data driver (also claiming data drive circuit), time schedule controller, gamma electric voltage maker and backlight.Liquid crystal panel is made up of array base palte and color membrane substrates and liquid crystal.Data line and grid line are formed on array base palte, and the TFT being arranged on data line and grid line infall is sent to the pixel electrode of array base palte, with the liquid crystal driving pixel electrode corresponding for the data-signal exported by data driver.
Shown in Fig. 1 is existing a kind of structural representation realizing TFT-LCD and drive.Wherein, time schedule controller 10 generates grid control signal and source control signal for the synchronizing signal according to input, and exports grid control signal to gate drivers 40, exports source control signal to data driver 30.This grid control signal is used for control gate driver 40, includes but not limited to CPV(Clock Pulse Vertical, gate clock) signal and grid OE(Output Enable, output enable) signal; This source control signal is used for control data driver 30.Gamma electric voltage maker 20 determines multiple voltage signals of gamma GTG for generating, and exports multiple voltage signals of the decision gamma GTG generated to data driver 30.The grid control signal of gate drivers 40 for exporting according to time schedule controller 10, generates gate drive signal, and this gate drive signal is opened for the TFT controlling grid line connection or closed.The source control signal of data driver 30 for exporting according to time schedule controller 10, generates the data-signal driven needed for liquid crystal, and by the pixel electrode outputting data signals of TFT to liquid crystal panel 50.
Realize in the circuit structure of TFT-LCD driving, gate drivers 40 starts to export gate drive signal at the negative edge of grid OE signal usually.And when gate drivers 40 exports the gate drive signal GATE1 for starting n-th line grid line, data-signal DATA corresponding for each pixel electrode on this row grid line outputs on each TFT corresponding to this row grid line by data driver 30.Shown in Fig. 2 is the desirable sequential relationship schematic diagram of gate drive signal, overlapping to not existing between the gate drive signal that often row grid line exports.That is, all close at each TFT that lastrow grid line is corresponding and have no progeny, the TFT that next line grid line is corresponding just can open.
Actual conditions are, on a grid line, from initial segment to end section, each position gate drive signal all exists RC Delay(RC delays), cause the rising edge of gate drive signal and negative edge to have certain time delay.The gate drive signal of TFT-LCD actual time order relation as shown in Figure 3.If the time delay of gate drive signal is relatively more serious, so when the gate drive signal GATE1 of n-th line grid line is in negative edge, the gate drive signal GATE2 of the (n+1)th row grid line has started to rise.Each TFT that then n-th line grid line is corresponding does not also all turn off, each TFT on (n+1)th row grid line opens, data driver starts to each TFT outputting data signals on the (n+1)th row grid line, causing the data-signal of each TFT corresponding with outputting to n-th line grid line to obscure, affecting picture display.
Summary of the invention
The object of this invention is to provide a kind of Drive And Its Driving Method of display panel, to solve the delay issue of gate drive signal.
The object of the invention is to be achieved through the following technical solutions:
A drive unit for display panel, comprising:
Time schedule controller, for sending grid control signal to logical drive;
Logical drive, for receiving the grid control signal that described time schedule controller exports, obtain the level signal on display panel grid line, RC Delay signal is postponed according to the capacitance resistance that the level signal on described grid line obtains on described grid line, utilize the RC Delay signal on described grid line to compensate described grid control signal, and export the grid control signal after compensating to described gate drivers;
Described gate drivers, for generating gate drive signal according to the grid control signal after described compensation, and exports described gate drive signal to described display panel grid line.
Preferably, described logical drive comprises:
Analog to digital converter, for being converted to digital signal by the RC Delay signal of described grid control signal and described grid line;
Totalizer, for the RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out additive operation, generates the grid control signal after compensating;
Digital to analog converter, for being converted to simulating signal by the grid control signal after described compensation and exporting to described gate drivers.
Preferably, described logical drive comprises:
Analog to digital converter, for being converted to digital signal by the RC Delay signal of described grid control signal and described grid line;
XOR module, for the RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out XOR, generates the grid control signal after compensating;
Digital to analog converter, for being converted to simulating signal by the grid control signal after described compensation and exporting to described gate drivers.
Preferably, described logical drive also comprises:
Feedback signal line, is connected with each grid line on described display panel, for obtaining the level signal on display panel grid line.
A driving method for display panel, comprising:
Logical drive receives the grid control signal that time schedule controller exports;
Described logical drive obtains the level signal on display panel grid line;
Described logical drive obtains the RC Delay signal of described grid line according to the level signal on described grid line;
Described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers;
Described gate drivers generates gate drive signal according to the grid control signal after described compensation, and exports described gate drive signal to described display panel grid line.
Preferably, described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out additive operation, generates the grid control signal after compensating;
Grid control signal after described compensation is converted to simulating signal and exports to described gate drivers.
Preferably, described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out XOR, generates the grid control signal after compensating;
Grid control signal after described compensation is converted to simulating signal and exports to described gate drivers.
Obtain grid line RC Delay signal owing to adding logical drive and grid control signal is compensated, thus effectively reduce RC Delay and signal is exported to the impact caused, the data-signal avoiding TFT corresponding to each row grid line is obscured, and affects the problem of picture display.
Accompanying drawing explanation
Fig. 1 is the structural representation that existing techniques in realizing TFT-LCD drives;
Fig. 2 is the desirable sequential relationship schematic diagram of prior art gate drive signal;
Fig. 3 is order relation schematic diagram actual time of prior art gate drive signal;
The driving device structure schematic diagram of the display panel that Fig. 4 provides for the embodiment of the present invention;
The structural representation of a kind of logical drive that Fig. 5 provides for the embodiment of the present invention;
The structural representation of the another kind of logical drive that Fig. 6 provides for the embodiment of the present invention;
Order relation schematic diagram actual time of the gate drive signal that Fig. 7 provides for the embodiment of the present invention;
The method flow diagram that Fig. 8 provides for the embodiment of the present invention.
Embodiment
In order to solve the delay issue of gate drive signal, embodiments providing a kind of drive unit of display panel, at least comprising: time schedule controller, gate drivers and logical drive.Wherein, time schedule controller sends grid control signal to logical drive.Logical drive receives the grid control signal that time schedule controller exports, obtain the level signal on display panel grid line, the RC Delay signal on described grid line is obtained according to the level signal on described grid line, utilize the RC Delay signal on described grid line to compensate described grid control signal, and export the grid control signal after compensating to described gate drivers.Gate drivers generates gate drive signal according to the grid control signal after described compensation, and exports described gate drive signal to described display panel grid line.Obtain grid line RC Delay signal owing to adding logical drive and grid control signal is compensated, thus effectively reduce RC Delay and signal is exported to the impact caused, the data-signal avoiding TFT corresponding to each row grid line is obscured, and affects the problem of picture display.
In the embodiment of the present invention, described display panel comprises color membrane substrates and array base palte.The grid line of described display panel can refer to, is arranged on the grid line on the array base palte of display panel.
Below in conjunction with accompanying drawing, the technical scheme that the embodiment of the present invention provides is described in detail.
The drive unit of a kind of preferred display panel that the embodiment of the present invention provides, it realizes structure as shown in Figure 4, at least comprises: time schedule controller 10, gamma electric voltage maker 20, data driver 30, gate drivers 40 and logical drive 60.
This drive unit is for driving display panel 70.Described display panel 70 comprises array base palte, color membrane substrates and liquid crystal.Array base palte comprises grid line, the data line of ranks cross-distribution, the pixel switch of every bar grid line and data line infall.Described display panel 70 can but be not limited only to display panels.Concrete:
Time schedule controller 10, from outside input sync signal, as clock signal, horizontal-drive signal, vertical synchronizing signal and data enable signal etc., also have input RGB(Red Green Blue, RGB) show data.
Time schedule controller 10 uses the synchronizing signal of input to generate grid control signal and source control signal, and exports grid control signal to logic controller 60, and data controlling signal is exported to data driver.Generate grid control signal can but be not limited only to CPV signal and grid OE signal.
Gamma electric voltage maker 20 generates the multiple voltage signals determining gamma GTG, and exports multiple voltage signals of the decision gamma GTG generated to data driver 30.
Gate drivers 40, according to the grid control signal of input, generates gate drive signal, and this gate drive signal is opened for the pixel switch that the grid line controlling display panel 70 connects or closed.Concrete, gate drive signal starts to export gate drive signal at the negative edge of grid OE signal, and within each CPV cycle, a grid line only to display panel 70 exports gate drive signal.
The source control signal that data driver 30 exports according to time schedule controller 10, generates the data-signal needed for pixel driving display panel, and by the pixel data output signal of pixel switch to display panel 70.
Logical drive 60 receives the grid control signal that time schedule controller 10 exports, the level signal of current C PV cycle enable grid line is obtained from the array base palte of display panel 70, the RC Delay signal on this grid line is obtained according to the level signal on this grid line, utilize the RC Delay signal of this grid line to compensate above-mentioned grid control signal, and export the grid control signal after compensating to gate drivers 40.
Concrete, by being compared by the gate drive signal of the level signal obtained from this grid line and this grid line, the RC Delay signal on this grid line can be obtained.
Wherein, the gate drive signal that level signal i.e. this row grid line obtained from grid line postpones.In order to obtain the level signal of grid line, logical drive 60 also comprises feedback signal line, and this feedback signal line is connected with each grid line on array base palte.All have RC Delay everywhere due to grid line, and RC Delay everywhere adds up, therefore, at the end of grid line, the RC Delay of its level signal is the most serious, and feedback signal line can be connected with the end of each grid line.So-called grid line end refers to, away from one end that grid line is connected with gate drivers 30.
Obtain grid line RC Delay signal owing to adding logical drive and grid control signal is compensated, and then control the time exporting gate drive signal to every row grid line, gate drive signal when exporting gate drive signal to next line grid line on lastrow grid line is disappeared, thus effectively reduce RC Delay and signal is exported to the impact caused, the data-signal avoiding pixel switch (as TFT) corresponding to each row grid line is obscured, and affects the problem of picture display.
In the embodiment of the present invention, specifically can be compensated grid control signal by additive operation, also can be compensated grid control signal by XOR.Can also by other means, RCDelay signal be utilized to compensate grid control signal.Accordingly, what embodiments provide two kinds of preferred logical drives realizes structure.
The first preferably realizes structure as shown in Figure 5, and logical drive 60 at least comprises: ADC(Analog-to-Digital Converter, analog to digital converter), for the RC Delay signal of grid control signal and current grid line is converted to digital signal; Adder(totalizer), for the RC Delay signal of the grid control signal and current grid line that convert digital signal to is carried out additive operation, generate the grid control signal after compensating; DAC(Digital-to-Analog Converter, analog to digital converter), for the grid control signal after compensation is converted to simulating signal and exports to gate drivers 30.
Concrete, Adder will carry out additive operation respectively with through analog-to-digital CPV signal and OE signal through analog-to-digital RC Delay signal.CPV signal after Adder process and OE signal are as shown in Figure 7.
The second preferably realizes structure as shown in Figure 6, and logical drive at least comprises: ADC, for grid control signal and grid RC Delay signal are converted to digital signal; XOR module 80, for the grid control signal and grid RC Delay signal that convert digital signal to are carried out XOR, generates the grid control signal after compensating; DAC, for being converted to simulating signal by the grid control signal after compensation and exporting to gate drivers.
Concrete, RC Delay signal, CPV signal and OE signal are carried out analog-to-digital conversion process by ADC module respectively, XOR module 80 will carry out additive operation respectively with through analog-to-digital CPV signal and OE signal through analog-to-digital RC Delay signal, and the CPV1 signal obtained after Adder process and OE1 signal are carried out digital-to-analog conversion process by DAC.CPV1 signal after XOR module 80 processes and OE1 signal are as shown in Figure 7.Wherein, GATE1 is the gate drive signal of current line grid line, and GAT2 is the gate drive signal of next line grid line.
The present invention also provides a kind of driving method of display panel, and its implementation as shown in Figure 8, specifically comprises following operation:
Step 800, logical drive receive the grid control signal that time schedule controller exports;
Step 810, described logical drive obtain the level signal on display panel grid line;
Step 820, described logical drive obtain the RC Delay signal of described grid line according to the level signal on described grid line;
Step 830, described logical drive utilize the RC Delay signal of described grid line to compensate described grid control signal, and export the grid control signal after compensating to gate drivers;
Step 840, described gate drivers generate gate drive signal according to the grid control signal after described compensation, and export described gate drive signal to described display panel grid line.
Preferably, described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out additive operation, generates the grid control signal after compensating;
Grid control signal after described compensation is converted to simulating signal and exports to described gate drivers.
Preferably, described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out, generates the grid control signal after compensating;
Grid control signal after described compensation is converted to simulating signal and exports to described gate drivers.
Obviously, those skilled in the art can carry out various change and modification to the present invention and not depart from the spirit and scope of the present invention.Like this, if these amendments of the present invention and modification belong within the scope of the claims in the present invention and equivalent technologies thereof, then the present invention is also intended to comprise these change and modification.
Claims (7)
1. a drive unit for display panel, is characterized in that, this device comprises:
Time schedule controller, for sending grid control signal to logical drive;
Logical drive, for receiving the grid control signal that described time schedule controller exports, obtain the level signal on display panel grid line, RC Delay signal is postponed according to the capacitance resistance that the level signal on described grid line obtains on described grid line, utilize the RC Delay signal on described grid line to compensate described grid control signal, and export the grid control signal after compensating to gate drivers;
Described gate drivers, for generating gate drive signal according to the grid control signal after described compensation, and exports described gate drive signal to described display panel grid line;
Wherein, the described capacitance resistance obtained on described grid line according to the level signal on described grid line postpones RC Delay signal, specifically comprises:
By the gate drive signal of the level signal obtained from this grid line and this grid line is compared, obtain the RC Delay signal on this grid line, the gate drive signal of the next line grid line adjacent with this grid line current is carried out time delay output according to this RC Delay signal.
2. drive unit according to claim 1, is characterized in that, described logical drive comprises:
Analog to digital converter, for being converted to digital signal by the RC Delay signal of described grid control signal and described grid line;
Totalizer, for the RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out additive operation, generates the grid control signal after compensating;
Digital to analog converter, for being converted to simulating signal by the grid control signal after described compensation and exporting to described gate drivers.
3. drive unit according to claim 1, is characterized in that, described logical drive comprises:
Analog to digital converter, for being converted to digital signal by the RC Delay signal of described grid control signal and described grid line;
XOR module, for the RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out XOR, generates the grid control signal after compensating;
Digital to analog converter, for being converted to simulating signal by the grid control signal after described compensation and exporting to described gate drivers.
4. the drive unit according to Claims 2 or 3, is characterized in that, described logical drive also comprises:
Feedback signal line, is connected with each grid line on described display panel, for obtaining the level signal on display panel grid line.
5. a driving method for display panel, is characterized in that, comprising:
Logical drive receives the grid control signal that time schedule controller exports;
Described logical drive obtains the level signal on display panel grid line;
Described logical drive obtains the RC Delay signal of described grid line according to the level signal on described grid line;
Described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers;
Described gate drivers generates gate drive signal according to the grid control signal after described compensation, and exports described gate drive signal to described display panel grid line;
Wherein, the described capacitance resistance obtained on described grid line according to the level signal on described grid line postpones RC Delay signal, specifically comprises:
By the gate drive signal of the level signal obtained from this grid line and this grid line is compared, obtain the RC Delay signal on this grid line, the gate drive signal of the next line grid line adjacent with this grid line current is carried out time delay output according to this RC Delay signal.
6. driving method according to claim 5, is characterized in that, described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out additive operation, generates the grid control signal after compensating;
Grid control signal after described compensation is converted to simulating signal and exports to described gate drivers.
7. driving method according to claim 5, is characterized in that, described logical drive utilizes the RC Delay signal of described grid line to compensate described grid control signal, and exports the grid control signal after compensating to gate drivers, specifically comprises:
The RC Delay signal of described grid control signal and described grid line is converted to digital signal;
The RC Delay signal of the grid control signal and described grid line that convert digital signal to is carried out XOR, generates the grid control signal after compensating;
Grid control signal after described compensation is converted to simulating signal and exports to described gate drivers.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210430542.3A CN102968970B (en) | 2012-11-01 | 2012-11-01 | Driving device and driving method for display panel |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201210430542.3A CN102968970B (en) | 2012-11-01 | 2012-11-01 | Driving device and driving method for display panel |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN102968970A CN102968970A (en) | 2013-03-13 |
| CN102968970B true CN102968970B (en) | 2015-01-28 |
Family
ID=47799079
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201210430542.3A Active CN102968970B (en) | 2012-11-01 | 2012-11-01 | Driving device and driving method for display panel |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN102968970B (en) |
Families Citing this family (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103366706B (en) * | 2013-07-19 | 2016-03-30 | 深圳市华星光电技术有限公司 | A kind of voltage compensating circuit of gate drivers and method and liquid crystal indicator |
| CN103928000B (en) | 2013-12-30 | 2016-08-17 | 厦门天马微电子有限公司 | Film crystal tube drive circuit and driving method, liquid crystal indicator |
| CN104766583B (en) * | 2015-04-27 | 2017-07-04 | 京东方科技集团股份有限公司 | A kind of compensation method of polarity inversion, device and liquid crystal display |
| CN105468063B (en) * | 2016-01-04 | 2017-03-08 | 京东方科技集团股份有限公司 | Source voltage control circuit, method, drive integrated circult and display device |
| KR102376490B1 (en) * | 2017-03-29 | 2022-03-18 | 삼성디스플레이 주식회사 | Display device |
| WO2018223313A1 (en) * | 2017-06-07 | 2018-12-13 | Boe Technology Group Co., Ltd. | Method of preventing false output of goa circuit of a liquid crystal display panel |
| CN109741716B (en) * | 2019-03-15 | 2021-01-29 | 京东方科技集团股份有限公司 | Data signal delay circuit and delay method and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101741A (en) * | 2006-07-07 | 2008-01-09 | 三星电子株式会社 | Driving apparatus, liquid crystal display comprising the driving apparatus and method of driving the liquid crystal display |
| CN101226713A (en) * | 2007-01-19 | 2008-07-23 | 三星电子株式会社 | Display apparatus and method of driving the same |
| CN101430850A (en) * | 2007-11-08 | 2009-05-13 | 中华映管股份有限公司 | Plane display device and its control method of signal control circuit |
| CN101727854A (en) * | 2008-10-21 | 2010-06-09 | 华映视讯（吴江）有限公司 | Output stage circuit, grid electrode drive module and control method of scanning line |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20080018607A (en) * | 2006-08-25 | 2008-02-28 | 삼성전자주식회사 | Gate driving circuit and liquid crystal display having the same |
-
2012
- 2012-11-01 CN CN201210430542.3A patent/CN102968970B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101101741A (en) * | 2006-07-07 | 2008-01-09 | 三星电子株式会社 | Driving apparatus, liquid crystal display comprising the driving apparatus and method of driving the liquid crystal display |
| CN101226713A (en) * | 2007-01-19 | 2008-07-23 | 三星电子株式会社 | Display apparatus and method of driving the same |
| CN101430850A (en) * | 2007-11-08 | 2009-05-13 | 中华映管股份有限公司 | Plane display device and its control method of signal control circuit |
| CN101727854A (en) * | 2008-10-21 | 2010-06-09 | 华映视讯（吴江）有限公司 | Output stage circuit, grid electrode drive module and control method of scanning line |
Also Published As
| Publication number | Publication date |
|---|---|
| CN102968970A (en) | 2013-03-13 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN102968970B (en) | Driving device and driving method for display panel | |
| CN105096876B (en) | GOA drive systems and liquid crystal panel | |
| CN102456331B (en) | Liquid crystal display | |
| US10332466B2 (en) | Method of driving display panel and display apparatus for performing the same | |
| CN102867543B (en) | Shift register, gate drivers and display device | |
| CN100543530C (en) | Liquid crystal indicator and display packing thereof | |
| US10068658B2 (en) | Shift register unit, driving circuit and method, array substrate and display apparatus | |
| US20080238895A1 (en) | Driving Device of Display Device and Related Method | |
| CN104464595B (en) | Scan drive circuit and display device | |
| CN105390106A (en) | Level conversion circuit and level conversion method of thin film transistor liquid crystal display panel | |
| CN101320539A (en) | Display and method of driving the same | |
| CN105374331A (en) | Gate driver on array (GOA) circuit and display by using the same | |
| CN101178879B (en) | Display panel of LCD device and drive method thereof | |
| CN105118470A (en) | Grid electrode driving circuit and grid electrode driving method, array substrate and display panel | |
| CN104050946B (en) | Multi-phase gate driver and display panel thereof | |
| CN103489392A (en) | Time schedule control method, time program controller and display device | |
| JP2009258733A (en) | Method and device for driving liquid crystal display | |
| CN102650779A (en) | Liquid crystal display | |
| CN104810004A (en) | Clock signal generation circuit, grid driving circuit, display panel and display device | |
| US8390612B2 (en) | Source driver and operation method thereof and flat panel display | |
| CN105047154A (en) | Driving compensating circuit, liquid crystal display device with driving compensating circuit and driving method | |
| CN101533598B (en) | A source electrode driven integrated circuit framework of display | |
| CN103077690B (en) | Gate drivers and liquid crystal display | |
| CN105304036B (en) | Display device | |
| CN102376254A (en) | Gate line driving device and restoration method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant |