CN210865580U - Control chip of LED display screen driving system - Google Patents
Control chip of LED display screen driving system Download PDFInfo
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- CN210865580U CN210865580U CN201920922479.2U CN201920922479U CN210865580U CN 210865580 U CN210865580 U CN 210865580U CN 201920922479 U CN201920922479 U CN 201920922479U CN 210865580 U CN210865580 U CN 210865580U
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Abstract
The embodiment of the utility model discloses LED display screen actuating system's control chip belongs to LED drive technical field. The control chip is provided with a combined shift register which comprises a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin: the 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and is communicated with the level input pin, and the level signal input pin is used for controlling whether the control signals output by the first control signal output pin and the second control signal output pin are the same or not by receiving a high level or low level signal, so that the selection of the working mode of the control chip is realized. Adopt the embodiment of the utility model provides a, realized that a control chip can support different mode's purpose.
Description
Technical Field
The embodiment of the utility model provides a relate to LED drive technical field, especially relate to a LED display screen actuating system's control chip.
Background
A Light Emitting Diode (LED) is a new solid semiconductor light source, and is widely used in lighting circuits, backlight modules or display panels. The LED driving chip is a power supply adjusting electronic device for driving the LED to emit light or the LED module assembly to normally work. According to different application requirements, control chips with different versions of LED driving systems are required, such as a commonly-used 4-channel control chip and an 8-channel control chip, in the prior art, a control chip of a specific version can only support one working mode, for example, can only support a 4-channel mode or an 8-channel mode, so that the design cost and the production cost of the control chip are high.
SUMMERY OF THE UTILITY MODEL
In view of this, an object of the present invention is to provide a control chip of an LED display screen driving system to solve the problem that the control chip of a specific version in the prior art can only support one working mode, so that the design cost and the production cost of the control chip of the LED display screen driving system are high.
The embodiment of the utility model provides a solve the technical scheme that above-mentioned technical problem adopted as follows:
the control chip of the LED display screen driving system is provided with a combined shift register, wherein the combined shift register comprises a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin:
the 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and is communicated with the level input pin, the CLK pin of each 2-bit shift register is connected in parallel and is communicated with the clock signal input pin, and the DIN pin of each 2-bit shift register is connected in series and is communicated with the data input pin;
the level signal input pin is used for controlling whether the control signals output by the first control signal output pin and the second control signal output pin are the same or not by receiving a high level signal or a low level signal, so that the selection of the working mode of the control chip is realized.
Preferably, the 2-bit shift register comprises a first D trigger and a second D trigger, and each D trigger is provided with a D pin, a ck pin, a Q pin and a set pin:
a set pin of the first D trigger 201 is connected with a set pin of the second D trigger 202 in parallel and then is connected with a DIR pin of the 2-bit shift register;
a ck pin of the first D trigger 201 is connected with a ck pin of the second D trigger 202 in parallel and then is connected with a CLK pin of the 2-bit shift register;
a D pin of the first D trigger 201 is connected with a DIN pin of the 2-bit shift register;
a pin Q of the first D trigger 201 is respectively connected with a pin D of the second D trigger 202 and a first control signal output pin of the 2-bit shift register;
and a Q pin of the second D trigger 202 is respectively connected with a second control signal output pin and a data output pin of the 2-bit shift register.
Preferably, the combination shift register is provided with four 2-bit shift registers.
Preferably, the level signal input pin receives a high level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register output different control signals, and the control chip has an 8-channel working mode.
Preferably, the level signal input pin receives a high level signal by turning on a power voltage. Preferably, the level signal input pin receives a low level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register output the same control signal, and the control chip has a 4-channel working mode.
Preferably, the level signal input pin receives a low level signal through a ground.
Preferably, the control chip further comprises a buffer, a multi-channel timing generation and control unit, and a gate control unit:
the shift register is communicated with the buffer and the multi-path time sequence generation and control unit through a bit line;
the multi-path time sequence generation and control unit is communicated with the gate control unit through a bit line;
the multi-path time sequence generating and controlling unit is provided with a chip selection function multiplexing pin which is used for receiving high level or low level signals, so that the working mode of the control chip is selected.
Preferably, the LED display screen driving circuit is further provided with a protection circuit, and the protection circuit is respectively connected to the buffer, the multi-path timing generation and control unit, and the gate control unit.
The control chip of the LED display screen driving system provided by the embodiment of the utility model is provided with a combined shift register which can support channel selection, the shift register is provided with a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin, a level signal received by the level signal input pin and a clock signal received by the clock signal input pin are parallelly input into each 2-bit shift register, a data signal received by the data input pin is serially input into each 2-bit shift register, a first control signal output pin and a second control signal output pin of each 2-bit shift register output control signals in parallel according to the level signal, the clock signal and the data signal received by each 2-bit shift register, when the level signal input pin receives a high level signal, the first control signal output pin and the second control signal output pin output different control signals, and when receiving a low level signal, the first control signal output pin and the second control signal output pin output the same control signal, so that the purpose that one control chip can support different working modes is achieved, and the design cost and the production cost are reduced.
Drawings
Fig. 1 is a schematic diagram of a module structure of a control chip of an LED display screen driving system according to a first embodiment of the present invention;
FIG. 2 is a block diagram of the combined shift register of FIG. 1;
FIG. 3 is a block diagram of the 2-bit shift register shown in FIG. 2.
The implementation, functional characteristics and advantages of the embodiments of the present invention will be further described with reference to the accompanying drawings.
Detailed Description
In order to make the technical problems, technical solutions and advantageous effects to be solved by the embodiments of the present invention clearer and more obvious, the embodiments of the present invention are further described in detail below with reference to the accompanying drawings and the embodiments. It should be understood that the description herein of specific embodiments is intended to be illustrative of the embodiments of the invention and is not intended to limit the embodiments of the invention.
The embodiment of the present invention provides a control chip suitable for a driving system of an LED display screen, please refer to fig. 1, the control chip includes a combination shift register 101, a buffer 102, a multi-path timing generation and control unit 103, a gate control unit 104 and a protection circuit 105.
The combined shift register 101 comprises a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin:
the 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and is communicated with the level input pin, the CLK pin of each 2-bit shift register is connected in parallel and is communicated with the clock signal input pin, and the DIN pin of each 2-bit shift register is connected in series and is communicated with the data input pin;
the level signal input pin is used for controlling whether the control signals output by the first control signal output pin and the second control signal output pin are the same or not by receiving a high level signal or a low level signal, so that the selection of the working mode of the control chip is realized.
In practical application, data transmission of each 2-bit shift register is realized by receiving a CLOCK signal by a CLOCK signal input pin and then transmitting the CLOCK signal to each 2-bit shift register in parallel, and when a CLOCK signal (CLK) with a certain frequency is input in sequence, data is sequentially sent to the registers by a DIN pin.
Referring to fig. 2, a possible scheme of the combined shift register of the present embodiment is shown. The combination shift register 101 in the described scheme comprises 4 2-bit shift registers. Each 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin CTRL0, and a second control signal output pin CTRL1, wherein:
DIR pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are all connected with a level signal input pin, so that parallel input of level signals is realized;
the CLK pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are all connected with the clock signal input pin to realize the parallel input of clock signals;
DIN pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203 and the 2-bit shift register 204 are connected in series and are connected with the data input pin, so that the serial input of data is realized.
The DIN pins of the 2-bit shift register 201, the 2-bit shift register 202, the 2-bit shift register 203, and the 2-bit shift register 204 are connected in series and connected to the data input pin, which means that:
the DIN pin of the 2-bit shift register 201 is connected with the logical data input pin of the shift register 101, the data output pin is connected with the DIN pin of the 2-bit shift register 202, the data output pin of the 2-bit shift register 202 is connected with the DIN pin of the 2-bit shift register 203, and the data output pin of the 2-bit shift register 203 is connected with the DIN pin of the 2-bit shift register 204.
Please refer to fig. 3, which is a block diagram of each 2-bit shift register of fig. 2.
The 2- bit shift registers 201, 202, 203 and 204 comprise a first D flip-flop 301 and a second D flip-flop 302, each D flip-flop is provided with a D pin, a ck pin, a Q pin and a set pin:
a set pin of the first D trigger 301 is connected with a set pin of the second D trigger 302 in parallel and then is connected with a DIR pin of the 2-bit shift register;
a ck pin of the first D trigger 301 is connected with a ck pin of the second D trigger 302 in parallel and then is connected with a CLK pin of the 2-bit shift register;
a D pin of the first D trigger 301 is connected with a DIN pin of the 2-bit shift register;
a pin Q of the first D trigger 301 is respectively connected with a pin D of the second D trigger 302 and a first control signal output pin of the 2-bit shift register;
and a Q pin of the second D trigger 302 is respectively connected with a second control signal output pin and a data output pin of the 2-bit shift register.
Thus, when the D pin of the first flip-flop 301 receives a high level signal, the control signal CTRL0 output from the Q pin of the first flip-flop 301 and the control signal CTRL1 output from the Q pin of the second flip-flop 302 are different, that is, the control signals output from the first control signal output pin and the second control signal output pin of the 2-bit shift register are different.
When the D pin of the first flip-flop 301 receives a low level signal, the control signal CTRL0 output from the Q pin of the first flip-flop 301 is the same as the control signal CTRL1 output from the Q pin of the second flip-flop 302, that is, the control signals output from the first control signal output pin and the second control signal output pin of the 2-bit shift register are the same.
Taking the combined shift register of fig. 2 as an example, 4 2-bit shift registers are provided, and when a level signal input pin of the combined shift register receives a high level signal and a control signal output by a first control signal output pin and a second control signal output pin of each 2-bit shift register is different, the working mode of the control chip is an 8-channel working mode; when the level signal input pin receives a low level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register output the same control signal, and the working mode of the control chip is a 4-channel working mode.
In practical applications, the level signal input pin of the control chip may receive a high level signal by switching on a power supply voltage, and receive a low level signal by grounding.
With continued reference to fig. 1, the combined shift register 101 is in communication with the buffer 102 and the multi-path timing generation and control unit 103 via bit lines;
the multi-path time sequence generating and controlling unit 103 is communicated with the grid controlling unit 104 through a bit line;
the multi-path time sequence generating and controlling unit 103 is provided with a chip selection function multiplexing pin, and the chip selection function multiplexing pin is used for receiving high level or low level signals so as to select the working mode of the driving circuit;
the protection circuit 105 is connected to the buffer 102, the multi-channel timing generation and control unit 103, and the gate control unit 102, respectively.
The protection circuit 105 of the present embodiment may include:
the abnormality detection sub-circuit is used for outputting channel voltage short-circuit protection and chip over-temperature protection;
the output channel voltage short-circuit protection sub-circuit is used for detecting the voltage of output channels (OUT 0-OUT 7) in real time, when the voltage is lower than 0.1V, the channel is considered to enter a short-circuit state, the channel is immediately turned off and locked, and the power supply needs to be restarted to be released;
and the chip over-temperature protection sub-circuit is used for triggering the over-temperature protection module when the temperature of the chip exceeds 135 ℃, outputting a high level (keeping a low level during normal work), and switching off an output channel so as to reduce the temperature. When the temperature is reduced to 115 ℃, the output channel is opened again;
the delay protection sub-circuit is used for realizing a delay protection mechanism and has the function of shielding instant voltage overshoot of 8 (or 4) output channels during opening and closing so as to prevent misjudgment of the protection circuit. A delay determination of about 50nm is typically achieved with cascaded directors. That is, the state detected by the protection module is considered to be the valid state after the output channel is turned on or off by 50 nm.
In this embodiment, the abnormality detection sub-circuit and the delay protection sub-circuit are combined, and an enable signal is output after internal logic operation, which is used for controlling both an output channel and a cascade signal (DOUT).
The specific circuit of the protection circuit 105 of this embodiment may be related to actual needs, or may adopt an existing protection circuit, which is not described herein.
With continued reference to fig. 1, the main pins of the control chip are illustrated:
DIN receives external input data, and is connected to a data input pin of the combination shift register 101; BK is an enable end, high level is effective, and low level turns off an output channel; the CLK pin receives an external clock signal and a clock signal input pin of the combined shift register 101 to realize shifting, number sending and time sequence generation; the DIR pin is a mode selection (chip select) pin, and is connected to a level signal input pin of the combination shift register 101, for selecting an 8-channel or 4-channel output mode.
The control chip of this embodiment is provided with a combined shift register capable of supporting channel selection, the shift register is provided with a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin, a level signal received by the level signal input pin and a clock signal received by the clock signal input pin are input into each 2-bit shift register in parallel, a data signal received by the data input pin is input into each 2-bit shift register in series, a first control signal output pin and a second control signal output pin of each 2-bit shift register output control signals in parallel according to the level signal, the clock signal and the data signal received by each 2-bit shift register, when the level signal input pin receives a high level signal, the control signals output by the first control signal output pin and the second control signal output pin are different, when receiving a low level signal, the control signals output by the first control signal output pin and the second control signal output pin are the same, so that the purpose that one control chip supports different working modes is achieved, and the design cost and the production cost are reduced.
The preferred embodiments of the present invention have been described above with reference to the accompanying drawings, and are not intended to limit the scope of the embodiments of the invention. Any modifications, equivalents and improvements which may occur to those skilled in the art without departing from the scope and spirit of the embodiments of the present invention are intended to be within the scope of the claims of the embodiments of the present invention.
Claims (9)
1. The control chip of the LED display screen driving system is characterized in that the control chip is provided with a combined shift register, and the combined shift register comprises a level signal input pin, at least two 2-bit shift registers, a clock signal input pin and a data input pin:
the 2-bit shift register is provided with a DIR pin, a CLK pin, a DIN pin, a first control signal output pin and a second control signal output pin, the DIR pin of each 2-bit shift register is connected in parallel and is communicated with the level signal input pin, the CLK pin of each 2-bit shift register is connected in parallel and is communicated with the clock signal input pin, and the DIN pin of each 2-bit shift register is connected in series and is communicated with the data input pin;
the level signal input pin is used for controlling whether the control signals output by the first control signal output pin and the second control signal output pin are the same or not by receiving a high level signal or a low level signal, so that the selection of the working mode of the control chip is realized.
2. The control chip of the LED display driving system according to claim 1, wherein the 2-bit shift register comprises a first D flip-flop and a second D flip-flop, each D flip-flop has a D pin, a ck pin, a Q pin, and a set pin:
a set pin of the first D trigger 201 is connected with a set pin of the second D trigger 202 in parallel and then is connected with a DIR pin of the 2-bit shift register;
a ck pin of the first D trigger 201 is connected with a ck pin of the second D trigger 202 in parallel and then is connected with a CLK pin of the 2-bit shift register;
a D pin of the first D trigger 201 is connected with a DIN pin of the 2-bit shift register;
a pin Q of the first D trigger 201 is respectively connected with a pin D of the second D trigger 202 and a first control signal output pin of the 2-bit shift register;
and a Q pin of the second D trigger 202 is respectively connected with a second control signal output pin and a data output pin of the 2-bit shift register.
3. The control chip of the driving system for the LED display screen according to claim 1 or 2, wherein the combination shift register is provided with four 2-bit shift registers.
4. The control chip of the LED display screen driving system according to claim 3, wherein the level signal input pin receives a high level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register output different control signals, and the control chip operating mode is an 8-channel operating mode.
5. The control chip of the LED display screen driving system according to claim 4, wherein the level signal input pin receives a high level signal by turning on a power voltage.
6. The control chip of the LED display driving system according to claim 3, wherein the level signal input pin receives a low level signal, the first control signal output pin and the second control signal output pin of each 2-bit shift register output the same control signal, and the control chip has a 4-channel operation mode.
7. The control chip of the LED display screen driving system according to claim 6, wherein the level signal input pin receives a low level signal through a ground.
8. The control chip of the LED display driving system according to claim 1, wherein the control chip further comprises a buffer, a multi-channel timing generation and control unit, and a gate control unit:
the shift register is communicated with the buffer and the multi-path time sequence generation and control unit through a bit line;
the multi-path time sequence generation and control unit is communicated with the gate control unit through a bit line;
the multi-path time sequence generating and controlling unit is provided with a chip selection function multiplexing pin which is used for receiving high level or low level signals, so that the working mode of the control chip is selected.
9. The control chip of the LED display driving system according to claim 8, wherein the LED display driving circuit further comprises a protection circuit, and the protection circuit is connected to the buffer, the multi-channel timing generation and control unit, and the gate control unit, respectively.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310590A (en) * | 2019-06-17 | 2019-10-08 | 深圳市帝麦德斯科技有限公司 | A kind of control chip of LED display drive system |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110310590A (en) * | 2019-06-17 | 2019-10-08 | 深圳市帝麦德斯科技有限公司 | A kind of control chip of LED display drive system |
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