CN101667400A - Driving device for liquid crystal display - Google Patents
Driving device for liquid crystal display Download PDFInfo
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- CN101667400A CN101667400A CN200810213781A CN200810213781A CN101667400A CN 101667400 A CN101667400 A CN 101667400A CN 200810213781 A CN200810213781 A CN 200810213781A CN 200810213781 A CN200810213781 A CN 200810213781A CN 101667400 A CN101667400 A CN 101667400A
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Abstract
The invention discloses a driving device for a liquid crystal display, which is used for avoiding operational errors of a shift register caused by noise on a clock signal. The driving device comprisesthe shift register, a receiving end, a noise canceling circuit and a control signal generation circuit, wherein the receiving end is used for receiving a first clock signal; the noise canceling circuit is coupled to the receiving end and used for canceling the noise of the first clock signal and delaying the first clock signal for a preset time so as to generate a second clock signal; and the control signal generation circuit is coupled to the receiving end and the noise canceling circuit and used for generating a first control signal and a second control signal according to the first and second clock signals so as to control the shift register.
Description
Technical field
The present invention relates to a kind of drive unit that is used for LCD, relate in particular to a kind of drive unit that is used for avoiding noise on the clock signal to cause the LCD operating mistake.
Background technology
In the driving circuit of LCD, shift register (Shift Register) is a DLC (digital logic circuit) that extensively is used, it comes according to a clock signal, provide a pulse signal to a plurality of signal output parts in regular turn, make the driving circuit of LCD be able to outputting data signals or output signal line by line, to drive corresponding pixel with pursuing row.
Please refer to Fig. 1, Fig. 1 is the functional block diagram of a gate driver circuit 10 of known LCD.Gate driver circuit 10 consists predominantly of a shift-register circuit 110 and an output buffer 120.Shift register 110 is used for producing pulse signal Q1～Qn in regular turn according to an initial pulse signal DIN and a clock signal clk.120 of output buffers carry out operations such as voltage amplification according to pulse signal Q1～Qn, with output gate drive signal X1～Xn to corresponding sweep trace.In addition, gate driver circuit 10 includes an output control circuit 130 in addition, be used for according to an output enable signal OE, pulse signals Q1～Qn modulates, with the situation generation of avoiding adjacent gate drive signal X1～Xn to make the mistake and drive LCD because of overlapping mutually.Detail operations about liquid crystal display drive circuit is known by industry, does not give unnecessary details at this.
In general, shift register is made up of the trigger of a plurality of serial connections, and it can be used to the binary bit of input is done temporary, the delay of data and serial and and operation such as line output conversion.Please refer to Fig. 2, Fig. 2 is the synoptic diagram of a known shift-register circuit 20.Shift-register circuit 20 can be the shift register 110 among Fig. 1, and its trigger FF1～FFn by serial connection is formed.Each trigger includes an input end D, an output terminal Q and a clock input end C, and it is used for the clock signal clk that received according to input end of clock C, and the signal level of input end D is passed to output terminal Q.Under general situation, the output terminal system of each trigger is coupled to the input end of time one-level trigger, therefore, when the input end of first trigger FF1 receives an input signal DIN, shift-register circuit 20 can down be transmitted the level one-level one-level of input signal DIN ground according to clock signal clk, with output pulse signal Q1～Qn in regular turn.About the coherent signal sequential of shift-register circuit 20, as shown in Figure 3.
Please continue with reference to figure 4, Fig. 4 is the synoptic diagram of a known trigger circuit 40.As shown in Figure 4, flip-flop circuit generally is made up of the two-stage latch cicuit, and its mode of operation is summarized as follows.When clock signal clk was low level, flip-flop circuit 40 can be stored to first order latch cicuit 41 inside with the logic level of input signal DIN, and second level latch cicuit 42 is closed condition (Disabled) at this moment; And when clock signal clk became high level by low level, first order latch cicuit 41 was closed, and second level latch cicuit 42 is opened, to export the data that 41 accesses of first order latch cicuit are arrived.In the case, when clock signal clk when unexpected pulse signal produces because of noise has, the situation that shift register has operating mistake easily takes place.
For instance, please refer to Fig. 5, Fig. 5 has illustrated the situation that known shift register is made a mistake by noise because of clock signal.As shown in Figure 5, when clock signal clk has unexpected down a pulse signal, each flip-flop circuit in the shift register can carry out the access of data and the action of output according to the pulse signal of mistake, and causes the pulse signal of shift register output error.Yet, because display panels generally need rely on multiple signal simultaneously and operate the coupling effect between signal, electromagnetic coupled for example, tend to cause the clock signal of driving circuit to produce noise, make the shift register operating mistake, and cause display frame unusual.
Therefore, how avoiding noise that clock signal is caused interference, is an important topic of design liquid crystal display drive circuit.
Summary of the invention
Therefore, the present invention promptly is to provide a kind of drive unit that is used for LCD.
The invention discloses a kind of drive unit that is used for LCD.This drive unit includes a shift register, a receiving end, a noise canceller circuit and a control signal generation circuit.This receiving end is used for receiving one first clock signal.This noise canceller circuit is coupled to this receiving end, is used for eliminating the noise of this first clock signal, and with this first clock signal delay, one Preset Time, to produce a second clock signal.This control signal generation circuit is coupled to this receiving end and this noise canceller circuit, is used for producing one first control signal and one second control signal, to control this shift register according to this first clock signal and this second clock signal.
The present invention discloses a kind of drive unit that is used for LCD in addition.This drive unit includes a shift register, a receiving end, a noise canceller circuit, a pulse-width modulator and a control signal generation circuit.This receiving end is used for receiving one first clock signal.This noise canceller circuit is coupled to this receiving end, is used for eliminating the noise of this first clock signal, and with this first clock signal delay, one Preset Time, to produce a second clock signal.This pulse-width modulator is coupled to this noise canceller circuit, is used for the pulse width of this second clock signal is modulated, to produce one the 3rd clock signal.This control signal generation circuit is coupled to this receiving end and this pulse-width modulator, is used for according to this first clock signal and the 3rd clock signal, produces one first control signal and one second control signal, to control this shift register.
The present invention discloses a kind of drive unit that is used for LCD in addition.This drive unit includes a shift register, a receiving end, a noise canceller circuit and a control signal generation circuit.This receiving end is used for receiving one first clock signal.This noise canceller circuit is coupled to this receiving end, is used for eliminating the noise of this first clock signal, and with this first clock signal delay, one Preset Time, to produce a second clock signal.This control signal generation circuit is coupled to this receiving end and this noise canceller circuit, be used for according to this first clock signal and an output enable (Output Enable, OE) signal, produce one first control signal, and, produce one second control signal according to this first clock signal and this second clock signal.Wherein, this output enable signal is used for modulating the output signal of this drive unit, overlap mutually to avoid adjacent output signal, and this first control signal and this second control signal is used for controlling this shift register.
Description of drawings
Fig. 1 is the functional block diagram of a gate driver circuit of known LCD.
Fig. 2 is the synoptic diagram of a known shift-register circuit.
Fig. 3 is the synoptic diagram of the coherent signal sequential of shift-register circuit among Fig. 2.
Fig. 4 is the synoptic diagram of a known trigger circuit.
Fig. 5 has illustrated the situation that known shift register is made a mistake by noise because of clock signal.
Fig. 6 is used for the synoptic diagram of a drive unit of LCD for the present invention.
Fig. 7 is the synoptic diagram of the coherent signal sequential of drive unit among Fig. 6.
Fig. 8 is an embodiment synoptic diagram of noise canceller circuit of the present invention.
Fig. 9 is the function mode synoptic diagram of noise canceller circuit among Fig. 8.
Figure 10 is the embodiment synoptic diagram corresponding to a flip-flop circuit of drive unit of the present invention.
Figure 11 is the coherent signal sequential synoptic diagram corresponding to a shift register of drive unit of the present invention.
Figure 12～14 are the coherent signal sequential synoptic diagram of drive unit under different noise situations among Fig. 6.
Figure 15 has illustrated that a gate drivers uses the function situation of output enable signal modulated output signal.
Figure 16 uses the signal timing diagram that the output enable signal is eliminated noise for drive unit of the present invention.
Figure 17 is used for the synoptic diagram of another drive unit of LCD for the present invention.
Figure 18 is the synoptic diagram of the coherent signal sequential of drive unit among Figure 17.
Figure 19～22 are the coherent signal sequential synoptic diagram of drive unit under different noise situations among Figure 17.
[main element symbol description]
10 gate driver circuits
110,20,65,75 shift-register circuits
40,90 flip-flop circuits
120 output buffers
130 output control circuits
The DIN initial pulse signal
CLK, CLK2, CLK2M clock signal
OE output enable signal
Q1～Qn pulse signal
X1～Xn gate drive signal
FF1～FFn trigger
The D input end
The Q output terminal
The C input end of clock
41,42,91,92 latch cicuits
60,70 drive units
61,71 receiving ends
62,72 noise canceller circuits
73 pulse-width modulators
63,74 control signal generation circuit
SCK1, SCK2 control signal
620 resistance capacitance formula filtering circuits
625 comparers
The VTH threshold voltage
Vx filtering result
Embodiment
Please refer to Fig. 6, Fig. 6 is used for the synoptic diagram of a drive unit 60 of LCD for the present invention.Drive unit 60 is used for avoiding the noise on the clock signal to cause the faulty operation of shift register, and it includes a receiving end 61, a noise canceller circuit 62, a control signal generation circuit 63 and a shift register 65.Receiving end 61 is used for receiving a clock signal clk.Noise canceller circuit 62 is coupled to receiving end 61, is used for the noise of filtering clock signal clk, and clock signal clk is postponed a Preset Time, to produce a clock signal CLK2.Control signal generation circuit 63 is coupled to receiving end 61 and noise canceller circuit 62, is used for according to clock signal clk and clock signal CLK2, produces control signal SCK1 and SCK2, with the drive signal of control shift register 65 output LCD.
Therefore, the present invention produces control signals of shift registers by original clock signal and the clock signal of removing noise, causes the situation of LCD operating mistake to avoid noise on the clock signal.Preferably, control signal SCK1 is at clock signal clk and produces when high logic level and clock signal clk 2 are in low logic level; And control signal SCK2 is at clock signal clk and produces when low logic level and clock signal clk 2 are in high logic level; The coherent signal sequential as shown in Figure 7.
Please continue with reference to figure 8, Fig. 8 is an embodiment synoptic diagram of noise canceller circuit 62 of the present invention.Noise canceller circuit 62 includes a resistance capacitance formula filtering circuit 620 and a comparer 625.Resistance capacitance formula filtering circuit 620 is coupled to receiving end 61, is used for clock signal clk is carried out filtering, to eliminate the noise of clock signal clk.Comparer 625 is coupled to resistance capacitance formula filtering circuit 620, be used for according to a threshold voltage VTH, to the filtering of clock signal as a result Vx compare, with clocking CLK2.Wherein, comparer 625 is in the filtering of clock signal when Vx is greater than threshold voltage VTH as a result, the high level part of clocking CLK2, and in the filtering of clock signal when Vx is less than thresholding electricity VTH as a result, the low level part of clocking CLK2.Detailed operation mode about noise canceller circuit 62 please refer to Fig. 9.Wherein, the preset time T delay that postponed of clock signal clk 2 is according to the time constant of resistance capacitance formula filtering circuit 620 and the size decision of threshold voltage VTH.
In addition, because each flip-flop circuit of shift register 65 is made up of the two-stage latch cicuit, so the present invention can control the two-stage latch cicuit of trigger respectively by control signal SCK1 and SCK2, correctly to produce the drive signal of LCD.For instance, please refer to Figure 10, Figure 10 is the embodiment synoptic diagram corresponding to a flip-flop circuit 90 of drive unit 60 of the present invention.Flip-flop circuit 90 is used for realizing the flip-flop circuit in the shift register 65, and it includes a first order latch cicuit 91 and a second level latch cicuit 92.Compared to the flip-flop circuit 40 of Fig. 4, first order latch cicuit 91 is stored a logical level of input signals according to control signal SCK2, and second level latch cicuit 92 is exported the level that first order latch cicuit 91 is stored then according to control signal SCK1.
Thus, when shift register receives control signal SCK2, each flip-flop circuit can be stored to logical level of input signals first order latch cicuit inside, and when receiving control signal SCK1, then exports the logic level that the access of first order latch cicuit institute is arrived.Coherent signal sequential about shift register please refer to Figure 11.In Figure 11, DIN represents the input signal of shift register, Q1～Q3 then represent shift register in regular turn output pulse signal.
Therefore, by control signal SCK1 and SCK2, drive unit 60 may command shift registers of the present invention correctly produce and drive the required pulse signal of LCD, cause the situation of LCD operating mistake to avoid noise on the clock signal.Please refer to Figure 12～14, Figure 12～14 are the coherent signal sequential synoptic diagram of drive unit 60 of the present invention under different noise situations.As shown in figure 12, if the noise of clock signal clk is present in clock signal clk when being high level and clock signal clk 2 for low level signal spacing, the control signal SCK1 that control signal generation circuit 63 is exported can become two less pulses.In this case, because each flip-flop circuit do not have the new data of access, though therefore carried out twice output action, the pulse signal that shift register is exported still keeps normally, and The noise on the subject clock signal not.As shown in figure 13, when the noise of clock signal clk was present in clock signal clk and CLK2 and is all the signal spacing of high level, control signal SCK2 had extra pulse and produces.In this case, each trigger just carries out access to new data in advance, so the pulse signal that shift register is exported still keeps normally, and The noise on the subject clock signal not.In addition, as shown in figure 14, if the noise on the clock signal is present in clock signal clk when being low level and clock signal clk 2 for the signal spacing of high level, control signal SCK2 can become two less pulses.At this moment, trigger just carries out the action of twice access to same data, so the pulse signal exported of shift register The noise on the subject clock signal not still.
Preferably, drive unit of the present invention can be a gate drivers (GateDriver) of LCD.In this case, control signal generation circuit 63 in addition can (OutputEnable, OE) signal produce control signal SCK1, the interference that control signal SCK1 is produced with the noise of eliminating clock signal clk according to an output enable.At first, please refer to Figure 15, Figure 15 has illustrated that a gate drivers uses the function situation of output enable signal modulated output signal.Wherein, DIN represents the input signal of shift register, Q1～Q3 represent shift register in regular turn output pulse signal, the drive signal that on behalf of gate drivers, X1～X3 then export.As shown in figure 15, output enable signal OE is used for pulse signals Q1～Q3 and modulates, and takes place to avoid adjacent gate drive signal X1～Xn situation that drives LCD that makes the mistake because of overlapping mutually.
Because clock signal clk carries out forward transition (Positive Transition) during for low level at output enable signal OE usually, produce next pulse signal with the control shift register, so control signal generation circuit of the present invention 63 can further go up the noise of improper generation by output enable signal OE filtering control signal SCK1.In this case, when output enable signal OE was low level, control signal generation circuit 63 can normally produce control signal SCK1, and when output enable signal OE is high level, then stops to export control signal SCK1.
Please refer to Figure 16, Figure 16 uses the signal timing diagram that the output enable signal is eliminated noise for drive unit 60 of the present invention.Wherein, on behalf of control signal SCK1, hatched example areas be output the part of enable signal OE institute filtering.As shown in figure 16, when the noise on the clock signal clk is present in clock signal clk and CLK2 and is all low level signal spacing, the noise on the control signal SCK1 can be further by in addition filtering of output enable signal OE.Thus, no matter there is which kind of noise situations on the clock signal, drive unit 60 of the present invention all can correctly produce control signals of shift registers SCK1 and SCK2, exports in regular turn with the control shift register and drives the required pulse signal of LCD.
In sum, drive unit 60 of the present invention is except the clock signal by original clock signal and removal noise, can produce control signals of shift registers by the output enable signal in addition, drive the required pulse signal of LCD so that shift register correctly produces, and be not subjected to the influence of various noise situations on the clock signal clk.
In addition, except aforesaid mode, the present invention also can directly pass through original clock signal CLK and output enable signal OE, produces control signal SCK1; Please consult Figure 16 again at this, as shown in Figure 16, control signal SCK1 is positioned at high-voltage level in clock signal clk, and output enable signal OE produces when being positioned at low voltage level, therefore, the present invention also can only produce control signal SCK1 with reference to original clock signal and output enable signal OE according to aforesaid mechanism, so corresponding variation also belongs to category of the present invention.
On the other hand, please refer to Figure 17, Figure 17 is used for the synoptic diagram of another drive unit 70 of LCD for the present invention.Drive unit 70 includes a receiving end 71, a noise canceller circuit 72, a pulse-width modulator 73, a control signal generation circuit 74 and a shift register 75.Receiving end 71 is used for receiving a clock signal clk.Noise canceller circuit 72 is coupled to receiving end 71, is used for the noise of filtering clock signal clk, and clock signal clk is postponed a Preset Time, to produce a clock signal CLK2.Pulse-width modulator 73 is coupled to noise canceller circuit 72, is used for the pulse width of clock signal clk 2 is modulated, to produce a clock signal CLK2M.Control signal generation circuit 74 is coupled to receiving end 71 and pulse-width modulator 73, is used for according to clock signal clk 1 and clock signal CLK2M, produces control signal SCK1 and SCK2, with the drive signal of control shift register 75 output LCD.
Therefore, compared to drive unit 60, the pulse width that drive unit 70 of the present invention prolongs clock signal CLK2 by pulse-width modulator 73 in addition is to increase the scope of the noise on the filtering clock signal clk.Coherent signal sequential about drive unit 70 of the present invention please refer to Figure 18.Wherein, the pulse width that on behalf of clock signal clk 2, dash area prolonged, it can be adjusted according to the actual requirements, to produce the clock signal clk 2M of different pulse widths.
In this case, please refer to Figure 19～22, Figure 19～22 are the coherent signal sequential synoptic diagram of drive unit 70 of the present invention under different noise situations.In Figure 19～21, the function mode of drive unit 60 is similar in the function mode of drive unit 70 and Figure 12～14, does not repeat them here.In Figure 22, when the noise of clock signal clk was present in clock signal clk and CLK2 and is all low level signal spacing, this moment, control signal SCK1 can produce extra pulse, made trigger export in advance and make the mistake.In this case, the present invention can prolong the pulse width of clock signal CLK2 by pulse-width modulator 73, goes up extra pulse with filtering control signal SCK1, and makes not The noise on the subject clock signal of pulse signal that shift register exports.
Thus, no matter there is which kind of noise situations on the clock signal, drive unit 70 of the present invention all can correctly produce control signals of shift registers SCK1 and SCK2, exports in regular turn with the control shift register and drives the required pulse signal of LCD.
Note that above-mentioned drive unit 60 and 70 only is used as of the present invention illustrating, and be not restriction of the present invention that those skilled in the art are when making suitable modification according to the actual requirements.For instance, control signal generation circuit of the present invention also can directly produce control signal SCK1 according to clock signal clk 1 and output enable signal OE, and, producing control signal SCK2 according to clock signal clk and CLK2, corresponding variation like this also belongs to scope of the present invention.
In addition, drive unit of the present invention is not limited to gate drivers, and it also can be implemented among the source electrode driver (Source Driver), causes the faulty operation of shift register to avoid the noise on the clock signal, and causes display frame unusual.
In sum, the present invention is by original clock signal and the clock signal of removing noise, produce control signals of shift registers, drive the required pulse signal of LCD, and be not subjected to the influence of various noise situations on the clock signal so that shift register correctly produces.Thus, the present invention can effectively improve the usefulness of liquid crystal display drive circuit.
The above only is the preferred embodiments of the present invention, and all equalizations of doing according to claims of the present invention change and modify, and all should belong to covering scope of the present invention.
Claims (23)
1. drive unit that is used for a LCD includes:
One shift register;
One receiving end is used for receiving one first clock signal;
One noise canceller circuit is coupled to this receiving end, is used for eliminating the noise of this first clock signal, and with this first clock signal delay, one Preset Time, to produce a second clock signal; And
One control signal generation circuit is coupled to this receiving end, this noise canceller circuit and this shift register, is used for producing one first control signal and one second control signal, to control this shift register according to this first clock signal and this second clock signal.
2. drive unit as claimed in claim 1, wherein this control signal generation circuit is when this first clock signal is in a high logic level and this second clock signal and is in a low logic level, produce this first control signal, and when this first clock signal is in this low logic level and this second clock signal and is in this high logic level, produce this second control signal.
3. drive unit as claimed in claim 1, wherein this shift register includes the trigger of a plurality of serial connections, each trigger includes a first order latch cicuit and a second level latch cicuit, this first order latch cicuit is used for according to this second control signal, storage one input data, this second level latch cicuit is used for exporting the data that this first order latch cicuit is stored according to this first control signal.
4. drive unit as claimed in claim 1, wherein this noise canceller circuit includes:
One resistance capacitance formula filtering circuit is coupled to this receiving end, is used for this first clock signal is carried out filtering, to eliminate the noise of this first clock signal; And
One comparer, be coupled to this resistance capacitance formula filtering circuit, be used for according to a threshold voltage, filtering result to this first clock signal compares, producing this second clock signal, and this comparer during greater than this threshold voltage, produces this second clock signal with high logic level in the filtering result of this first clock signal, and during less than this threshold voltage, produce this second clock signal with low logic level in the filtering result of this first clock signal.
5. drive unit as claimed in claim 4, wherein this Preset Time of being postponed of this first clock signal is according to the size decision of this threshold voltage.
6. drive unit as claimed in claim 1, wherein this drive unit is a gate drivers.
7. drive unit as claimed in claim 6, wherein this control signal generation circuit is in addition according to an output enable signal, produce this first control signal, to eliminate the noise of this first control signal, this output enable signal is used for modulating the output signal of this gate drivers, overlaps mutually to avoid adjacent output signal.
8. drive unit as claimed in claim 7, wherein this control signal generation circuit produces this first control signal when this output enable signal is in this low logic level.
9. drive unit as claimed in claim 1, wherein this drive unit is the one source pole driver.
10. drive unit that is used for a LCD includes:
One shift register;
One receiving end is used for receiving one first clock signal;
One noise canceller circuit is coupled to this receiving end, is used for eliminating the noise of this first clock signal, and with this first clock signal delay, one Preset Time, to produce a second clock signal;
One pulse-width modulator is coupled to this noise canceller circuit, is used for the pulse width of this second clock signal is modulated, to produce one the 3rd clock signal; And
One control signal generation circuit, be coupled to this receiving end, this pulse-width modulator and this shift register, be used for according to this first clock signal and the 3rd clock signal, produce one first control signal and one second control signal, to control this shift register.
11. drive unit as claimed in claim 10, wherein this pulse-width modulator is used for prolonging the pulse width of this second clock signal, to produce the 3rd clock signal.
12. drive unit as claimed in claim 10, wherein this control signal generation circuit is when this first clock signal is in a high logic level and the 3rd clock signal and is in a low logic level, produce this first control signal, and when this first clock signal is in this low logic level and the 3rd clock signal and is in this high logic level, produce this second control signal.
13. drive unit as claimed in claim 10, wherein this shift register includes the trigger of a plurality of serial connections, each trigger includes a first order latch cicuit and a second level latch cicuit, this first order latch cicuit is used for according to this second control signal, storage one input data, this second level latch cicuit is used for exporting the data that this first order latch cicuit is stored according to this first control signal.
14. drive unit as claimed in claim 10, wherein this noise canceller circuit includes:
One resistance capacitance formula filtering circuit is coupled to this receiving end, is used for this first clock signal is carried out filtering, to eliminate the noise of this first clock signal; And
One comparer, be coupled to this resistance capacitance formula filtering circuit, be used for according to a threshold voltage, filtering result to this first clock signal compares, producing this second clock signal, and this comparer during greater than this threshold voltage, produces this second clock signal with high logic level in the filtering result of this first clock signal, and during less than this threshold voltage, produce this second clock signal with low logic level in the filtering result of this first clock signal.
15. drive unit as claimed in claim 14, wherein this Preset Time of being postponed of this first clock signal is according to the size decision of this threshold voltage.
16. drive unit as claimed in claim 10, wherein this drive unit is a gate drivers.
17. drive unit as claimed in claim 10, wherein this drive unit is the one source pole driver.
18. a drive unit that is used for a LCD includes:
One shift register;
One receiving end is used for receiving one first clock signal;
One noise canceller circuit is coupled to this receiving end, is used for eliminating the noise of this first clock signal, and with this first clock signal delay, one Preset Time, to produce a second clock signal; And
One control signal generation circuit, be coupled to this receiving end, this noise canceller circuit and this shift register, be used for according to this first clock signal and an output enable signal, produce one first control signal, and according to this first clock signal and this second clock signal, produce one second control signal, this output enable signal is used for modulating the output signal of this drive unit, avoiding adjacent output signal to overlap mutually, and this first control signal and this second control signal are used for controlling this shift register.
19. drive unit as claimed in claim 18, wherein this control signal generation circuit is when this first clock signal is in a high logic level and this output enable signal and is in a low logic level, produce this first control signal, and when this first clock signal is in this low logic level and this second clock signal and is in this high logic level, produce this second control signal.
20. drive unit as claimed in claim 18, wherein this shift register includes the trigger of a plurality of serial connections, each trigger includes a first order latch cicuit and a second level latch cicuit, this first order latch cicuit is used for according to this second control signal, storage one input data, this second level latch cicuit is used for exporting the data that this first order latch cicuit is stored according to this first control signal.
21. drive unit as claimed in claim 18, wherein this noise canceller circuit includes:
One resistance capacitance formula filtering circuit is coupled to this receiving end, is used for this first clock signal is carried out filtering, to eliminate the noise of this first clock signal; And
One comparer, be coupled to this resistance capacitance formula filtering circuit, be used for according to a threshold voltage, filtering result to this first clock signal compares, producing this second clock signal, and this comparer during greater than this threshold voltage, produces this second clock signal with high logic level in the filtering result of this first clock signal, and during less than this threshold voltage, produce this second clock signal with low logic level in the filtering result of this first clock signal.
22. drive unit as claimed in claim 21, wherein this Preset Time of being postponed of this first clock signal is according to the size decision of this threshold voltage.
23. drive unit as claimed in claim 18, wherein this drive unit is a gate drivers.
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| CN2008102137817A CN101667400B (en) | 2008-09-04 | 2008-09-04 | Driving device for liquid crystal display |
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| CN2008102137817A CN101667400B (en) | 2008-09-04 | 2008-09-04 | Driving device for liquid crystal display |
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| CN101667400B CN101667400B (en) | 2011-09-28 |
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| CN102693692A (en) * | 2011-03-25 | 2012-09-26 | 京东方科技集团股份有限公司 | Shift register unit and LCD (liquid crystal display) grid driving device |
| CN105427826A (en) * | 2016-01-07 | 2016-03-23 | 京东方科技集团股份有限公司 | GOA driving circuit and driving method thereof, and display apparatus |
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| CN111653229A (en) * | 2020-06-22 | 2020-09-11 | 武汉京东方光电科技有限公司 | Gate drive circuit and display device |
| WO2021051453A1 (en) * | 2019-09-18 | 2021-03-25 | Tcl华星光电技术有限公司 | Goa circuit drive system and display apparatus |
| WO2023168762A1 (en) * | 2022-03-11 | 2023-09-14 | 深圳市华星光电半导体显示技术有限公司 | Display driving circuit, display driving device, and display driving method |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007178784A (en) * | 2005-12-28 | 2007-07-12 | Oki Electric Ind Co Ltd | Driving device |
| JP4654923B2 (en) * | 2006-01-26 | 2011-03-23 | カシオ計算機株式会社 | Shift register circuit and display driving device |
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2008
- 2008-09-04 CN CN2008102137817A patent/CN101667400B/en not_active Expired - Fee Related
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102693692A (en) * | 2011-03-25 | 2012-09-26 | 京东方科技集团股份有限公司 | Shift register unit and LCD (liquid crystal display) grid driving device |
| CN105427826A (en) * | 2016-01-07 | 2016-03-23 | 京东方科技集团股份有限公司 | GOA driving circuit and driving method thereof, and display apparatus |
| CN106297652A (en) * | 2016-10-08 | 2017-01-04 | 杭州视芯科技有限公司 | LED display and protection circuit thereof and control method |
| CN106297652B (en) * | 2016-10-08 | 2019-08-27 | 杭州视芯科技有限公司 | LED display and its control method |
| WO2021051453A1 (en) * | 2019-09-18 | 2021-03-25 | Tcl华星光电技术有限公司 | Goa circuit drive system and display apparatus |
| CN111653229A (en) * | 2020-06-22 | 2020-09-11 | 武汉京东方光电科技有限公司 | Gate drive circuit and display device |
| CN111653229B (en) * | 2020-06-22 | 2022-07-15 | 武汉京东方光电科技有限公司 | Gate drive circuit and display device |
| WO2023168762A1 (en) * | 2022-03-11 | 2023-09-14 | 深圳市华星光电半导体显示技术有限公司 | Display driving circuit, display driving device, and display driving method |
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|---|---|
| CN101667400B (en) | 2011-09-28 |
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