JPH10290058A - Printed-circuit board - Google Patents
Printed-circuit boardInfo
- Publication number
- JPH10290058A JPH10290058A JP9947797A JP9947797A JPH10290058A JP H10290058 A JPH10290058 A JP H10290058A JP 9947797 A JP9947797 A JP 9947797A JP 9947797 A JP9947797 A JP 9947797A JP H10290058 A JPH10290058 A JP H10290058A
- Authority
- JP
- Japan
- Prior art keywords
- qfp
- package
- lands
- bga
- land
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/0286—Programmable, customizable or modifiable circuits
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/02—Details
- H05K1/11—Printed elements for providing electric connections to or between printed circuits
- H05K1/111—Pads for surface mounting, e.g. lay-out
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
- H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
- H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
- H05K3/341—Surface mounted components
- H05K3/3431—Leadless components
- H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
Abstract
Description
【0001】[0001]
【発明の属する技術分野】本発明は、プリント基板に関
するもので、特にランド配置とその配線方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a printed circuit board, and more particularly to a land arrangement and a wiring method thereof.
【0002】[0002]
【従来の技術】従来、QFP等の半導体パッケージを搭
載するプリント基板においては、例えば、QFPを搭載
していたプリント基板において、そのQFPと同じ機能
を有し、パッケージの形態のみが異なるBGAの搭載に
置き換える場合には、QFPを搭載できるランドを有す
るプリント基板のQFPのランドを、BGAが搭載でき
るランドに変更した別のプリント基板を製造し、BGA
の搭載をする。2. Description of the Related Art Conventionally, in a printed circuit board on which a semiconductor package such as a QFP is mounted, for example, in a printed circuit board on which a QFP is mounted, a BGA having the same function as the QFP and having a different package form is used. In the case of replacing with a BGA, another printed circuit board is manufactured by changing the land of the QFP of the printed board having the land on which the QFP can be mounted to the land on which the BGA can be mounted.
To be installed.
【0003】[0003]
【発明が解決しようとする課題】以上から明らかなよう
に、従来の方法では、ある種類のパッケージを搭載して
いるプリント基板において、そのパッケージを、全く同
じ機能を有した、パッケージの形状のみが異なる別のパ
ッケージの搭載に置き換える場合、プリント基板もパッ
ケージの形状に合わせたランドを有する別のプリント基
板に変更しなければならないという問題があった。As is apparent from the above, according to the conventional method, in a printed circuit board on which a certain type of package is mounted, only the shape of the package having exactly the same function is obtained. When replacing with a different package, there is a problem that the printed circuit board must be changed to another printed circuit board having a land according to the shape of the package.
【0004】本発明は、プリント基板に搭載するパッケ
ージの形状が変更されても、新規に別のプリント基板を
製造せずに、同一のプリント基板で搭載ができるように
することを目的としている。[0004] It is an object of the present invention to enable mounting on the same printed circuit board without manufacturing a new printed circuit board even if the shape of a package mounted on the printed circuit board is changed.
【0005】[0005]
【課題を解決するための手段】上記目的を達成するため
に、本発明のプリント基板においては、パッケージサイ
ズの大きいQFP等のランドの内側に、パッケージサイ
ズの小さいBGAやCSP等のランドを、各ランドのセ
ンターが一致するように配置し、または、QFP等のラ
ンドと、BGAやCSP等のランドを2列に並べて配置
し、それぞれのパッケージで同じ機能を有する端子が接
続されるべきランド同士をパターン配線で接続したもの
であるため、プリント基板に搭載するパッケージの形状
が変わっても、同一のプリント基板に搭載できるように
したものである。In order to achieve the above object, in a printed circuit board of the present invention, a land such as a BGA or CSP having a small package size is provided inside a land such as a QFP having a large package size. Lands are arranged so that the centers of the lands coincide, or lands such as QFP and lands such as BGA and CSP are arranged in two rows, and lands to which terminals having the same function are to be connected in each package are connected. Since they are connected by pattern wiring, they can be mounted on the same printed circuit board even if the shape of the package mounted on the printed circuit board changes.
【0006】[0006]
【発明の実施の形態】本発明の実施例を図面を参照して
説明する。図1は、パッケージサイズの大きいQFPの
ランド1の内側に、QFPよりパッケージサイズの小さ
いBGAのランド2を、各ランドのセンターが一致する
ように配置した例である。また、図4はQFPのランド
とBGAのランドを2列に並べて配置した例である。図
1、図4ともに、両パッケージの同じ機能を有する端子
を接続するべきランド同士を、配線パターン3や、バイ
アホール4により接続されており、QFPとBGAのど
ちらを選択しても同一のプリント基板上に搭載できる構
造になっている。DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described with reference to the drawings. FIG. 1 shows an example in which a BGA land 2 having a smaller package size than a QFP is arranged inside a land 1 of a QFP having a larger package size so that the centers of the lands coincide with each other. FIG. 4 shows an example in which lands of QFP and lands of BGA are arranged in two rows. In both FIGS. 1 and 4, the lands to which the terminals having the same function of both packages are connected are connected by the wiring pattern 3 and the via hole 4, and the same print is made regardless of whether QFP or BGA is selected. It has a structure that can be mounted on a substrate.
【0007】図2及び図5は、それぞれ図1、図4のQ
FPランド1を選択し、QFP5をQFPのリード端子
6により、QFPランド1に接続した例である。FIGS. 2 and 5 show Q in FIGS. 1 and 4, respectively.
In this example, the FP land 1 is selected, and the QFP 5 is connected to the QFP land 1 by the lead terminal 6 of the QFP.
【0008】次に、図3及び図6は、それぞれ図1、図
4のBGAランド2を選択し、BGA7をBGAのボー
ル端子8により、BGAランド2に接続した例である。Next, FIGS. 3 and 6 show examples in which the BGA lands 2 of FIGS. 1 and 4 are selected and the BGA 7 is connected to the BGA lands 2 by the BGA ball terminals 8.
【0009】[0009]
【発明の効果】本発明は、以上説明したように構成され
ているので、以下に記載されるような効果を奏する。Since the present invention is configured as described above, it has the following effects.
【0010】第1に、同一のプリント基板上に、パッケ
ージ形状の違うランドがそれぞれ配置されており、それ
ぞれのパッケージで同じ機能を有する端子が接続される
べきランド同士をパターン配線で接続したものであるた
め、プリント基板に搭載するパッケージの形状が変わっ
ても、新規にプリント基板を製造する必要がなく、同一
の基板を共有することができる。First, lands having different package shapes are arranged on the same printed circuit board, and lands to be connected to terminals having the same function in each package are connected by pattern wiring. Therefore, even if the shape of the package mounted on the printed circuit board changes, it is not necessary to manufacture a new printed circuit board, and the same substrate can be shared.
【0011】それゆえ、第2に、プリント基板に半導体
パッケージを搭載する実装工場においては、半導体パッ
ケージ搭載の技術レベルに合わせて、搭載するパッケー
ジを選択して使い分けることができる。または、半導体
パッケージを供給する側の供給レベルに合わせて使い分
けることができる。Therefore, second, in a mounting factory for mounting a semiconductor package on a printed circuit board, the package to be mounted can be selectively used according to the technical level of mounting the semiconductor package. Alternatively, the semiconductor package can be selectively used in accordance with the supply level of the supply side.
【0012】第3に、図1のように、QFPランドの内
側にBGAランドを配置した場合においては、プリント
基板の実装密度を損なわず、更に、各ランドのセンター
を一致させた場合には、搭載機械の搭載プログラムにお
いて、その座標値を変更せずに共用できる。Third, as shown in FIG. 1, when the BGA lands are arranged inside the QFP lands, the mounting density of the printed circuit board is not impaired, and when the centers of the lands are matched, In the mounting program of the mounting machine, the coordinate values can be shared without changing.
【図1】QFPのランドの内側に、BGAのランドを、
各ランドのセンターが一致するように配置した場合を示
す図である。FIG. 1 shows a BGA land inside a QFP land.
It is a figure which shows the case where it arrange | positions so that the center of each land may correspond.
【図2】図1にQFPを搭載した場合を示す図である。FIG. 2 is a diagram showing a case where a QFP is mounted on FIG. 1;
【図3】図1にBGAを搭載した場合を示す図である。FIG. 3 is a diagram showing a case where a BGA is mounted in FIG. 1;
【図4】QFPのランドと、BGAのランドを2列に並
べて配置した場合を示す図である。FIG. 4 is a diagram showing a case where lands of QFP and lands of BGA are arranged in two rows.
【図5】図4にQFPを搭載した場合を示す図である。FIG. 5 is a diagram showing a case where a QFP is mounted in FIG. 4;
【図6】図4にBGAを搭載した場合を示す図である。FIG. 6 is a diagram showing a case where a BGA is mounted in FIG. 4;
1‥‥ QFPのランド 2‥‥ BGAのランド 3‥‥ 配線パターン 4‥‥ バイアホール 5‥‥ QFP 1 land of QFP 2 land of BGA 3 wiring pattern 4 via hole 5 QFP
Claims (3)
(以下QFPと略す)や、Ball Grid Arr
ay(以下BGAと略す)、 Chip Size P
ackage(以下CSPと略す)等の半導体パッケー
ジを搭載するプリント基板において、パッケージサイズ
の大きいQFP等のランドの内側に、パッケージサイズ
の小さいBGAやCSP等のランドを配置し、外側に配
置したQFP等のランドと、内側に配置したBGAやC
SP等のランドのそれぞれのパッケージで同じ機能を有
する端子が接続されるべきランド同士をパターン配線で
接続したことを特徴とするプリント基板。1. Quad Flat Package
(Hereinafter abbreviated as QFP), Ball Grid Arr
ay (hereinafter abbreviated as BGA), Chip Size P
In a printed circuit board on which a semiconductor package such as a package (hereinafter abbreviated as CSP) is mounted, a land such as a BGA or CSP having a small package size is arranged inside a land such as a QFP having a large package size, and a QFP etc. arranged outside the land. Land and BGA and C arranged inside
A printed circuit board wherein lands to be connected to terminals having the same function in respective packages of lands such as SP are connected by pattern wiring.
側に配置したBGAやCSP等のランドのセンターが一
致していることを特徴とする請求項1記載のプリント基
板。2. The printed circuit board according to claim 1, wherein a land such as a QFP disposed outside and a center of a land such as a BGA or CSP disposed inside coincide with each other.
ンドを2列に並べて配置し、それぞれのパッケージで同
じ機能を有する端子が接続されるべきランド同士をパタ
ーン配線で接続したことを特徴とするプリント基板。3. Lands such as QFP and lands such as BGA and CSP are arranged in two rows, and lands to be connected to terminals having the same function in each package are connected by pattern wiring. Printed circuit board.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9947797A JPH10290058A (en) | 1997-04-16 | 1997-04-16 | Printed-circuit board |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP9947797A JPH10290058A (en) | 1997-04-16 | 1997-04-16 | Printed-circuit board |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH10290058A true JPH10290058A (en) | 1998-10-27 |
Family
ID=14248400
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP9947797A Withdrawn JPH10290058A (en) | 1997-04-16 | 1997-04-16 | Printed-circuit board |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH10290058A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100416000B1 (en) * | 2001-07-11 | 2004-01-24 | 삼성전자주식회사 | Pcb mounting chip having plural pins |
US6853092B2 (en) | 2002-10-11 | 2005-02-08 | Seiko Epson Corporation | Circuit board, mounting structure for semiconductor device with bumps, and electro-optic device and electronic device |
US7268303B2 (en) | 2002-10-11 | 2007-09-11 | Seiko Epson Corporation | Circuit board, mounting structure of ball grid array, electro-optic device and electronic device |
-
1997
- 1997-04-16 JP JP9947797A patent/JPH10290058A/en not_active Withdrawn
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100416000B1 (en) * | 2001-07-11 | 2004-01-24 | 삼성전자주식회사 | Pcb mounting chip having plural pins |
US6853092B2 (en) | 2002-10-11 | 2005-02-08 | Seiko Epson Corporation | Circuit board, mounting structure for semiconductor device with bumps, and electro-optic device and electronic device |
CN1303677C (en) * | 2002-10-11 | 2007-03-07 | 精工爱普生株式会社 | Circuit substrate, mounting structure of semiconductor element with lug and electrio-optical device |
US7268303B2 (en) | 2002-10-11 | 2007-09-11 | Seiko Epson Corporation | Circuit board, mounting structure of ball grid array, electro-optic device and electronic device |
CN100407413C (en) * | 2002-10-11 | 2008-07-30 | 精工爱普生株式会社 | Circuit substrate, installing structure of solder ball network display and electro-light device |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A300 | Withdrawal of application because of no request for examination |
Free format text: JAPANESE INTERMEDIATE CODE: A300 Effective date: 20040706 |