JPS6334969A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To prevent the increase of a connection pattern by a method wherein the lower surface or the upper surface of a semiconductor storage element package is attached to the positions corresponding with each other on both surfaces of a substrate, and each of the corresponding connection pads of both element packages on the corresponding positions are connected through the intermediary of the through hole provided on the substrate. CONSTITUTION:Semiconductor storage element packages 2 are mounted on both sides of a substrate 1, the lower side B of the semiconductor storage element packages 2 on the upper side of the substrate 1 as shown in the diagram is soldered to the substrate 1, and the upper surface A of the semiconductor storage element package 2 on the lower side of the substrate is soldered to the substrate 1. In this case, the connection pads 3 of each semiconductor storage element package 2 are on the positions corresponding with each other in vertical direction when viewed from the upper surface. Each of the terminals of the same attribute of the semiconductor storage element packages 2 on the corresponding position are connected with each other through the intermediary of the connection through holes 4 vertically penetrating the substrate 1. Accordingly, it is unnecessary to provided a connection pattern on the surface of the substrate 1, and the number of patterns can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device in which a semiconductor memory element-package having connection pads provided on both upper and lower surfaces is attached to both sides of a substrate.

[Prior Art] In general, in semiconductor memory devices, the capacity of a single semiconductor memory element is increasing by a factor of 4, but in addition, main memory devices used in information processing devices, etc., which are made up of a plurality of semiconductor memory elements are increasing. In order to increase the capacity, the packaging density is being improved. Conventionally, this type of semiconductor memory element has been housed in a package called Dual InLine (hereinafter referred to as DIP) to form a semiconductor memory element package, and by arranging this semiconductor memory element package on a substrate, a semiconductor memory device can be manufactured. It consisted of In recent years, various package forms have been developed with the aim of improving packaging density. Among them, Leadles
s Chip Carrier (hereinafter referred to as LCC) is becoming dominant. Unlike DIP, L (Ic:) does not connect by inserting a terminal (Lead) into a through hole on the board, but instead connects an electrode pad to an LCC package that does not have the terminal and houses a semiconductor element. Furthermore, electrode pads are provided on the board on which this package is mounted, and the electrode pads on the LCC package and the board are connected by soldering.The tLcc Hara cage requires through holes on the board. Therefore, it becomes possible to mount the LCC package on both sides of the board.An example of this is shown in Fig. 3. In Fig. 3, 201 is the board.

202 and 203 are semiconductor memory element packages which are LCC packages, and 206 are terminals attached to the substrate 201. The semiconductor memory element package 202 is a substrate 201
The other semiconductor memory element package 203 is mounted on the surface opposite to the surface of the substrate 201 on which this semiconductor memory element package 202 is mounted. In addition, semiconductor memory element packages 202 and 203
Since the connection pads use only the terminals on one side of the element housing package, they are mounted so that they face each other when mounted on both sides of the board 201.

[Problems to be Solved] In the above conventional semiconductor memory device, the connection pads of the semiconductor memory element packages 202 and 203 use only the terminals on one side of the element housing package, so when mounted on both sides of the substrate 201, they do not touch each other. Since the semiconductor memory element packages 202 and 203 are mounted facing each other, the address terminals of the semiconductor memory element packages 202 and 203 are usually connected to each other. Therefore, a problem arises in that connection patterns must be provided on the substrate 201 to connect the connection pads, resulting in an increase in the number of patterns.

[Means for Solving Problems] The present invention has been made by focusing on the above-mentioned conventional problems, and provides a semiconductor memory in which the number of connection patterns does not increase even when a large number of semiconductor memory element packages are arranged on a large substrate. The aim is to provide the equipment.

To this end, the present invention provides a semiconductor memory device in which semiconductor memory element packages having connection pads provided on both upper and lower surfaces are attached to both sides of a substrate, in which the lower surface of one semiconductor memory element package is attached to one side of the substrate, and The top surface of the other semiconductor memory element package is attached to the other surface of the substrate at a position corresponding to that of the semiconductor memory element package, and the corresponding connection pads of both semiconductor memory element packages at the corresponding positions are connected to each other via a through hole provided in the substrate. The present invention provides a semiconductor memory device characterized by the following features.

[Example] Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view showing one embodiment of the present invention. 2 in the diagram
2 is a semiconductor memory element package, and 2 is a substrate on which the semiconductor memory element package 2 is mounted. Figure 2 (a) (
llI) shows the semiconductor memory element package 2, in which connection pads 3 are provided over both upper and lower surfaces A and H. Each connection pad 3 is assigned as shown in FIG. 2(α). 1. Normally, when the semiconductor memory element packages 2 are used in an array, the address bits are commonly connected.

Therefore, the AO terminals of the semiconductor memory element package 2 shown in Figure @i are commonly connected to each other. The semiconductor memory element packages 2 are mounted on both sides of the substrate l, and the semiconductor memory element package 2 on the upper side in the figure has its lower surface B soldered to the substrate l, and the semiconductor memory element package 2 on the lower side has its upper surface A soldered to the substrate l. It is designed to be soldered to the board l. In this case, the connection pads 3 of each semiconductor memory element package 2 are located at vertically corresponding positions to each other when viewed from the top. Terminals of the semiconductor memory element packages 2 at corresponding positions having the same attributes are connected to each other through connection through holes 4 that vertically penetrate the substrate 1. Therefore, it is not necessary to provide connection patterns on the surface of the substrate 1, and reducing the number of patterns is advantageous.

[Effects of the Invention] As described above, the present invention provides a semiconductor memory device in which semiconductor memory element packages having connection pads provided on both upper and lower surfaces are attached to both sides of a substrate, in which one semiconductor memory element package is attached to one side of the substrate. At the same time, the upper surface of the other semiconductor memory element package is attached to the other surface of the substrate at a position corresponding to the semiconductor memory element package, and the corresponding connection pads of the two-handed conductive memory element package at the corresponding positions are provided on the substrate. Because the semiconductor memory device is characterized in that it is connected through a through-hole,
When a large number of semiconductor memory element puff cages are arranged on a large substrate, it is possible to prevent the interconnection patterns between the chips from increasing, and the packaging density can be greatly improved.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing a semiconductor memory device according to an embodiment of the present invention, FIG. 2(4)(a) is a perspective view and a plan view of a package in which a semiconductor memory element is mounted, and FIG. 4) (El) is a front view and a sectional view showing a conventional semiconductor memory device. 1: Substrate 2 2 Semiconductor storage element package 3: Connection pad 4 Varnish through hole

Claims (1)

[Claims] In a semiconductor memory device in which a semiconductor memory element package having connection pads provided on both upper and lower surfaces is attached to both sides of a substrate, the lower surface of one semiconductor memory element package is attached to one side of the substrate, and the lower surface of one semiconductor memory element package is attached at a position corresponding to the semiconductor memory element package. A semiconductor memory device characterized in that the upper surface of the other semiconductor memory element package is attached to the other surface of the substrate, and corresponding connection pads of both semiconductor memory element packages at corresponding positions are connected to each other via a through hole provided in the substrate. .