JPH01304795A - Method for wiring printed board - Google Patents

Method for wiring printed board

Info

Publication number
JPH01304795A
JPH01304795A JP13444188A JP13444188A JPH01304795A JP H01304795 A JPH01304795 A JP H01304795A JP 13444188 A JP13444188 A JP 13444188A JP 13444188 A JP13444188 A JP 13444188A JP H01304795 A JPH01304795 A JP H01304795A
Authority
JP
Japan
Prior art keywords
footprint
board
substrate
conductive pattern
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13444188A
Other languages
Japanese (ja)
Inventor
Manabu Suzuki
学 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP13444188A priority Critical patent/JPH01304795A/en
Publication of JPH01304795A publication Critical patent/JPH01304795A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3415Surface mounted components on both sides of the substrate or combined with lead-in-hole components

Abstract

PURPOSE:To require a shorter wiring of the surface and back of a substrate by a method wherein a throughfoot print is formed so as to extend from the surface to the back of the substrate or to reach an intermediate conductive pattern at a foot print for connecting the surface and the back of the substrate and then leads of a surface mounted part of a conductive pattern is connected to the throughfoot print on the surface of the substrate, on the back of the substrate or at the intermediate conductive pattern. CONSTITUTION:At a footprint A for connecting the surface and the back of a substrate, a throughfoot print 10 is formed by filling the solder 10b inside a via 10a which extends from the surface 1a to the back 1b of the substrate 1. On the end of the surface 1a of this throughfoot print 10, a part lead 4 is soldered in the same way as other foot print 2. And on the end of the back 1b, a part lead 4' or a conductive pattern 5' is soldered. At a portion B having an intermediate conductive pattern 11, a throughfoot print 10 is formed from the surface 1a to the intermediate conductive pattern 11 and from the back 1b to the intermediate conductive pattern 11 and the part leads 4 and 4' and other parts are soldered on the surface 1a and the back 1b. By this method, a shorter wiring is required than before and such a high speed printed board is obtained which has little noise.

Description

【発明の詳細な説明】 〔概要〕 フラットパックタイプパッケージ等の表面実装される部
品が搭載されるプリント板の配線方法で、詳しくは、基
板の表裏面相互を接続する配線の短縮化に関し、 表面実装されるプリント板において表裏配線を短縮化す
ることを目的とし、 基板上にピン間隔と同様にフットプリントを設け、表面
実装部品の多数のリードを各フットプリントに平面付け
して実装するプリント板において、表裏接続用フットプ
リント部に基板の表裏面又は中間導体パターンに及ぶス
ルーフットプリントを形成し、基板の表面、裏面又は中
間導体パターンでスルーフットプリントに部品リード又
は導体パターンを接続する。
[Detailed Description of the Invention] [Summary] A wiring method for a printed circuit board on which surface-mounted components such as a flat pack type package are mounted. A printed board that is designed to shorten the wiring on the front and back sides of the printed circuit board to be mounted. Footprints are provided on the board in the same manner as the pin spacing, and a large number of leads of surface mount components are mounted by flatly attaching them to each footprint. In this step, a through footprint extending to the front and back surfaces of the board or the intermediate conductor pattern is formed in the front and back connection footprint portion, and component leads or conductor patterns are connected to the through footprint on the front and back surfaces of the board or the intermediate conductor pattern.

〔産業上の利用分野〕[Industrial application field]

本発明は、フラットバックタイプパッケージ等の表面実
装される部品が搭載されるプリント板の配線方法で、詳
しくは、基板の表裏面相互を接続する配線の短縮化に関
する。
The present invention relates to a wiring method for a printed board on which surface-mounted components such as a flat back type package are mounted, and more particularly, to shortening of wiring connecting the front and back surfaces of the board.

近年、プリント板の実装密度を増大するため、ピン間隔
を狭くして2方向又は4方向に端子リードを出したフラ
ットパックタイプパッケージ等の部品が多く用いられて
いる。この表面実装部品では同ピン数のDTPに比べて
実装面積が半分以下になり、両面実装により実装密度を
倍増することが可能であり、端子数の多い部品に適し、
薄形化が可能である等の利点を有する。しかし、部品リ
ードとの接続部はピン間隔が狭いためDIPのようなス
ルーホールを形成し、このスルーホールを基板の表裏面
の接続に用いるような配線ができない。
In recent years, in order to increase the packaging density of printed circuit boards, components such as flat pack type packages with narrow pin spacing and terminal leads extending in two or four directions have been increasingly used. With this surface mount component, the mounting area is less than half that of a DTP with the same number of pins, and the mounting density can be doubled by double-sided mounting, making it suitable for components with a large number of terminals.
It has advantages such as being able to be made thinner. However, since the pin spacing between the pins is narrow at the connection part with the component lead, a through hole such as a DIP is formed, and wiring such as using this through hole for connection between the front and back surfaces of the board is not possible.

〔従来の技術〕[Conventional technology]

そこで、従来上記表面実装されるプリント板の配線方法
は、第2図(a)、(b)のように行われている。即ち
、基板1の表面にピン間隔と同じ狭い間隔でフットプリ
ント(ランド)2が設けられ、このフットプリント2に
表面実装部品3の各リード4が直接平面付けして実装さ
れる。そして、基板1上に各フットプリント2と接続す
る導体パターン5が多数引回されている。ここで、フッ
トプリント2は単に部品リード4との平面付けにしか用
いられていないため、基板1の表面1aと裏面1bの接
続の場合は、各別にスルーホール6が設けられて導体パ
ターン5から分岐するパターン7がスルーホール6を介
して裏面側に配線されている。
Therefore, the conventional wiring method for surface-mounted printed circuit boards is as shown in FIGS. 2(a) and 2(b). That is, footprints (lands) 2 are provided on the surface of the substrate 1 at narrow intervals that are the same as the pin intervals, and each lead 4 of the surface mount component 3 is directly flattened and mounted on the footprints 2. A large number of conductor patterns 5 are routed on the substrate 1 to connect to each footprint 2. Here, since the footprint 2 is used only for flattening the component lead 4, when connecting the front surface 1a and the back surface 1b of the board 1, through holes 6 are provided separately for each of the conductor patterns 5. A branching pattern 7 is wired through the through hole 6 on the back side.

(発明が解決しようとする課題〕 ところで、上記従来例のものにあっては、基板1の表裏
面1a、1bの配線が専用のパターン7とスルーホール
6により行われるので、そのための配線領域が必要にな
り、図示のような両面実装で表裏配線数が多い場合は基
板の多くの領域を占有し、配線パターンの複雑化を招く
。また、表裏配線の回路が長くなることで、ノイズ低減
、高速化等に対し不利になる。
(Problems to be Solved by the Invention) By the way, in the conventional example described above, since the wiring on the front and back surfaces 1a and 1b of the substrate 1 is performed using the dedicated pattern 7 and the through hole 6, the wiring area for this is small. When the number of front and back wiring is large in double-sided mounting as shown in the figure, it occupies a large area of the board, leading to a complicated wiring pattern.In addition, the circuit of the front and back wiring becomes long, which reduces noise. This will be disadvantageous when it comes to speeding up, etc.

本発明は、かかる問題点に鑑みなされたもので、その目
的とするところは、表面実装されるプリント仮において
表裏配線を短縮化することができるプリント板の配線方
法を提供することにある。
The present invention has been made in view of these problems, and an object of the present invention is to provide a printed board wiring method that can shorten the front and back wiring in a surface-mounted printed circuit board.

〔課題を解決するための手段〕[Means to solve the problem]

上記目的を達成するため、本発明の配線方法は、 部品リードが平面付けされる基板のフットプリントを表
裏配線にも活用するものである。そこで、表裏接続用フ
ットプリント部に基板の表裏面又は中間導体パターンに
及ぶスルーフットプリントを形成し、基板の表面、裏面
又は中間導体パターンでスルーフットプリントに表面実
装部品のリード、又は、導体パターンを接続するもので
ある。
In order to achieve the above object, the wiring method of the present invention utilizes the footprint of the board on which component leads are flattened for front and back wiring. Therefore, a through footprint that extends to the front and back surfaces of the board or the intermediate conductor pattern is formed in the front and back connection footprint portion, and leads of surface mount components or conductor patterns are formed in the through footprint on the front and back surfaces of the board or the intermediate conductor pattern. It connects.

〔作用〕[Effect]

上記配線方法により、基板の表裏面では通常。 Due to the above wiring method, it is normal for both the front and back sides of the board.

のフットプリントとスルーフットプリントに部品リード
が平面付けされて表面実装される。また、スルーフット
プリントのみ又はそれと中間導体パターンを介して基板
の表裏面に直接配線されることになる。
Component leads are flattened to the footprint and through footprint for surface mounting. Further, wiring is directly performed on the front and back surfaces of the board via only the through footprint or through the intermediate conductor pattern.

〔実施例] 以下、本発明の実施例を図面に基いて説明する。〔Example] Embodiments of the present invention will be described below with reference to the drawings.

第1図において、1は基板、2は基板1上に多数設けら
れるフットプリント、3は表面実装部品、4はリード、
5は導体パターンであり、この部品リード4がフットプ
リント2に直接半田付けして実装されるのであり、図示
の場合は基板1の表面1aと裏面1bに両面実装されて
いる。ここで、裏面1bの表面1aにおける各部と該当
する部分は同一符号にダッシュを付しである。
In FIG. 1, 1 is a board, 2 is a large number of footprints provided on the board 1, 3 is a surface mount component, 4 is a lead,
5 is a conductor pattern, and this component lead 4 is directly soldered to the footprint 2 and mounted, and in the case shown, it is mounted on both sides of the front surface 1a and back surface 1b of the board 1. Here, each part and the corresponding part on the front surface 1a of the back surface 1b are given the same reference numerals with a dash.

そこで、表裏接続用フンドブリント部Aでは基板1に表
裏面1a、1bに及んで貫通したビア10aが、レーザ
光等による孔明けで狭い範囲内に明けられ、このビア1
0a内に半田10bを詰めてスルーフットプリント10
が形成される。そして、このスルーフットプリント10
の表面1a側端部に部品リード4が他のフットプリント
2と同様に半田付けされ、裏面1b側端部に図示のよう
に部品リード4′又は導体パターン5′が半田付けされ
る。
Therefore, in the fundprint part A for front and back connections, a via 10a penetrating the front and back surfaces 1a and 1b of the substrate 1 is opened within a narrow range by drilling with a laser beam or the like.
Fill solder 10b inside 0a to create through footprint 10
is formed. And this through footprint 10
A component lead 4 is soldered to the end of the front surface 1a in the same manner as the other footprints 2, and a component lead 4' or a conductor pattern 5' is soldered to the end of the back surface 1b as shown.

一方、中間導体パターン11を有する部分Bでは、基板
1において表面1aと裏面1bから中間導体パターン1
1に及んで上述と同様のスルーフットプリント10が形
成される。そして、このスルーフットプリント10に表
裏面1a、1bで部品リード4.4′等が半田付けされ
る。
On the other hand, in the portion B having the intermediate conductor pattern 11, the intermediate conductor pattern 1
1, a through footprint 10 similar to that described above is formed. Component leads 4, 4', etc. are soldered to this through footprint 10 on the front and back surfaces 1a and 1b.

かかる構成により、基板1の表面1aでは表面実装部品
3のリード4がフットプリント2とスルーフットプリン
ト10の両者に同一に平面付けされて表面実装され、裏
面1bでも同様になる。
With this configuration, on the front surface 1a of the board 1, the leads 4 of the surface mount component 3 are surface-mounted on both the footprint 2 and the through footprint 10 in the same plane, and the same is true on the back surface 1b.

また、表面1aの部品リード4からスルーフンドブリン
ト10又はそれと中間導体パターン11を介して、裏面
1bの部品リード4′等に短い距離で配線されて電気接
続する。
Furthermore, electrical connection is made by wiring over a short distance from the component lead 4 on the front surface 1a to the component lead 4' on the back surface 1b via the through-end blind 10 or an intermediate conductor pattern 11 therebetween.

尚、本発明は片面実装の場合にも適用し得るのは勿論で
ある。
It goes without saying that the present invention can also be applied to single-sided mounting.

〔発明の効果〕〔Effect of the invention〕

以上述べてきたように、本発明によれば、表面実装され
るプリント板において、表裏接続配線がフットプリント
部のスルーフットプリントで行われるので、このための
パターンの引回しが著しく少なくなって、実装密度を向
上し得る。
As described above, according to the present invention, in a surface-mounted printed circuit board, the front and back connection wiring is performed in the through-footprint of the footprint section, so the wiring of patterns for this purpose is significantly reduced. Packaging density can be improved.

フットプリント部のスルーフットプリントにより配線長
さが短縮化して、ノイズ対策、高速化に有利である。
The through footprint of the footprint section shortens the wiring length, which is advantageous for noise countermeasures and increased speed.

中間層がある場合はその導体パターンをスルーフットプ
リントで利用できて、配線の自由度が増す。
If there is an intermediate layer, its conductor pattern can be used in a through footprint, increasing the degree of freedom in wiring.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明のプリント板の配線方法の実施例を示す
断面図、 第2図(a)は従来例の断面図、(b)は同平面図であ
る。 図において、 1は基板、 1aは表面、 1bは裏面、 2はフットプリント、 3は表面実装部品、 4.4′ はリード、 5′は導体パターン、 10はスルーフットプリント、 11は中間導体パターンを示す。
FIG. 1 is a sectional view showing an embodiment of the printed board wiring method of the present invention, FIG. 2(a) is a sectional view of a conventional example, and FIG. 2(b) is a plan view thereof. In the figure, 1 is the board, 1a is the front surface, 1b is the back surface, 2 is the footprint, 3 is the surface mount component, 4.4' is the lead, 5' is the conductor pattern, 10 is the through footprint, and 11 is the intermediate conductor pattern. shows.

Claims (1)

【特許請求の範囲】 基板(1)上にピン間隔と同様にフットプリント(2)
を設け、表面実装部品(3)の多数のリード(4)を各
フットプリント(2)に平面付けして実装するプリント
板において、 表裏接続用フットプリント部に基板(1)の表裏面(1
a、1b)又は中間導体パターン(11)に及ぶスルー
フットプリント(10)を形成し、 基板(1)の表面(1a)、裏面(1b)又は中間導体
パターン(11)でスルーフットプリント(10)に部
品リード(4、4′)又は導体パターン(5′)を接続
するプリント板の配線方法。
[Claims] A footprint (2) on the board (1) as well as a pin spacing.
In a printed board on which a large number of leads (4) of surface mount components (3) are mounted flatly on each footprint (2), the front and back surfaces (1) of the board (1) are mounted on the front and back connection footprints.
a, 1b) or the intermediate conductor pattern (11); ) A printed board wiring method that connects component leads (4, 4') or conductor patterns (5') to
JP13444188A 1988-06-02 1988-06-02 Method for wiring printed board Pending JPH01304795A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13444188A JPH01304795A (en) 1988-06-02 1988-06-02 Method for wiring printed board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13444188A JPH01304795A (en) 1988-06-02 1988-06-02 Method for wiring printed board

Publications (1)

Publication Number Publication Date
JPH01304795A true JPH01304795A (en) 1989-12-08

Family

ID=15128429

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13444188A Pending JPH01304795A (en) 1988-06-02 1988-06-02 Method for wiring printed board

Country Status (1)

Country Link
JP (1) JPH01304795A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06310827A (en) * 1993-04-26 1994-11-04 Nec Corp Surface mounting component arrangement structure
US5374848A (en) * 1991-04-23 1994-12-20 Mitsubishi Denki Kabushiki Kaisha Thermal stress resistant semiconductor device mounting arrangement
USRE36077E (en) * 1991-10-15 1999-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing inversion type IC's and IC module using same
JP2015115565A (en) * 2013-12-16 2015-06-22 住友電装株式会社 Printed board for mounting microcomputer and controller using the same

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5374848A (en) * 1991-04-23 1994-12-20 Mitsubishi Denki Kabushiki Kaisha Thermal stress resistant semiconductor device mounting arrangement
USRE36077E (en) * 1991-10-15 1999-02-02 Mitsubishi Denki Kabushiki Kaisha Method of manufacturing inversion type IC's and IC module using same
JPH06310827A (en) * 1993-04-26 1994-11-04 Nec Corp Surface mounting component arrangement structure
JP2015115565A (en) * 2013-12-16 2015-06-22 住友電装株式会社 Printed board for mounting microcomputer and controller using the same

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