JPH10284632A - Circuit substrate and manufacture therefor - Google Patents

Circuit substrate and manufacture therefor

Info

Publication number
JPH10284632A
JPH10284632A JP8968397A JP8968397A JPH10284632A JP H10284632 A JPH10284632 A JP H10284632A JP 8968397 A JP8968397 A JP 8968397A JP 8968397 A JP8968397 A JP 8968397A JP H10284632 A JPH10284632 A JP H10284632A
Authority
JP
Japan
Prior art keywords
wiring
substrate
circuit board
insulating
wirings
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8968397A
Other languages
Japanese (ja)
Other versions
JP3754171B2 (en
Inventor
Yasuo Yamagishi
康男 山岸
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP8968397A priority Critical patent/JP3754171B2/en
Publication of JPH10284632A publication Critical patent/JPH10284632A/en
Application granted granted Critical
Publication of JP3754171B2 publication Critical patent/JP3754171B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/142Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/46Manufacturing multilayer circuits
    • H05K3/4611Manufacturing multilayer circuits by laminating two or more circuit boards

Landscapes

  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To simplify the mounting operation of a circuit part, even when the substrate material and the circuit part having ordinary heat-resistant property are used, to mount a chip and an inserting type part on the same substrate, and to accomplish high density in the manufacture of the circuit substrate on which a circuit part is mounted and it is connected by a multilayered wiring. SOLUTION: A plurality of wirings are laminated between wirings pinching an interlayer insulating film on a part of a circuit substrate in the circuit substrate, a multilayered wiring part 111, on which the upper and the lower wirings are connected through the inner via hole of the interlayer insulating film formed on the lower wiring is provided, and the part which is the mounted surface of the circuit substrate 112, including the surface of the multilayered wiring part 111, is almost planarized.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、回路基板及びその
製造方法に関し、より詳しくは、回路部品を搭載し、該
回路部品を多層配線により相互に接続する回路基板及び
その製造方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit board and a method of manufacturing the same, and more particularly, to a circuit board on which circuit parts are mounted and the circuit parts are connected to each other by multilayer wiring, and a method of manufacturing the same.

【0002】[0002]

【従来の技術】近年、電子機器を小型化、高速化するに
は、半導体集積回路装置の集積度の向上とともに、実装
基板の高密度化が要望されている。このため、回路基板
内の配線が微細化されるとともに、単層プリント基板か
ら、層状に複数の配線が形成された多層プリント基板が
用いられるようになっている。現在では数十層の多層配
線が内蔵されたプリント基板が実用化されている。そし
て、異なる層の配線同士はプリント基板を貫通するスル
ーホールを通して接続される。殆どの電子部品はこのよ
うなプリント基板上に実装されている。
2. Description of the Related Art In recent years, in order to reduce the size and speed of electronic devices, there is a demand for higher integration of semiconductor integrated circuit devices and higher density of mounting substrates. For this reason, the wiring in the circuit board has been miniaturized, and a multilayer printed board having a plurality of wirings formed in layers from a single-layer printed board has been used. At present, a printed circuit board in which several tens of layers of multilayer wiring are built has been put to practical use. Then, wirings of different layers are connected through through holes penetrating the printed circuit board. Most electronic components are mounted on such a printed circuit board.

【0003】上記プリント基板は、以下のようにして作
成される。即ち、図7(a)に示すように、配線2a〜
2dや電極2e,2fを形成した複数のエポキシ樹脂板
1a〜1eを半硬化状態のエポキシ樹脂シート3a〜3
dを介して重ねる。続いて、図7(b)に示すように、
ホットプレスして一体化し、基板101を作成する。そ
の後、層間の配線2a〜2dを接続する箇所に基板10
1を貫くスルーホール4a〜4dを形成する。
[0003] The printed circuit board is prepared as follows. That is, as shown in FIG.
A plurality of epoxy resin plates 1a-1e on which 2d and electrodes 2e, 2f are formed are semi-cured epoxy resin sheets 3a-3
Layer through d. Subsequently, as shown in FIG.
The substrate 101 is formed by hot pressing and integrating. After that, the substrate 10 is connected to a place where the interlayer wirings 2a to 2d are connected.
1 through holes 4a to 4d are formed.

【0004】次いで、図7(c)に示すように、スルー
ホール4a〜4dの内壁面に銅膜5a〜5dを形成して
所望の層間の配線2a〜2dの接続を行う。しかし、こ
のようなプリント基板101の場合、1つのスルーホー
ル4aで1組の配線3b,3dの接続しか行えないこ
と、全ての層でスルーホール4a〜4dを避けて配線す
る必要があることなどの理由で、高密度化には限界があ
る。一方で、半導体集積回路装置の多端子化、狭ピッチ
化に伴い、上記のような形態のプリント基板では対応困
難な高密度配線に対する要望が増しつつある。
Then, as shown in FIG. 7C, copper films 5a to 5d are formed on the inner wall surfaces of the through holes 4a to 4d to connect the desired wirings 2a to 2d between the layers. However, in the case of such a printed circuit board 101, only one set of wirings 3b and 3d can be connected with one through hole 4a, and it is necessary to perform wiring avoiding the through holes 4a to 4d in all layers. For this reason, there is a limit to high density. On the other hand, with the increase in the number of terminals and the narrower pitch of the semiconductor integrated circuit device, there is an increasing demand for high-density wiring which is difficult to cope with the printed circuit board of the above-described embodiment.

【0005】より一層の高密度化を実現するためには、
インナビアホール(層間接続孔)による層間の配線接続
が必要である。そのようなものとして、図8に示すよう
に、多端子、狭ピッチのLSIチップを複数搭載するマ
ルチチップモジュール(MCM)用に、薄膜多層法やビ
ルトアップ法によって層状に複数の配線12a〜12d
を高密度に形成し、層間絶縁膜13a〜13cに形成さ
れたインナビアホール14a〜14cにより異なる層の
配線12a〜12dを接続した多層回路基板(MCM基
板)102が開発されている。
[0005] In order to realize higher density,
Wiring connection between layers by an inner via hole (interlayer connection hole) is required. As shown in FIG. 8, for a multi-chip module (MCM) in which a plurality of multi-terminal, narrow-pitch LSI chips are mounted, a plurality of wirings 12a to 12d are layered by a thin-film multilayer method or a built-up method.
Is formed at a high density, and wirings 12a to 12d of different layers are connected by inner via holes 14a to 14c formed in interlayer insulating films 13a to 13c.

【0006】このような多層回路基板102は、下地基
板の材料によって以下のような種類に分類されている。
即ち、セラミック基板を用いたMCM−D、Si基板を
用いたMCM−C、樹脂基板を用いたMCM−L等であ
る(回路実装学会誌vol.11 No.5 1996, pp.311-315を参
照)。上記多層配線を内蔵するプリント基板(マザーボ
ード)101に、多端子、狭ピッチのLSIチップ、例
えば、ボールグリッドアレイ(BGA)タイプのチップ
サイズパッケージ(CSP)やエリアバンプを有するベ
アチップを実装する場合、図9に示すように、一度多層
回路基板上にハンダ付けによりLSIチップを実装して
MCMユニット103とした後、MCMユニット103
をプリント基板101上にハンダ付けにより実装すると
いう2段階実装方式が採用されている。この場合、MC
Mユニット103の基板11には基板11を貫通する基
板間接続孔が形成され、この基板間接続孔を通してMC
Mユニット103内の配線とプリント基板101内の配
線とが接続されている。なお、図9において、符号10
4は挿入型部品であり、105はチップ抵抗又はチップ
コンデンサである。
[0006] Such multilayer circuit boards 102 are classified into the following types according to the material of the underlying substrate.
That is, MCM-D using a ceramic substrate, MCM-C using a Si substrate, MCM-L using a resin substrate, and the like (Journal of the Circuit Packaging Society, vol.11 No.5 1996, pp.311-315). reference). When mounting a multi-terminal, narrow-pitch LSI chip, for example, a ball grid array (BGA) type chip size package (CSP) or a bare chip having area bumps on a printed circuit board (mother board) 101 containing the above-described multilayer wiring, As shown in FIG. 9, after once mounting an LSI chip on a multilayer circuit board by soldering to form an MCM unit 103,
Is mounted on the printed circuit board 101 by soldering. In this case, MC
A board-to-board connection hole penetrating the board 11 is formed in the board 11 of the M unit 103, and the MC connection hole is formed through the board-to-board connection hole.
The wiring in the M unit 103 and the wiring in the printed circuit board 101 are connected. Note that in FIG.
Reference numeral 4 denotes an insertion type component, and reference numeral 105 denotes a chip resistor or chip capacitor.

【0007】[0007]

【発明が解決しようとする課題】しかし、回路基板全体
をこのようなインナビアホール14a〜14cを有する
多層回路基板102とするのは著しく高価となる。この
ため、高密度配線を有する半導体チップを一度MCMと
してまとめてから比較的密度の低い配線を有する部品と
ともに通常のガラスエポキシ基板に実装している。
However, it is extremely expensive to make the entire circuit board a multilayer circuit board 102 having such inner via holes 14a to 14c. For this reason, a semiconductor chip having high-density wiring is once assembled as an MCM, and then mounted on a normal glass epoxy board together with components having relatively low-density wiring.

【0008】このような方式は工程数が増えるという問
題があり、さらに、MCMユニット103と他の部品
(チップ抵抗やQFPなど)とをプリント基板101に
搭載する際、先にハンダ付けしたMCMユニット103
側のハンダ接合部が外れないように対処しなければなら
ない。このため、MCMユニット103側のハンダが溶
融しても、部品が外れないよう接着剤等で補強・固定す
るか、或いはMCMユニット103側のハンダ付けにP
b−5SnやPb−10Snといった高融点ハンダを使
用する必要がある。前者の場合、工程が煩雑になるし、
後者の場合は、基板材料や回路部品に対して高い耐熱性
が要求されるため、材料コストが高くなるという問題が
ある。
[0008] Such a method has a problem that the number of steps is increased. Further, when mounting the MCM unit 103 and other components (such as a chip resistor and a QFP) on the printed circuit board 101, the MCM unit soldered first is used. 103
Care must be taken to keep the side solder joints from coming off. For this reason, even if the solder on the MCM unit 103 side melts, it is reinforced and fixed with an adhesive or the like so that the parts do not come off,
It is necessary to use a high melting point solder such as b-5Sn or Pb-10Sn. In the former case, the process becomes complicated,
In the latter case, high heat resistance is required for the substrate material and circuit components, and thus there is a problem that the material cost is increased.

【0009】更に、表面実装部品の割合が増加しつつあ
るとはいえ、現状ではDIP(DualInline Package )
等の挿入型部品も使用されており、半導体チップと挿入
型部品とを同一基板に搭載する必要もある。しかし、イ
ンナビアホール14a〜14cを有する多層回路基板1
02はスルーホールを有しないので、挿入型部品を搭載
することは困難である。
Further, although the ratio of surface mount components is increasing, at present, DIP (Dual Inline Package)
And the like, and it is necessary to mount the semiconductor chip and the insertable component on the same substrate. However, the multilayer circuit board 1 having the inner via holes 14a to 14c
Since No. 02 has no through hole, it is difficult to mount an insertion type component.

【0010】本発明は、上記の従来例の問題点に鑑みて
創作されたものであり、通常の耐熱性を有する基板材料
や回路部品を用いたときでも回路部品の搭載作業が簡単
で、チップと挿入型部品とを同一基板に搭載することが
でき、かつ高密度化を図ることができる回路基板及びそ
の製造方法を提供するものである。
SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems of the prior art, and is simple in mounting circuit components even when a normal heat-resistant substrate material or circuit components are used. The present invention provides a circuit board and a method for manufacturing the same, which can mount the same and the insertion-type component on the same board and can increase the density.

【0011】[0011]

【課題を解決するための手段】上記課題は、第1の発明
である、複数の配線が該配線間に絶縁板を挟んで積層さ
れ、上下の前記配線同士が全ての前記絶縁板を貫通する
貫通孔を通して接続されている回路基板であって、前記
回路基板の一部に、複数の配線が該配線間に層間絶縁膜
を挟んで積層され、上下の前記配線同士が該下方の配線
上に形成された層間絶縁膜のインナビアホールを通して
接続されている多層配線部分が設けられ、該多層配線部
分の表面を含む前記回路基板の部品搭載面がほぼ平坦に
なっていることを特徴とする回路基板によって解決さ
れ、第2の発明である、前記多層配線部分は、前記回路
基板の凹部又は切欠部に形成されていることを特徴とす
る第1の発明に記載の回路基板によって解決され、第3
の発明である、前記多層配線部分と、該多層配線部分の
下方の前記回路基板とを貫通する貫通孔を通して、前記
多層配線部分内の配線と前記回路基板内の配線とが接続
されていることを特徴とする第2の発明に記載の回路基
板によって解決され、第4の発明である、前記インナビ
アホールを有する多層配線部分内の配線と前記多層配線
部分の下方の回路基板内の配線とは、前記多層配線部分
の接続孔を通して接続されていることを特徴とする第2
の発明に記載の回路基板によって解決され、第5の発明
である、絶縁性基板上に配線と層間絶縁膜とを交互に積
層し、かつインナビアホールを通して前記層間絶縁膜の
上下の配線を接続してなる部分基板を準備する工程と、
複数枚の重ね合わせにより凹部又は切欠部が形成される
ような、配線が形成された複数の絶縁板を準備する工程
と、前記複数の絶縁板を重ねるとともに、前記凹部又は
前記切欠部に前記部分基板を置く工程と、前記複数の絶
縁板と前記部分基板を固着させる工程と、前記全ての絶
縁板を貫く貫通孔を形成し、該貫通孔を通して上下の前
記絶縁板の配線同士を接続する工程と、前記部分基板と
該部分基板の下にある全ての前記絶縁板とを貫通する貫
通孔を形成し、該貫通孔を通して前記部分基板内の配線
と前記絶縁板の配線とを接続する工程とを有することを
特徴とする回路基板の製造方法によって解決され、第6
の発明である、絶縁性基板上に配線と層間絶縁膜とを交
互に積層し、かつ該配線のいずれかと繋がる接続孔を前
記絶縁性基板に形成してなる部分基板を準備する工程
と、複数枚の重ね合わせにより凹部又は切欠部が形成さ
れるような、配線が形成された複数の絶縁板を準備する
工程と、前記複数の絶縁板を重ねるとともに、前記凹部
又は前記切欠部に前記部分基板を置く工程と、前記複数
の絶縁板と前記部分基板を固着させるとともに、前記部
分基板の絶縁性基板の接続孔を通して前記部分基板内の
配線と前記絶縁板の配線とを接続する工程と、前記全て
の絶縁板を貫く貫通孔を形成し、該貫通孔を通して上下
の前記絶縁板の配線同士を接続する工程とを有すること
を特徴とする回路基板の製造方法によって解決され、第
7の発明である、前記部分基板の絶縁性基板の下面に
は、前記絶縁性基板の接続孔を通して前記絶縁性基板上
の配線と接続する導電膜と、該導電膜上に開口部を有す
る接着用絶縁膜と、前記接着用絶縁膜の開口部内に埋め
込まれた導電性接着剤又は低融点合金材料とが形成され
ていることを特徴とする第6の発明に記載の回路基板の
製造方法によって解決される。
According to the first aspect of the present invention, a plurality of wirings are stacked with an insulating plate interposed between the wirings, and the upper and lower wirings penetrate all the insulating plates. A circuit board connected through a through hole, wherein a plurality of wirings are laminated on a part of the circuit board with an interlayer insulating film interposed between the wirings, and the upper and lower wirings are formed on the lower wirings. A circuit board provided with a multilayer wiring portion connected through an inner via hole of the formed interlayer insulating film, and a component mounting surface of the circuit board including a surface of the multilayer wiring portion is substantially flat; The second invention is solved by the circuit board according to the first invention, wherein the multilayer wiring portion is formed in a concave portion or a cutout of the circuit board.
The wiring in the multilayer wiring part and the wiring in the circuit board are connected through a through hole penetrating the multilayer wiring part and the circuit board below the multilayer wiring part. According to a fourth aspect of the present invention, there is provided a circuit board according to a second aspect, wherein the wiring in the multilayer wiring part having the inner via hole and the wiring in the circuit board below the multilayer wiring part are: Wherein the connection is made through a connection hole of the multilayer wiring portion.
A wiring board and an interlayer insulating film are alternately laminated on an insulating substrate, and the wirings above and below the interlayer insulating film are connected through an inner via hole. Preparing a partial substrate consisting of
A step of preparing a plurality of insulating plates on which wiring is formed, such that a concave portion or a cutout portion is formed by superimposing a plurality of sheets, and stacking the plurality of insulating plates, and forming the portion in the concave portion or the cutout portion. A step of placing a substrate, a step of fixing the plurality of insulating plates and the partial substrate, and a step of forming a through hole penetrating all the insulating plates, and connecting wirings of the upper and lower insulating plates through the through holes. Forming a through-hole penetrating the partial substrate and all the insulating plates below the partial substrate, and connecting wiring in the partial substrate and wiring of the insulating plate through the through-hole; A sixth aspect of the present invention provides a circuit board manufacturing method,
A step of preparing a partial substrate in which wiring and interlayer insulating films are alternately laminated on an insulating substrate, and a connection hole connected to any of the wirings is formed in the insulating substrate, A step of preparing a plurality of insulating plates on which wiring is formed, such that a concave portion or a cutout portion is formed by superimposing sheets; and overlapping the plurality of insulating plates, and forming the partial substrate in the concave portion or the cutout portion. Placing the plurality of insulating plates and the partial substrate, and connecting the wiring in the partial substrate and the wiring of the insulating plate through a connection hole of the insulating substrate of the partial substrate; Forming a through-hole penetrating all the insulating plates, and connecting the wirings of the upper and lower insulating plates through the through-holes. Yes, before A conductive film connected to a wiring on the insulating substrate through a connection hole of the insulating substrate, a bonding insulating film having an opening on the conductive film, According to a sixth aspect of the present invention, there is provided a method for manufacturing a circuit board, wherein a conductive adhesive or a low melting point alloy material embedded in an opening of an insulating film for use is formed.

【0012】本発明においては、上下の配線同士が回路
基板を貫通する貫通孔を通して接続されている回路基板
の一部に、上下の配線同士が層間絶縁層のビアホールを
通して接続されている多層配線部分を有する。即ち、回
路基板には、インナビアホールによる配線接続領域と貫
通孔による配線接続領域が混在している。また、多層配
線部分内の配線と多層配線部分以外の回路基板の配線と
は、多層配線部分とその下の回路基板の両方を貫く貫通
孔を通して接続されるか、或いは、多層配線部分の接続
孔を通して接続される。
In the present invention, a multilayer wiring portion in which upper and lower wirings are connected to each other through a via hole in an interlayer insulating layer is connected to a part of a circuit board in which upper and lower wirings are connected through a through hole penetrating the circuit board. Having. That is, the circuit board has a wiring connection region formed by inner via holes and a wiring connection region formed by through holes. Further, the wiring in the multilayer wiring part and the wiring of the circuit board other than the multilayer wiring part are connected through a through hole penetrating both the multilayer wiring part and the circuit board thereunder, or a connection hole of the multilayer wiring part. Connected through.

【0013】ところで、隣接するインナビア間の間隔は
隣接する貫通孔間の間隔と比べて狭くしうる。しかも、
インナビアは、接続すべき異なる層の配線の間に介在す
る層間絶縁膜のみに形成されるのに対して、貫通孔は接
続すべき異なる層の配線の間のみでなく、回路基板全体
に及ぶ。このため、貫通孔による配線接続領域では配線
密度をあまり高くできないが、貫通孔が部品搭載領域に
露出するため挿入型部品を搭載することができる。一
方、インナビアによる配線接続領域では、貫通孔がない
ため挿入型部品を搭載することはできないが、配線密度
を高くすることができる。
Incidentally, the distance between adjacent inner vias can be made narrower than the distance between adjacent through holes. Moreover,
The inner via is formed only in the interlayer insulating film interposed between wirings of different layers to be connected, while the through hole extends not only between the wirings of different layers to be connected but also the entire circuit board. For this reason, although the wiring density cannot be increased so much in the wiring connection region by the through hole, the through hole is exposed to the component mounting region, so that the insertion type component can be mounted. On the other hand, in a wiring connection region formed by inner vias, insertion-type components cannot be mounted because there is no through hole, but the wiring density can be increased.

【0014】従って、配線密度の高い領域と貫通孔を有
する領域とが同一の回路基板に存在するため、例えば貫
通孔による配線接続領域に挿入型部品やサイズの大きい
回路部品を搭載し、インナビアによる配線接続領域にチ
ップ等の引出し電極数の多い高密度配線の必要な部品を
搭載することにより、半導体チップや挿入型部品及びそ
の他の必要な部品を同一の回路基板に搭載することがで
きる。
Therefore, since a region having a high wiring density and a region having a through-hole are present on the same circuit board, for example, an insertion-type component or a large-sized circuit component is mounted in a wiring connection region formed by the through-hole, and an inner via By mounting a component such as a chip that requires a large number of lead-out electrodes and needs high-density wiring in the wiring connection region, a semiconductor chip, an insertion-type component, and other necessary components can be mounted on the same circuit board.

【0015】また、インナビアによる配線接続領域(部
分基板)と貫通孔による配線接続領域(部分基板以外の
回路基板)とが同一の回路基板に形成されているので、
一度の加熱・溶着により必要な部品をすべて搭載するこ
とが出来る。従って、溶着するための加熱時期が、従来
のMCM基板を搭載するときのように搭載部品によって
ずれることはない。このため、同じ温度で溶融する一つ
の溶着材料を用いることができるとともに、回路基板や
回路部品のうちで、一部で特に耐熱性の高い基板材料や
部品材料を用いる必要もない。
Further, since the wiring connection region (partial substrate) by the inner via and the wiring connection region (circuit substrate other than the partial substrate) by the through-hole are formed on the same circuit substrate,
All necessary parts can be mounted by one heating / welding. Therefore, the heating time for welding does not shift depending on the mounted components as in the case of mounting the conventional MCM substrate. For this reason, one welding material that melts at the same temperature can be used, and it is not necessary to use a particularly heat-resistant board material or component material in a part of the circuit board or the circuit component.

【0016】さらに、部分基板内の配線と、部分基板以
外の回路基板内の配線とを接続するための導電性材料と
して低融点合金材料を用いたとき、低融点合金材料は予
め部分基板の裏面の接着用絶縁性膜内に埋め込まれてお
り、かつ部分基板と回路基板とはホットプレス等により
密着させうるので、部品搭載時の加熱により低融点合金
材料が溶融しても部分基板と回路基板の間に染みだすこ
とはない。このため、導電性材料として通常と異なる高
融点合金材料を用いる必要もない。
Further, when a low-melting alloy material is used as a conductive material for connecting the wiring in the partial substrate and the wiring in the circuit board other than the partial substrate, the low-melting alloy material is previously set on the back surface of the partial substrate. Embedded in the insulating film for bonding, and the partial substrate and the circuit board can be brought into close contact with each other by hot pressing or the like. It does not seep out between. Therefore, it is not necessary to use an unusual high melting point alloy material as the conductive material.

【0017】以上により、通常の基板材料を用いた回路
基板に通常の部品材料を用いた回路部品を簡単な作業で
搭載することができる。また、回路部品の引出し電極数
に応じた配線密度の領域を、搭載すべき回路部品の個数
に応じた大きさとすることができる。このため、回路基
板の高密度化を図ることができる。
As described above, a circuit component using a normal component material can be mounted on a circuit board using a normal substrate material by a simple operation. Further, the area of the wiring density corresponding to the number of lead electrodes of the circuit component can be set to a size corresponding to the number of circuit components to be mounted. For this reason, the density of the circuit board can be increased.

【0018】[0018]

【発明の実施の形態】以下に、本発明の実施の形態につ
いて図面を参照しながら説明する。 (1)第1の実施の形態 (薄膜多層基板(部分基板)の作成方法)図1(a)〜
(e)は、本発明の第1の実施の形態に係る薄膜多層基
板の作成方法について示す断面図である。以下の(a)
〜(e)の工程を経て薄膜多層基板111が完成する。
Embodiments of the present invention will be described below with reference to the drawings. (1) First Embodiment (Method of Producing Thin Film Multilayer Substrate (Partial Substrate)) FIGS.
(E) is a sectional view showing a method for producing a thin-film multilayer substrate according to the first embodiment of the present invention. The following (a)
Through the steps (e) to (e), the thin film multilayer substrate 111 is completed.

【0019】(a)まず、図1(a)に示すように、縦
横2インチで、厚さ0.9mmの、シリカ粉末を充填し
たビスマレイミド−トリアジン樹脂(BTレジン)基板
(絶縁性基板)21を用意する。 (b)その上に、図1(b)に示すように、無電解メッ
キ法で、厚さ10μmのCu膜22を形成する。
(A) First, as shown in FIG. 1A, a bismaleimide-triazine resin (BT resin) substrate (insulating substrate) having a length of 2 inches and a width of 0.9 mm and filled with silica powder is used. 21 is prepared. (B) A 10 μm thick Cu film 22 is formed thereon by electroless plating as shown in FIG. 1 (b).

【0020】(c)次いで、図1(c)に示すように、
Cu膜22上にフォトレジスト膜23を形成した後、露
光し、その後現像して配線を形成すべき領域にフォトレ
ジスト膜23を残す。次に、配線を形成すべき領域に残
るフォトレジスト膜23をマスクとしてCu膜22をエ
ッチングし、除去して最小線幅60μmの配線22aを
形成する。
(C) Next, as shown in FIG.
After a photoresist film 23 is formed on the Cu film 22, the photoresist film 23 is exposed and then developed to leave the photoresist film 23 in a region where a wiring is to be formed. Next, the Cu film 22 is etched and removed by using the photoresist film 23 remaining in the region where the wiring is to be formed as a mask to form a wiring 22a having a minimum line width of 60 μm.

【0021】(d)次いで、図1(d)に示すように、
配線22a上に膜厚30μmの感光性の多官能アクリル
樹脂膜24aを形成する。続いて、インナビアを形成す
べき領域以外を露光した後、現像液に浸けて現像し、未
露光部分を溶出させてインナビア(インナビアホール)
25aを形成する。以上により、一層目の配線22aと
これを被覆するインナビア25aを有する層間絶縁膜2
4aが形成される。
(D) Next, as shown in FIG.
A photosensitive polyfunctional acrylic resin film 24a having a thickness of 30 μm is formed on the wiring 22a. Subsequently, after exposing the area other than the area where the inner via is to be formed, the substrate is immersed in a developing solution and developed, and the unexposed part is eluted to form the inner via (inner via hole).
25a is formed. As described above, the interlayer insulating film 2 having the first-layer wiring 22a and the inner via 25a covering the first-layer wiring 22a
4a is formed.

【0022】(e)引き続き、上記(b)〜(d)の工
程を繰り返し、2層目以降の配線22b,22cと各層
の配線を被覆するインナビア25b,25cを有する層
間絶縁膜24b,24cを形成する。さらに、最上部に
配線22dのほか部品の搭載のためのパッドを形成す
る。以上により、薄膜多層基板111が完成する。
(E) Subsequently, the above-mentioned steps (b) to (d) are repeated, and the interlayer insulating films 24b and 24c having the second and later wirings 22b and 22c and the inner vias 25b and 25c covering the wirings of the respective layers are formed. Form. Further, pads for mounting components other than the wiring 22d are formed on the uppermost portion. As described above, the thin film multilayer substrate 111 is completed.

【0023】(回路基板の作成方法)図2(a)〜
(c)は、上記薄膜多層基板111を回路基板に入れ込
んでなる回路基板の作成方法について示す断面図であ
る。まず、図2(a)に示すように、線幅0.2mmで
適当な長さの銅膜からなる配線32aや電極32eを形
成したガラスエポキシ板31aと、配線32bを形成し
たガラスエポキシ板31bを作成する。
(Method of Forming Circuit Board) FIGS.
(C) is a sectional view showing a method for producing a circuit board in which the thin-film multilayer board 111 is inserted into a circuit board. First, as shown in FIG. 2A, a glass epoxy plate 31a on which a wiring 32a and an electrode 32e formed of a copper film having a line width of 0.2 mm and an appropriate length are formed, and a glass epoxy plate 31b on which a wiring 32b is formed. Create

【0024】さらに、上記と同じ様な配線32c,32
dや電極32fを張りつけたガラスエポキシ板31c〜
31eであって、薄膜多層基板111を入れ込む部分に
予め縦横2インチの開口部OP1〜OP3が形成された
ものを3枚作成する。開口部OP1〜OP3は、例えば
ガラスエポキシ板の打ち抜きにより形成される。上記の
ガラスエポキシ板31a〜31eの厚さは5枚とも凡そ
0.3mmである。
Further, the same wirings 32c and 32 as described above
d or glass epoxy plate 31c to which electrode 32f is attached
Three pieces 31e, in which openings OP1 to OP3 of 2 inches in length and width are formed in advance in a portion where the thin-film multilayer substrate 111 is to be inserted, are prepared. The openings OP1 to OP3 are formed, for example, by punching a glass epoxy plate. The thickness of each of the five glass epoxy plates 31a to 31e is approximately 0.3 mm.

【0025】次いで、厚さ0.05mmのエポキシプリ
プレグフィルム33a〜33dを各ガラスエポキシ板3
1a〜31eの間に挟んで重ねる。このとき、開口部が
形成されていない2枚のガラスエポキシ板31a,31
bを重ね、その上に開口部を有する3枚のガラスエポキ
シ板31c〜31eを重ねる。このとき、3枚のガラス
エポキシ板31c〜31eの開口部OP1〜OP3がす
べて丁度一致するように重ねる。ガラスエポキシ板31
cと31d、及びガラスエポキシ板31dと31eに挟
まれるエポキシプリプレグフィルム33c,33dに
は、ガラスエポキシ板31c〜31eの開口部と同じ位
置に、同じ大きさの開口部が形成されている。その他の
エポキシプリプレグフィルム33a,33bには開口部
が形成されていない。従って、開口部OP1〜OP3の
重なりによって形成される凹部の底部にはエポキシプリ
プレグフィルム33bが敷かれており、薄膜多層基板1
11はそのエポキシプリプレグフィルム33bの上に載
る。
Next, a 0.05 mm-thick epoxy prepreg film 33a to 33d was
1a to 31e and sandwich them. At this time, the two glass epoxy plates 31a and 31 having no openings are formed.
b, and three glass epoxy plates 31c to 31e having openings are stacked thereon. At this time, the three glass epoxy plates 31c to 31e are overlapped so that the openings OP1 to OP3 exactly coincide with each other. Glass epoxy board 31
In the epoxy prepreg films 33c and 33d sandwiched between c and 31d and the glass epoxy plates 31d and 31e, openings of the same size are formed at the same positions as the openings of the glass epoxy plates 31c to 31e. No openings are formed in the other epoxy prepreg films 33a and 33b. Therefore, the epoxy prepreg film 33b is laid on the bottom of the concave portion formed by the overlap of the openings OP1 to OP3, and the thin film multilayer substrate 1
11 is put on the epoxy prepreg film 33b.

【0026】次いで、図2(b)に示すように、開口部
OP1〜OP3の重なりによって形成される凹部115
内に上記の薄膜多層基板111を入れ込んだものを、温
度180℃,圧力10気圧の条件でホットプレスし、そ
れらを相互に固着させる。なお、ガラスエポキシ板31
a〜31eを5枚重ねた基板が回路基板112を構成す
る。
Next, as shown in FIG. 2B, a concave portion 115 formed by overlapping the openings OP1 to OP3.
The above-mentioned thin-film multilayer substrate 111 is hot-pressed at a temperature of 180 ° C. and a pressure of 10 atm to fix them together. The glass epoxy plate 31
The circuit board 112 is formed by stacking five boards a to 31e.

【0027】上記のように薄膜多層基板(部分基板)1
11を入れ込んだ回路基板112を形成した後、図2
(c)に示すように、回路基板112のガラスエポキシ
板31a〜31eの積層部分であって配線の層間接続を
行う部分、及び薄膜多層基板111内の配線と回路基板
112内の配線との相互接続を行う部分をドリルで孔明
けしてスルーホール(貫通孔)34a〜34dを形成す
る。
As described above, the thin film multilayer substrate (partial substrate) 1
After forming the circuit board 112 in which the substrate 11 is inserted, FIG.
As shown in (c), a portion where the glass epoxy plates 31a to 31e of the circuit board 112 are laminated and a portion where the wiring is connected between layers, and the mutual connection between the wires in the thin film multilayer board 111 and the wires in the circuit board 112. Portions to be connected are formed by drilling to form through holes (through holes) 34a to 34d.

【0028】続いて、スルーホール34a〜34d内を
一般のプリント基板の作成のときと同様に活性化した
後、無電解メッキを行ってスルーホール34a〜34d
の内壁に銅膜35a〜35dを形成する。これにより、
接続すべき異なる層の配線同士を接続させるとともに、
薄膜多層基板111内の配線と回路基板112内の配線
とを接続させる。
Subsequently, after the insides of the through holes 34a to 34d are activated in the same manner as when a general printed circuit board is formed, electroless plating is performed to perform through holes 34a to 34d.
Copper films 35a to 35d are formed on the inner wall of. This allows
While connecting the wiring of different layers to be connected,
The wiring in the thin-film multilayer substrate 111 and the wiring in the circuit board 112 are connected.

【0029】以上により、回路基板が完成する。その
後、図2(c)に示すように、回路基板を加熱した状態
で、薄膜多層基板111上にハンダ等を介してLSIチ
ップ122を載せ、薄膜多層基板111以外の回路基板
112上に挿入型部品121や配線密度の比較的低い回
路部品123をハンダ等を介して載せた後、冷却し、固
着させて回路装置が完成する。
As described above, the circuit board is completed. Thereafter, as shown in FIG. 2C, while the circuit board is being heated, the LSI chip 122 is mounted on the thin film multilayer substrate 111 via solder or the like, and is inserted into the circuit board 112 other than the thin film multilayer substrate 111. After placing the components 121 and the circuit components 123 having a relatively low wiring density via solder or the like, the components are cooled and fixed to complete the circuit device.

【0030】以上のように、本発明の第1の実施の形態
に係る回路基板においては、多層配線のうち異なる層の
配線同士がスルーホール34a,34dを通して接続さ
れた回路基板112内に、多層配線のうち異なる層の配
線同士が層間絶縁膜24a〜24cのインナビア25a
〜25cを通して接続された薄膜多層基板111が入れ
込まれ、回路基板112内の配線と薄膜多層基板111
内の配線とは、薄膜多層基板111及び回路基板112
を貫くスルーホール34b,34cを通して接続されて
いる。
As described above, in the circuit board according to the first embodiment of the present invention, in the circuit board 112 in which different layers of the multilayer wiring are connected through the through holes 34a and 34d, Wirings of different layers among the wirings are inner vias 25a of interlayer insulating films 24a to 24c.
Through the thin film multilayer substrate 111 connected through the wiring board 25c.
The wirings inside are the thin film multilayer board 111 and the circuit board 112
Are connected through through holes 34b and 34c penetrating through.

【0031】ところで、隣接するインナビア25a〜2
5c間の間隔は隣接するスルーホール34a〜34d間
の間隔と比べて狭くしうる。しかも、インナビア25a
〜25cは、接続すべき異なる層の配線の間に介在する
層間絶縁膜24a〜24cのみに形成されるのに対し
て、スルーホール34a〜34dは接続すべき異なる層
の配線の間のみでなく、回路基板112全体に形成され
る。
Incidentally, the adjacent inner vias 25a to 25a-2
The interval between 5c may be narrower than the interval between adjacent through holes 34a to 34d. Moreover, Innavia 25a
25c are formed only in the interlayer insulating films 24a to 24c interposed between the wirings of different layers to be connected, while the through holes 34a to 34d are formed not only between the wirings of the different layers to be connected but also Are formed over the entire circuit board 112.

【0032】このため、薄膜多層基板111以外の回路
基板112では配線密度をあまり高くできないが、スル
ーホール34a〜34dが部品搭載領域に露出するため
挿入型部品を搭載することができる。一方、薄膜多層基
板111では、インナビア25a〜25cが部品搭載領
域に露出していないため挿入型部品を搭載することはで
きないが、配線密度を高くすることができる。
For this reason, in the circuit board 112 other than the thin-film multilayer board 111, the wiring density cannot be increased so much. However, since the through holes 34a to 34d are exposed in the component mounting area, insertion type components can be mounted. On the other hand, in the thin-film multilayer substrate 111, since the inner vias 25a to 25c are not exposed to the component mounting area, insertion type components cannot be mounted, but the wiring density can be increased.

【0033】従って、配線密度の高い領域とスルーホー
ル34a〜34dを有する領域とが同一の回路基板に存
在するため、スルーホール34a〜34dを有する領域
に挿入型部品やサイズの大きい回路部品を搭載し、配線
密度の高い領域にチップ等の引出し電極数の多い部品を
搭載することにより、半導体チップや挿入型部品及びそ
の他の必要な部品を同一の回路基板に搭載することがで
きる。
Therefore, since a region having a high wiring density and a region having through holes 34a to 34d are present on the same circuit board, an insertion type component or a large-sized circuit component is mounted in the region having through holes 34a to 34d. By mounting a component having a large number of lead electrodes such as a chip in a region having a high wiring density, a semiconductor chip, an insertion component, and other necessary components can be mounted on the same circuit board.

【0034】しかも、薄膜多層基板111が回路基板1
12と一体的に形成されているので、一度の加熱・溶着
により必要な部品をすべて搭載することが出来る。従っ
て、溶着するための加熱時期が、従来のMCM基板を搭
載するときのように搭載部品によってずれることはな
い。このため、同じ温度で溶融する一つの溶着材料を用
いることができるとともに、回路基板や回路部品のうち
で、一部で特に耐熱性の高い基板材料や部品材料を用い
る必要もない。
In addition, the thin film multilayer substrate 111 is
Since it is formed integrally with the substrate 12, all necessary components can be mounted by heating and welding once. Therefore, the heating time for welding does not shift depending on the mounted components as in the case of mounting the conventional MCM substrate. For this reason, one welding material that melts at the same temperature can be used, and it is not necessary to use a particularly heat-resistant board material or component material in a part of the circuit board or the circuit component.

【0035】以上により、通常の基板材料を用いた回路
基板に通常の部品材料を用いた回路部品を簡単な作業で
搭載することができる。また、回路部品の引出し電極数
に応じた配線密度の領域を、搭載すべき回路部品の個数
に応じた大きさとすることができる。このため、回路基
板の高密度化を図ることができる。
As described above, a circuit component using a normal component material can be mounted on a circuit board using a normal substrate material by a simple operation. Further, the area of the wiring density corresponding to the number of lead electrodes of the circuit component can be set to a size corresponding to the number of circuit components to be mounted. For this reason, the density of the circuit board can be increased.

【0036】(2)第2の実施の形態 第2の実施の形態において、第1の実施の形態に係る回
路基板と異なるところは、薄膜多層基板113の下地基
板(絶縁性基板)41に予め下地基板41を貫通する基
板間接続孔44a,44bを形成し、この基板間接続孔
44a,44bを通して表面及び裏面の電極42a,4
3同士を接続し、その裏面側の基板間接続孔44a,4
4bに導電性接着剤55a,55bを埋め込んでいるこ
とである。そして、この基板間接続孔44a,44bの
導電性接着剤55a,55bを介して回路基板114内
の配線と薄膜多層基板(部分基板)113内の配線とが
接続される。
(2) Second Embodiment In the second embodiment, the difference from the circuit board according to the first embodiment is that the base substrate (insulating substrate) 41 of the thin-film multilayer substrate 113 is provided in advance. Inter-substrate connection holes 44a, 44b penetrating the base substrate 41 are formed, and the front and rear electrodes 42a, 4b are formed through the inter-substrate connection holes 44a, 44b.
3 are connected to each other, and the inter-substrate connection holes 44a, 44
4b is that the conductive adhesives 55a and 55b are embedded. Then, the wiring in the circuit board 114 and the wiring in the thin film multilayer substrate (partial substrate) 113 are connected via the conductive adhesives 55a and 55b of the inter-substrate connection holes 44a and 44b.

【0037】(薄膜多層基板(部分基板)の作成方法)
図3(a)〜(d),図4(a)〜(c)は、本発明の
第2の実施の形態に係る薄膜多層基板の作成方法につい
て示す断面図である。 (a)まず、図3(a)に示すように、縦横2インチ
で、厚さ0.8mmのガラスエポキシ基板(絶縁性基
板)41の両面に電極又は配線42a,43を形成す
る。続いて、そのガラスエポキシ板41の両端にある電
極又は配線42a,43を通るスルーホール(接続孔)
44a,44bを形成し、その内壁に導電膜45a,4
5bを形成して両面の電極又は配線42a,43同士を
接続する。次いで、スルーホール44a,44b内にエ
ポキシ樹脂46a,46bを充填する。
(Method of Making Thin Film Multilayer Substrate (Partial Substrate))
FIGS. 3A to 3D and FIGS. 4A to 4C are cross-sectional views showing a method for manufacturing a thin-film multilayer substrate according to the second embodiment of the present invention. (A) First, as shown in FIG. 3A, electrodes or wirings 42a and 43 are formed on both sides of a glass epoxy substrate (insulating substrate) 41 having a length and width of 2 inches and a thickness of 0.8 mm. Subsequently, through holes (connection holes) passing through electrodes or wirings 42a and 43 at both ends of the glass epoxy plate 41 are provided.
44a, 44b are formed, and conductive films 45a, 4
5b is formed to connect the electrodes or wirings 42a, 43 on both surfaces. Next, epoxy resins 46a and 46b are filled in the through holes 44a and 44b.

【0038】(b)次いで、図3(b)に示すように、
両面にアクリル樹脂からなる接着層を形成した厚さ55
μmのポリイミドフィルムからなる層間絶縁膜47aと
厚さ10μmのCuホイル48をこの順にガラスエポキ
シ基板41の上に積層する。 (c)次いで、図3(c)に示すように、Cuホイル4
8上にフォトレジスト膜49を形成した後、露光し、そ
の後現像してインナビアホールを形成すべき領域にフォ
トレジスト膜49の開口部を形成する。
(B) Next, as shown in FIG.
Thickness 55 with adhesive layers made of acrylic resin formed on both sides
An interlayer insulating film 47a made of a μm polyimide film and a Cu foil 48 having a thickness of 10 μm are laminated on the glass epoxy substrate 41 in this order. (C) Next, as shown in FIG.
After a photoresist film 49 is formed on the substrate 8, the photoresist film 49 is exposed and then developed to form an opening of the photoresist film 49 in a region where an inner via hole is to be formed.

【0039】続いて、フォトレジスト膜49の開口部を
通してCuホイル48をエッチングし、ポリイミドフィ
ルム47aを露出させる。次いで、KrFエキシマレー
ザを全面に照射し、レーザアブレーションによってフォ
トレジスト膜49の開口部内に露出したポリイミドフィ
ルム47aをエッチングし、除去してCuホイル48b
及びポリイミドフィルム47aを貫通する開口部(イン
ナビアホール)50aを形成する。
Subsequently, the Cu foil 48 is etched through the opening of the photoresist film 49 to expose the polyimide film 47a. Next, the entire surface is irradiated with a KrF excimer laser, and the polyimide film 47a exposed in the opening of the photoresist film 49 is etched and removed by laser ablation to remove the Cu foil 48b.
Then, an opening (inner via hole) 50a penetrating through the polyimide film 47a is formed.

【0040】(d)次に、図3(d)に示すように、フ
ォトレジスト膜49を除去した後、開口部50a内及び
Cuホイル48b上に無電解メッキによってCu膜51
bを形成する。 (e)次いで、図4(a)に示すように、フォトレジス
ト膜52を形成した後、露光し、その後現像して配線を
形成すべき領域にフォトレジスト膜52を残す。このフ
ォトレジスト膜52をマスクとしてCu膜51b及びC
uホイル48bをエッチングし、除去して最小線幅60
μmの第2層目の配線42bを形成する。
(D) Next, as shown in FIG. 3D, after removing the photoresist film 49, the Cu film 51 is formed by electroless plating in the opening 50a and on the Cu foil 48b.
b is formed. (E) Next, as shown in FIG. 4A, after a photoresist film 52 is formed, exposure is performed, and then development is performed to leave the photoresist film 52 in a region where a wiring is to be formed. Using the photoresist film 52 as a mask, the Cu film 51b and C
u foil 48b is etched and removed to obtain a minimum line width of 60
A second layer wiring 42b of μm is formed.

【0041】以上により、第1層目及び第2層目の配線
42a,42bとこれらの間に挟まれたインナビアホー
ル50aを有する層間絶縁膜47aが形成される。 (f)引き続き、上記(b)〜(e)の工程を繰り返
し、図4(b)に示すように、層間絶縁膜47bと3層
目の配線42cと層間絶縁膜47cとを順に形成し、さ
らに最上層の層間絶縁膜47c上に4層目の配線と部品
搭載のためのパッド42dを形成する。
As described above, the interlayer insulating film 47a having the first and second wiring layers 42a and 42b and the inner via hole 50a interposed therebetween is formed. (F) Subsequently, the above steps (b) to (e) are repeated, and as shown in FIG. 4B, an interlayer insulating film 47b, a third-layer wiring 42c, and an interlayer insulating film 47c are sequentially formed. Further, a fourth-layer wiring and a pad 42d for mounting components are formed on the uppermost interlayer insulating film 47c.

【0042】(g)以上のようにして4層の配線を形成
した後、図4(c)に示すように、絶縁性基板の裏面に
エポキシプリプレグフィルム(接着用絶縁膜)53を置
き、エポキシプリプレグフィルム53が硬化しない程度
の温度凡そ120℃に加熱して接着する。次に、エキシ
マレーザを部分的に照射して電極43及び導電膜45
a,45b上のエポキシプリプレグフィルム53を除去
する。
(G) After the four-layer wiring is formed as described above, an epoxy prepreg film (adhesive insulating film) 53 is placed on the back surface of the insulating substrate as shown in FIG. The prepreg film 53 is adhered by heating to a temperature of about 120 ° C. at which the prepreg film 53 does not cure. Next, the electrode 43 and the conductive film 45 are partially irradiated with an excimer laser.
The epoxy prepreg film 53 on a and 45b is removed.

【0043】次いで、銀粉と熱硬化型のエポキシ樹脂か
らなる導電性接着剤55a,55bを印刷により電極4
3及び導電膜45a,45b上に形成する。以上によ
り、薄膜多層基板113が完成する。 (回路基板の作成方法)図5(a)〜(c)は、本発明
の第2の実施の形態に係る回路基板の作成方法について
示す断面図である。
Next, conductive adhesives 55a and 55b made of silver powder and a thermosetting epoxy resin are applied to the electrodes 4 by printing.
3 and the conductive films 45a and 45b. As described above, the thin film multilayer substrate 113 is completed. (Method of Manufacturing Circuit Board) FIGS. 5A to 5C are cross-sectional views illustrating a method of manufacturing a circuit board according to the second embodiment of the present invention.

【0044】まず、図5(a)に示すように、第1の実
施の形態と同じエポキシプリプレグフィルム63a〜6
3dを間に挟んで第1の実施の形態と同じガラスエポキ
シ板61a〜61eを5枚、薄膜多層基板113を入れ
込む凹部116が形成されるように重ねる。このとき、
エポキシプリプレグフィルム63bには開口部が形成さ
れており、かつ第2層目のガラスエポキシ板61bの上
面には、第1の実施の形態の配線のほかに薄膜多層基板
113の裏面の導電性接着剤55a,55bと接続させ
る電極又は配線62bが形成されている。従って、凹部
116の底部には電極又は配線62bが露出し、薄膜多
層基板113の導電性接着剤55a,55bと接触する
ようになっている。
First, as shown in FIG. 5A, the same epoxy prepreg films 63a to 63a as in the first embodiment are used.
Five glass epoxy plates 61a to 61e, which are the same as those in the first embodiment, are stacked so as to form a concave portion 116 into which the thin-film multilayer substrate 113 is inserted, with 3d interposed therebetween. At this time,
An opening is formed in the epoxy prepreg film 63b, and on the upper surface of the glass epoxy plate 61b of the second layer, in addition to the wiring of the first embodiment, the conductive adhesive of the back surface of the thin film multilayer substrate 113 is provided. An electrode or wiring 62b to be connected to the agents 55a and 55b is formed. Therefore, the electrode or wiring 62b is exposed at the bottom of the concave portion 116 and comes into contact with the conductive adhesives 55a and 55b of the thin film multilayer substrate 113.

【0045】次いで、回路基板の凹部116内に上記の
薄膜多層基板113を入れ込んだものを、温度180
℃,圧力10気圧の条件でホットプレスし、それらを相
互に固着させる。このとき、薄膜多層基板113裏面の
電極43及び導電膜45a,45bと2層目のガラスエ
ポキシ基板61b上の電極又は配線62bとが導電性接
着剤55a,55bを介して圧着される。なお、ガラス
エポキシ板61a〜61eを5枚重ねた基板が薄膜多層
基板113以外の回路基板114を構成する。
Next, the above-mentioned thin film multilayer substrate 113 placed in the concave portion 116 of the circuit board is heated at a temperature of 180 °.
Hot pressing is performed at a temperature of 10 ° C. and a pressure of 10 atm. At this time, the electrodes 43 and the conductive films 45a and 45b on the back surface of the thin-film multilayer substrate 113 and the electrodes or wirings 62b on the second-layer glass epoxy substrate 61b are pressed together via the conductive adhesives 55a and 55b. A circuit board 114 other than the thin film multilayer board 113 constitutes a circuit board in which five glass epoxy plates 61 a to 61 e are stacked.

【0046】次いで、加熱して薄膜多層基板113裏面
の電極及び導電膜45a,45bと2層目のガラスエポ
キシ板61b上の電極又は配線62bとの間で電気的な
接続を得る。上記のように薄膜多層基板113を入れ込
んだ回路基板114を形成した後、回路基板114のガ
ラスエポキシ板61a〜61eの積層部分であって層間
接続を行う部分をドリルで孔明けしてスルーホール(貫
通孔)64a,64bを形成する。
Then, heating is performed to obtain an electrical connection between the electrodes and the conductive films 45a and 45b on the back surface of the thin-film multilayer substrate 113 and the electrodes or wirings 62b on the second-layer glass epoxy plate 61b. After forming the circuit board 114 in which the thin-film multilayer board 113 is inserted as described above, a portion where the glass epoxy plates 61a to 61e of the circuit board 114 are to be connected to form an interlayer connection is drilled to form a through hole. (Through holes) 64a and 64b are formed.

【0047】続いて、スルーホール64a,64b内を
活性化した後、無電解メッキによりスルーホール64
a,64bの内壁に銅膜65a,65bを形成する。こ
れにより、接続すべき異なる層の配線同士を接続させ
る。以上により、回路基板が完成する。その後、図5
(c)に示すように、回路基板を加熱した状態で、薄膜
多層基板113上にハンダ等を介してLSIチップ12
2を載せ、薄膜多層基板113以外の回路基板114上
に挿入型部品121や配線密度の比較的低い回路部品1
23をハンダ等を介して載せた後、冷却し、固着させて
回路装置が完成する。
Subsequently, after activating the insides of the through holes 64a and 64b, the through holes 64a and 64b are electrolessly plated.
Copper films 65a and 65b are formed on the inner walls of a and 64b. Thus, wires of different layers to be connected are connected to each other. Thus, a circuit board is completed. Then, FIG.
As shown in (c), while the circuit board is heated, the LSI chip 12 is placed on the thin-film multilayer board 113 via solder or the like.
2 on a circuit board 114 other than the thin-film multilayer board 113, the insertion-type component 121 or the circuit component 1 having a relatively low wiring density.
23 is placed via solder or the like, then cooled and fixed to complete the circuit device.

【0048】以上のように、本発明の第2の実施の形態
に係る回路基板においては、第1の実施の形態と同様
に、配線密度の高い領域とスルーホール64a,64b
を有する領域とが同一の回路基板に存在するため、スル
ーホール64a,64bを有する領域に挿入型部品やサ
イズの大きい回路部品を搭載し、配線密度の高い領域に
チップ等の引出し電極数の多い部品を搭載することによ
り、半導体チップや挿入型部品及びその他の必要な部品
を同一の回路基板に搭載することができる。
As described above, in the circuit board according to the second embodiment of the present invention, similarly to the first embodiment, the region having a high wiring density and the through holes 64a, 64b
Is located on the same circuit board, so that insert-type components or large-sized circuit components are mounted in the regions having the through holes 64a and 64b, and the number of lead-out electrodes such as chips is large in the region with high wiring density. By mounting the components, the semiconductor chip, the insertion type component, and other necessary components can be mounted on the same circuit board.

【0049】また、薄膜多層基板113が回路基板11
4内に入れ込まれて一体的に形成されているので、一度
の加熱・溶着により必要な部品をすべて搭載することが
出来る。このため、同じ温度で溶融する一つの溶着材料
を用いることができるとともに、回路基板や回路部品の
うちで、一部で特に耐熱性の高い基板材料や部品材料を
用いる必要もない。
Further, the thin film multilayer substrate 113 is
4 and is integrally formed, so that all necessary components can be mounted by heating and welding once. For this reason, one welding material that melts at the same temperature can be used, and it is not necessary to use a particularly heat-resistant board material or component material in a part of the circuit board or the circuit component.

【0050】以上により、通常の基板材料を用いた回路
基板に通常の部品材料を用いた回路部品を簡単な作業で
搭載することができる。また、回路部品の引出し電極数
に応じた配線密度の領域を、搭載すべき回路部品の個数
に応じた大きさとすることができる。このため、回路基
板の高密度化を図ることができる。
As described above, a circuit component using a normal component material can be mounted on a circuit board using a normal substrate material by a simple operation. Further, the area of the wiring density corresponding to the number of lead electrodes of the circuit component can be set to a size corresponding to the number of circuit components to be mounted. For this reason, the density of the circuit board can be increased.

【0051】なお、第2の実施の形態では、薄膜多層基
板113内の配線と薄膜多層基板113以外の回路基板
114内の配線とを接続するための導電性材料として導
電性接着剤55a,55bを用いているが、ハンダ等の
低融点合金材料を用いてもよい。この場合、低融点合金
材料は予め第2の基板の下面の接着用絶縁性膜53の開
口部54a,54b内に埋め込まれ、かつ回路基板11
4と薄膜多層基板113とがホットプレスにより密着さ
れているので、部品搭載時の加熱により溶融しても回路
基板の層間の隙間等に染みだすことはない。従って、導
電性材料として高融点合金材料を用いなくてもよいの
で、通常の基板材料を用いた回路基板に通常の部品材料
を用いた回路部品を簡単な作業で搭載することができ
る。
In the second embodiment, the conductive adhesives 55a and 55b are used as conductive materials for connecting the wiring in the thin-film multilayer substrate 113 and the wiring in the circuit board 114 other than the thin-film multilayer substrate 113. Although a low melting point alloy material such as solder may be used. In this case, the low melting point alloy material is embedded in the openings 54a and 54b of the bonding insulating film 53 on the lower surface of the second substrate in advance, and
4 and the thin-film multilayer substrate 113 are in close contact with each other by hot pressing, so that even if they are melted by heating when mounting components, they do not seep into gaps between layers of the circuit board. Therefore, since a high melting point alloy material need not be used as the conductive material, a circuit component using a normal component material can be mounted on a circuit board using a normal substrate material by a simple operation.

【0052】なお、上記第1及び第2の実施の形態で
は、貫通孔による配線接続領域である回路基板112,
114の凹部115,116に部分基板(インナビアに
よる配線接続領域)111,113が搭載されている
が、第1の実施の形態の回路基板112を用いて例示す
る図6に示すように、回路基板112の切欠部117に
部分基板(インナビアによる配線接続領域)111が搭
載されてもよい。
In the first and second embodiments, the circuit board 112, which is a wiring connection area by a through hole,
Although the partial substrates (wiring connection regions by inner vias) 111 and 113 are mounted in the concave portions 115 and 116 of the 114, as shown in FIG. 6 which is exemplified using the circuit substrate 112 of the first embodiment, The partial substrate (wiring connection region by inner via) 111 may be mounted in the cutout 117 of the 112.

【0053】また、複数の絶縁板を重ね、固着する回路
基板112,114の作成と回路基板112,114へ
の部分基板111,113の搭載とを同時に行っている
が、まず、複数の絶縁板を重ね、固着して凹部や切欠部
を有する回路基板112を作成し、その後、凹部や切欠
部に部分基板111,113を搭載してもよい。
The circuit boards 112 and 114 for stacking and fixing a plurality of insulating boards and the mounting of the partial boards 111 and 113 on the circuit boards 112 and 114 are simultaneously performed. May be stacked and fixed to form a circuit board 112 having a concave portion or a cutout portion, and then the partial substrates 111 and 113 may be mounted in the concave portion or the cutout portion.

【0054】[0054]

【発明の効果】以上のように、本発明によれば、層間の
配線同士が貫通孔を通して接続された回路基板の一部
に、層間の配線同士が所謂インナビアホールを通して接
続された多層配線部分が設けられている。即ち、配線密
度の高い領域と貫通孔を有する領域とが同一の回路基板
に存在するため、半導体チップや挿入型部品及びその他
の必要な部品を同一の回路基板に搭載することができ
る。
As described above, according to the present invention, a multilayer wiring portion in which the interlayer wirings are connected to each other through a so-called inner via hole is provided on a part of the circuit board where the interlayer wirings are connected through the through holes. Is provided. That is, since the region having a high wiring density and the region having the through-hole exist on the same circuit board, the semiconductor chip, the insertion type component, and other necessary components can be mounted on the same circuit board.

【0055】しかも、インナビアホールによる配線接続
領域(部分基板)と貫通孔による配線接続領域(部分基
板以外の回路基板)とが一体的に形成されているので、
一度の加熱・溶着により必要な部品をすべて部品搭載領
域に搭載することが出来、加熱時期をずらす必要はな
い。このため、同じ温度で溶融する一つの溶着材料を用
いることができるとともに、回路基板や回路部品のうち
で、その一部に特に耐熱性の高い基板材料や部品材料を
用いる必要もない。
Further, since the wiring connection region (partial substrate) by the inner via hole and the wiring connection region (circuit substrate other than the partial substrate) by the through hole are formed integrally,
All necessary components can be mounted in the component mounting area by a single heating and welding process, and there is no need to shift the heating timing. Therefore, it is possible to use one welding material that melts at the same temperature, and it is not necessary to use a particularly heat-resistant board material or component material for a part of the circuit board or the circuit component.

【0056】また、部分基板内の配線と部分基板以外の
回路基板内の配線とを接続するために低融点合金材料を
用いた場合、低融点合金材料は予め部分基板の下面の接
着用絶縁性膜の開口部内に埋め込まれているので、部品
搭載時の加熱により低融点合金材料が溶融しても部分基
板と回路基板の間の隙間等に染みだすことはない。この
ため、導電性材料として通常と異なる高融点合金材料を
用いる必要もない。
When a low-melting-point alloy material is used to connect the wiring in the partial substrate to the wiring in the circuit board other than the partial substrate, the low-melting-point alloy material may be used as a bonding insulating material on the lower surface of the partial substrate in advance. Since it is embedded in the opening of the film, even if the low-melting alloy material is melted by heating at the time of mounting components, it does not seep into the gap between the partial board and the circuit board. Therefore, it is not necessary to use an unusual high melting point alloy material as the conductive material.

【0057】以上のように、通常の基板材料を用いた回
路基板に通常の部品材料を用 いた回路部品を簡単な作
業で搭載することができる。また、回路部品の引出し電
極数に応じた配線密度の領域を、搭載すべき回路部品の
個数に応じた大きさとすることができ、このため、回路
基板の高密度化を図ることができる。
As described above, a circuit component using a normal component material can be mounted on a circuit board using a normal substrate material by a simple operation. In addition, the area of the wiring density according to the number of lead electrodes of the circuit component can be set to a size corresponding to the number of circuit components to be mounted, so that the density of the circuit board can be increased.

【図面の簡単な説明】[Brief description of the drawings]

【図1】図1(a)〜(e)は、本発明の第1の実施の
形態に係る薄膜多層基板の作成方法について示す断面図
である。
FIGS. 1A to 1E are cross-sectional views showing a method for producing a thin-film multilayer substrate according to a first embodiment of the present invention.

【図2】図2(a)〜(c)は、本発明の第1の実施の
形態に係る回路基板の作成方法について示す断面図であ
る。
FIGS. 2A to 2C are cross-sectional views illustrating a method for manufacturing a circuit board according to the first embodiment of the present invention.

【図3】図3(a)〜(d)は、本発明の第2の実施の
形態に係る薄膜多層基板の作成方法について示す断面図
(その1)である。
FIGS. 3A to 3D are cross-sectional views (part 1) illustrating a method for manufacturing a thin-film multilayer substrate according to a second embodiment of the present invention.

【図4】図4(a)〜(c)は、本発明の第2の実施の
形態に係る薄膜多層基板の作成方法について示す断面図
(その2)である。
FIGS. 4A to 4C are cross-sectional views (part 2) illustrating a method of manufacturing a thin-film multilayer substrate according to a second embodiment of the present invention.

【図5】図5(a)〜(c)は、本発明の第2の実施の
形態に係る回路基板の作成方法について示す断面図であ
る。
FIGS. 5A to 5C are cross-sectional views illustrating a method of manufacturing a circuit board according to a second embodiment of the present invention.

【図6】図6は、本発明の他の実施の形態に係る回路基
板について示す断面図である。
FIG. 6 is a cross-sectional view showing a circuit board according to another embodiment of the present invention.

【図7】図7(a)〜(c)は、従来例に係る回路基板
の作成方法について示す断面図である。
FIGS. 7A to 7C are cross-sectional views illustrating a method of manufacturing a circuit board according to a conventional example.

【図8】図8は、従来例に係る薄膜多層基板について示
す断面図である。
FIG. 8 is a sectional view showing a thin-film multilayer substrate according to a conventional example.

【図9】図9は、従来例に係る回路基板上に回路部品が
搭載された回路装置を示す断面図である。
FIG. 9 is a cross-sectional view showing a circuit device according to a conventional example in which circuit components are mounted on a circuit board.

【符号の説明】[Explanation of symbols]

21 BTレジン基板(絶縁性基板)、 22 Cu膜、 22a〜22d,32a〜32f,42a〜42d,6
2a〜62f 配線又は電極、 23,49,52 フォトレジスト膜、 24a〜24c,47a〜47c 層間絶縁膜、 25a〜25c,50a〜50c インナビアホール
(ビアホール)、 31a〜31e,61a〜61e ガラスエポキシ板
(絶縁板)、 33a〜33d,63a〜63d エポキシプリプレグ
フィルム、 34a〜34d,64a,64b スルーホール(貫通
孔)、 35a〜35d,65a,65b 銅膜、 41 ガラスエポキシ基板(絶縁性基板)、 43 、 44a,44b スルーホール(接続孔)、 45a,45b 導電膜、 46a,46b エポキシ樹脂、 47a〜47c ポリイミドフィルム(層間絶縁膜)、 48,48b Cuホイル、 51b Cu膜、 53 エポキシプリプレグフィルム(接着用絶縁膜)、 54a,54b 開口部、 55a,55b 導電性接着剤、 111,113 薄膜多層基板(部分基板)、 112,114 回路基板、 115,116 凹部、 117 切欠部、 121 挿入型部品、 122 LSIチップ、 123 回路部品。
21 BT resin substrate (insulating substrate), 22 Cu film, 22a to 22d, 32a to 32f, 42a to 42d, 6
2a to 62f Wiring or electrode, 23, 49, 52 Photoresist film, 24a to 24c, 47a to 47c Interlayer insulating film, 25a to 25c, 50a to 50c Inner via hole (via hole), 31a to 31e, 61a to 61e Glass epoxy plate (Insulating plate), 33a-33d, 63a-63d epoxy prepreg film, 34a-34d, 64a, 64b through hole (through hole), 35a-35d, 65a, 65b copper film, 41 glass epoxy substrate (insulating substrate), 43, 44a, 44b through hole (connection hole), 45a, 45b conductive film, 46a, 46b epoxy resin, 47a to 47c polyimide film (interlayer insulating film), 48, 48b Cu foil, 51b Cu film, 53 epoxy prepreg film ( Insulating film for bonding), 54a, 54b opening, 55a, 55b conductive adhesive, 111, 113 thin-film multilayer substrate (partial substrate), 112, 114 circuit board, 115, 116 recess, 117 notch, 121 insertion type component, 122 LSI chip, 123 circuit component .

Claims (7)

【特許請求の範囲】[Claims] 【請求項1】 複数の配線が該配線間に絶縁板を挟んで
積層され、上下の前記配線同士が全ての前記絶縁板を貫
通する貫通孔を通して接続されている回路基板であっ
て、 前記回路基板の一部に、複数の配線が該配線間に層間絶
縁膜を挟んで積層され、上下の前記配線同士が該下方の
配線上に形成された層間絶縁膜のインナビアホールを通
して接続されている多層配線部分が設けられ、該多層配
線部分の表面を含む前記回路基板の部品搭載面がほぼ平
坦になっていることを特徴とする回路基板。
1. A circuit board wherein a plurality of wirings are stacked with an insulating plate interposed between the wirings, and the upper and lower wirings are connected to each other through through holes penetrating all the insulating plates. A multilayer in which a plurality of wirings are stacked on a part of a substrate with an interlayer insulating film interposed therebetween, and the upper and lower wirings are connected to each other through inner via holes of an interlayer insulating film formed on the lower wirings. A circuit board, wherein a wiring portion is provided, and a component mounting surface of the circuit board including a surface of the multilayer wiring portion is substantially flat.
【請求項2】 前記多層配線部分は、前記回路基板の凹
部又は切欠部に形成されていることを特徴とする請求項
1に記載の回路基板。
2. The circuit board according to claim 1, wherein the multilayer wiring portion is formed in a recess or a cutout of the circuit board.
【請求項3】 前記多層配線部分と、該多層配線部分の
下方の前記回路基板とを貫通する貫通孔を通して、前記
多層配線部分内の配線と前記回路基板内の配線とが接続
されていることを特徴とする請求項2に記載の回路基
板。
3. The wiring in the multilayer wiring part and the wiring in the circuit board are connected through a through hole penetrating the multilayer wiring part and the circuit board below the multilayer wiring part. The circuit board according to claim 2, wherein:
【請求項4】 前記インナビアホールを有する多層配線
部分内の配線と前記多層配線部分の下方の回路基板内の
配線とは、前記多層配線部分の接続孔を通して接続され
ていることを特徴とする請求項2に記載の回路基板。
4. The wiring in the multilayer wiring portion having the inner via hole and a wiring in a circuit board below the multilayer wiring portion are connected through a connection hole in the multilayer wiring portion. Item 3. The circuit board according to item 2.
【請求項5】 絶縁性基板上に配線と層間絶縁膜とを交
互に積層し、かつインナビアホールを通して前記層間絶
縁膜の上下の配線を接続してなる部分基板を準備する工
程と、 複数枚の重ね合わせにより凹部又は切欠部が形成される
ような、配線が形成された複数の絶縁板を準備する工程
と、 前記複数の絶縁板を重ねるとともに、前記凹部又は前記
切欠部に前記部分基板を置く工程と、 前記複数の絶縁板と前記部分基板を固着させる工程と、 前記全ての絶縁板を貫く貫通孔を形成し、該貫通孔を通
して上下の前記絶縁板の配線同士を接続する工程と、 前記部分基板と該部分基板の下にある全ての前記絶縁板
とを貫通する貫通孔を形成し、該貫通孔を通して前記部
分基板内の配線と前記絶縁板の配線とを接続する工程と
を有することを特徴とする回路基板の製造方法。
5. A step of preparing a partial substrate in which wirings and interlayer insulating films are alternately laminated on an insulating substrate, and connecting upper and lower wirings of the interlayer insulating film through inner via holes; A step of preparing a plurality of insulating plates on which wiring is formed such that a concave portion or a cutout portion is formed by superimposing; and placing the partial substrate in the concave portion or the cutout portion while overlapping the plurality of insulating plates. Fixing the plurality of insulating plates and the partial substrate, forming a through hole penetrating all the insulating plates, and connecting wirings of the upper and lower insulating plates through the through holes; Forming a through-hole penetrating the partial substrate and all of the insulating plates below the partial substrate, and connecting wiring in the partial substrate and wiring of the insulating plate through the through-hole. Characterized by Method of manufacturing a circuit board.
【請求項6】 絶縁性基板上に配線と層間絶縁膜とを交
互に積層し、かつ該配線のいずれかと繋がる接続孔を前
記絶縁性基板に形成してなる部分基板を準備する工程
と、 複数枚の重ね合わせにより凹部又は切欠部が形成される
ような、配線が形成された複数の絶縁板を準備する工程
と、 前記複数の絶縁板を重ねるとともに、前記凹部又は前記
切欠部に前記部分基板を置く工程と、 前記複数の絶縁板と前記部分基板を固着させるととも
に、前記部分基板の絶縁性基板の接続孔を通して前記部
分基板内の配線と前記絶縁板の配線とを接続する工程
と、 前記全ての絶縁板を貫く貫通孔を形成し、該貫通孔を通
して上下の前記絶縁板の配線同士を接続する工程とを有
することを特徴とする回路基板の製造方法。
6. A step of preparing a partial substrate in which wirings and interlayer insulating films are alternately laminated on an insulating substrate and connection holes connected to any of the wirings are formed in the insulating substrate. A step of preparing a plurality of insulating plates on which wiring is formed, such that a concave portion or a cutout portion is formed by superimposing sheets; and superposing the plurality of insulating plates, and forming the partial substrate in the concave portion or the cutout portion. Placing the plurality of insulating plates and the partial substrate together, and connecting a wiring in the partial substrate and a wiring of the insulating plate through a connection hole of the insulating substrate of the partial substrate; Forming a through-hole penetrating all the insulating plates, and connecting the wiring of the upper and lower insulating plates through the through-holes.
【請求項7】 前記部分基板の絶縁性基板の下面には、
前記絶縁性基板の接続孔を通して前記絶縁性基板上の配
線と接続する導電膜と、該導電膜上に開口部を有する接
着用絶縁膜と、前記接着用絶縁膜の開口部内に埋め込ま
れた導電性接着剤又は低融点合金材料とが形成されてい
ることを特徴とする請求項6に記載の回路基板の製造方
法。
7. The lower surface of the insulating substrate of the partial substrate,
A conductive film connected to a wiring on the insulating substrate through a connection hole of the insulating substrate; a bonding insulating film having an opening on the conductive film; and a conductive film embedded in the opening of the bonding insulating film. 7. The method for manufacturing a circuit board according to claim 6, wherein a conductive adhesive or a low melting point alloy material is formed.
JP8968397A 1997-04-08 1997-04-08 Circuit board and manufacturing method thereof Expired - Fee Related JP3754171B2 (en)

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