JPH10284516A - Semiconductor device and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent chip crack in a semiconductor chip by providing a number of voids in a junction material when a semiconductor chip and a chip mounting part are joined by a junction material. SOLUTION: A recessed part of silver plating 3 applied to a chip mounting part 2b is formed to a lattice and a void part formed of a recessed part also thereby forms a lattice shape when a semiconductor chip 1 is mounted on the chip mounting part 2b. Therefore, a projecting part in a circumference of a recessed part in the silver plating 3 is formed of a square at approximately equal pitch lengthwise and breadthwise. It is possible to maintain the semiconductor chip 1 and the chip mounting part 2b divided by a void part of a junction material of both thereof, to relax thermal stress by a void part of a junction material when thermal stress is applied and as a result, to prevent a chip crack in the semiconductor chip 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor manufacturing technique, and more particularly to a small and surface-mount type semiconductor device for preventing occurrence of chip cracks and a method for manufacturing the same.

[0002]

2. Description of the Related Art The technology described below studies the present invention,
Upon completion, they were examined by the inventor, and the outline is as follows.

[0003] With the miniaturization and multifunctionality of electronic and communication devices, the miniaturization of semiconductor devices mounted thereon is also required.

Here, there is a so-called chip diode as an example of a small-sized semiconductor device having a semiconductor chip mounted thereon. The chip diode has a semiconductor chip mounted on a die pad portion (chip mounting portion) of a frame member.
Further, it has a structure in which the semiconductor chip and its peripheral portion are sealed with resin.

The smallest chip diode having a size of 1.6 × 0.8 mm has been commercialized.

Further, when a semiconductor device such as a chip diode is mounted on a mounting substrate, the semiconductor device is in a high temperature state (for example, 210 to 260 ° C.) due to solder reflow.
become.

As a result, in the encapsulated semiconductor device, temperature fluctuations occur due to heat at the time of solder reflow, so that thermal stress is applied to the joint between the die pad portion of the frame member and the semiconductor chip, and chip cracking occurs. May occur.

Further, if the external size of the semiconductor device is reduced along with the miniaturization, further large thermal stress is applied to the semiconductor chip.

In a small semiconductor device, a technique for improving the adhesion between a die pad portion of a frame member and a semiconductor chip is described in, for example, Japanese Utility Model Laid-Open No. 5-1225 or Japanese Patent Laid-Open No. 5-308083. further,
A technique for improving the adhesion between the die pad portion of the frame member and the resin sealing portion is disclosed in, for example, Japanese Utility Model Laid-Open No. 57-175448.
No., published in Japanese Unexamined Patent Publication No.

[0010]

However, in the above-mentioned technology, in the semiconductor device described in Japanese Utility Model Laid-Open No. 5-1225, solder is used as a bonding material, and silver plating is used as a buffer against stress. And a hole is provided in the die pad portion (island) of the frame member.

Accordingly, there is a problem that the manufacturing process of the frame member and the semiconductor device is complicated and the manufacturing cost is high.

Further, the semiconductor device described in Japanese Patent Application Laid-Open No. Hei 5-308083 forms an uneven portion on the back surface of a semiconductor chip. It is very difficult to process the uneven portion on the back surface of the semiconductor chip. There is a problem.

Further, the semiconductor device described in Japanese Utility Model Laid-Open No. 57-175448 has a groove formed on the back surface of the die pad portion of the frame member, and the adhesion between the die pad portion and the sealing resin can be improved. However, there is a problem that a chip crack generated in a semiconductor chip cannot be prevented.

An object of the present invention is to provide a semiconductor device for preventing chip cracks occurring in a semiconductor chip and a method for manufacturing the same.

The above and other objects and novel features of the present invention will become apparent from the description of the present specification and the accompanying drawings.

[0016]

SUMMARY OF THE INVENTION Among the inventions disclosed in the present application, the outline of a representative one will be briefly described.
It is as follows.

That is, a semiconductor device according to the present invention includes a frame member having a chip mounting portion for supporting a semiconductor chip, and a bonding material for bonding the semiconductor chip and the chip mounting portion. When the semiconductor chip and the chip mounting portion are bonded, a large number of voids are provided in the bonding material.

As a result, the degree of adhesion can be kept low while the semiconductor chip and the chip mounting portion are joined by the joining material.

That is, the semiconductor chip and the chip mounting portion can be joined by the joining material, and the two can be divided by the gaps of the joining material.

Accordingly, when thermal stress is applied to the semiconductor chip and the chip mounting portion, the thermal stress can be reduced by the voids of the bonding material, and as a result, chip cracks are formed in the semiconductor chip. Can be prevented.

Further, in the semiconductor device of the present invention, silver plating is used as the bonding material.

In the semiconductor device of the present invention, a large number of the voids are formed with regularity, and are provided separately on the chip mounting portion.

Further, the method of manufacturing a semiconductor device according to the present invention
A step of preparing a lead frame having a frame member provided with a chip mounting portion for supporting the semiconductor chip; and a step of arranging a bonding material having a large number of concave portions or holes in the semiconductor chip or the chip mounting portion. Forming a large number of voids in the bonding material by the concave portions or the holes, bonding the semiconductor chip and the chip mounting portion with the bonding material, and mounting the semiconductor chip on the chip mounting portion. Separating the frame member from the lead frame.

Further, in the method of manufacturing a semiconductor device according to the present invention, there is provided a step of preparing a lead frame having a frame member provided with a chip mounting portion for supporting the semiconductor chip; Applying silver plating, which is a joining material to be joined, to at least the chip mounting portion of the lead frame, and forming a number of recesses in the silver plating on the chip mounting portion;
Forming a number of voids in the silver plating by the recesses, joining the semiconductor chip and the chip mounting portion by the silver plating, and the frame member mounting the semiconductor chip on the chip mounting portion. Separating from the lead frame.

[0025]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a cross-sectional view showing an embodiment of the structure of a semiconductor device according to the present invention. FIG. 2 is an example of the embodiment of the structure of the semiconductor device according to the present invention in a state where a semiconductor chip and a chip mounting portion are joined. FIG. 3 is a partial plan view showing an embodiment of a thin plate structure forming a lead frame used in the semiconductor device of the present invention, and FIG. 4 is a chip mounting portion in the semiconductor device of the present invention. It is a figure which shows an example of embodiment of the structure of the lattice-shaped recessed part formed in the upper joining material, (a) is an expanded partial plan view, (b) is an enlarged view which shows the AA cross section of (a). FIG. 5 is a cross-sectional view, and FIG. 5 is a perspective view showing an example of the embodiment of the structure of the semiconductor device according to the present invention.

The semiconductor device according to the present embodiment is a small, resin-sealed type diode on which a semiconductor chip 1 made of silicon is mounted, and is a surface mount type, also called a chip diode.

The structure of the chip diode shown in FIGS. 1 and 5 is a frame member 2a having a chip mounting portion 2b for supporting the semiconductor chip 1, and a bonding material for bonding the semiconductor chip 1 and the chip mounting portion 2b. When the semiconductor chip 1 and the chip mounting portion 2b are joined by the silver plating 3, the silver plating 3 is formed. Are provided with a large number of voids 6.

The frame member 2a used for the chip diode is included in the multiple lead frames 2 shown in FIG.

Here, the frame member 2a is composed of a chip mounting portion 2b for supporting the semiconductor chip 1, and a lead portion 2c electrically connected to the semiconductor chip 1.

Thus, the lead frame 2 includes the frame member 2a, the dam bar 2d for preventing the resin from flowing out at the time of resin sealing, the frame member 2a and the dam bar 2d.
d and the frame member 2a and the dam bar 2d
And an outer frame portion 2e that supports
The case where the lead frame 2 including the frame member 2a is formed of a copper alloy will be described.

However, the lead frame 2 may not necessarily be formed of a copper alloy, but may be formed of, for example, an alloy of iron and nickel.

The silver plating 3 is applied to at least the chip mounting portion 2b of the frame member 2a to a thickness of about 10 μm.

Further, in the chip diode of the present embodiment, when the semiconductor chip 1 and the chip mounting portion 2b are joined by silver plating 3 and the semiconductor chip 1 is mounted on the chip mounting portion 2b, the silver plating 3 A large number of voids 6 are formed with regularity, and the chip mounting portion 2b
Above, the gaps 6 are provided in a dispersed manner.

Here, in the present embodiment, a case where the regularity of the gaps 6 is a lattice will be described.

The gap 6 is formed by applying silver plating 3 to at least the chip mounting portion 2b of the frame member 2a.
It is formed from a concave portion 3 a provided in the silver plating 3.

That is, in the present embodiment, FIG.
As shown in FIG. 3, the concave portion 3a of the silver plating 3 applied to the chip mounting portion 2b is formed so as to form a lattice shape, so that when the semiconductor chip 1 is mounted on the chip mounting portion 2b. , A gap 6 formed by the recess 3a
Also form a lattice.

Here, as shown in FIG.
a is formed to have a depth of 7 μm, a width of 5 μm, and a bottom thickness of 3 μm, and is further formed in the chip mounting portion 2 b in a grid pattern at an installation pitch of about 50 μm in the vertical and horizontal directions.

Therefore, in the silver plating 3, the concave portions 3a
As shown in FIG. 4 (a), the convex portions 3b around are formed in a quadrangular shape at substantially equal vertical and horizontal pitches.

Further, as shown in FIG.
Is formed of silicon, the size of which is, for example,
It is a square with a length and width of 350 μm and a thickness of 15 μm.
It is about 0 to 180 μm.

For mounting (fixing) the semiconductor chip 1, a eutectic bonding method is used in which gold deposited on the back surface 1a of the semiconductor chip 1 and silver plating 3 as a bonding material.

That is, the bonding portion 7 between the semiconductor chip 1 and the chip mounting portion 2b is heated to a predetermined temperature, and at the same time, is subjected to ultrasonic vibration (ultrasonic bonding), so that the gold and silver plating 3 are fused. The semiconductor chip 1 is thermocompression-bonded to the chip mounting portion 2b.

Here, when a copper alloy is used for the frame member 2a, it is preferable to use silver plating 3 as a bonding material due to compatibility with copper.
For example, when using an alloy of iron and nickel,
It is also possible to use gold plating as a joining material.

In this case, the back surface 1a of the semiconductor chip 1
It is not necessary to deposit gold on the semiconductor chip 1, and the bonding of the semiconductor chip 1 is performed by eutectic of silicon of the semiconductor chip 1 and gold of the gold plating.

However, in the case of the gold plating, it is considered that the cost is high. Therefore, it is most preferable to use the silver plating 3 as the bonding material.

When the semiconductor chip 1 is pellet-bonded by ultrasonic bonding, a large number of recesses 3a provided in the silver plating 3 before joining are formed as lattice-shaped voids 6 in the silver plating 3 even after joining. Pellet bonding is performed so as to remain.

Here, the bonding conditions at the time of pellet bonding are the same as the bonding conditions when the concave portion 3a is not formed in the silver plating 3.

The surface electrode of the semiconductor chip 1 mounted on the chip mounting portion 2b is electrically connected to the lead portion 2c of the frame member 2a by a thin metal wire 8 formed of gold or the like.

Further, the semiconductor chip 1 and its peripheral portion 4 are resin-sealed with an epoxy-based thermosetting resin or the like, whereby a sealing main body 5 is formed.

The outer lead 2f of the lead 2c of the frame member 2a projecting from the sealing body 5
Is formed by bending into a desired shape after resin sealing.

A method for manufacturing the semiconductor device (chip diode) according to the present embodiment will be described.

First, an elongated thin plate 9 made of a copper alloy is prepared, whereby the lead frame 2 having the shape shown in FIG. 3 is manufactured.

In this embodiment, a case will be described in which silver plating 3, which is a bonding material between semiconductor chip 1 and chip mounting portion 2b, is applied to thin plate 9 before manufacturing lead frame 2.

First, the silver plating 3 is applied to the thin plate 9 in the shape of a strip in the vicinity of the center thereof in the longitudinal direction along the longitudinal direction so as to have a thickness of about 10 μm.

At this time, silver plating 3 is applied to at least a portion corresponding to chip mounting portion 2b of lead frame 2.

That is, when the lead frame 2 is manufactured from the thin plate 9, at least the chip mounting portion 2b is plated with silver.
Is applied to a position corresponding to the thin plate 9 in a strip shape with a predetermined width.

Subsequently, a number of recesses 3a are formed in the silver plating 3 applied near the center of the thin plate 9.

Here, in the present embodiment, FIG.
As shown in (a), the concave portions 3a are formed in a lattice shape. The recess 3a is formed in the silver plating 3 applied on the chip mounting portion 2b by stamping of a molding press.

At this time, as shown in FIG. 4B, for example, the depth of the concave portion 3a is 7 μm, the width is 5 μm, and the bottom thickness is 3 μm.
m, and concave portions 3a are formed at a pitch of about 50 μm in the vertical and horizontal directions to form a lattice shape.

When the silver plating 3 is embossed by a molding press, a dent may be formed on the thin plate 9 as well, but this is not a particular problem.

Further, in the concave portion 3a of the silver plating 3,
When embossing is performed, the bottom of the recess 3a may not be formed.

That is, the portion having a thickness of 3 μm in the concave portion 3a of the silver plating 3 shown in FIG. 4B is preferably formed, but need not be formed.

In the embossing by the forming press, since the concave portion 3a is formed by using an embossing die, it is preferable to perform the embossing over the entire area of the thin plate 9 where the silver plating 3 is applied. Easy.

That is, by forming the concave portion 3a over the entire area where the silver plating 3 of the thin plate 9 is applied by the embossing, the concave portion 3a is necessarily formed at the position corresponding to the chip mounting portion 2b. Will be.

However, it is not always necessary to perform the embossing over the entire area where the silver plating 3 is applied, and the engraving is performed only on the silver plating 3 applied at least on the area corresponding to the chip mounting portion 2b. The recess 3a may be formed.

In the present embodiment, when the recesses 3a are formed in a lattice shape using a mold of a molding press, the recesses 3a are divided into two times.

That is, the first stamping is performed in one predetermined direction, and then the second stamping is performed by changing the angle of the mold by 90 ° with respect to the longitudinal direction of the thin plate 9. The lattice-shaped concave portions 3a crossing 90 ° can be formed by one mold.

However, the formation of the lattice-shaped concave portion 3a by stamping is not limited to the use of one mold, and the lattice shape may be formed by a plurality of dies, for example. Alternatively, a lattice shape may be formed by one stamping using one mold.

Thereafter, in a forming step using the same forming press, the thin plate 9 is punched into a predetermined shape,
A multiple lead frame 2 having a frame member 2a provided with a chip mounting portion 2b for supporting the semiconductor chip 1 can be manufactured (prepared).

In the present embodiment, at this stage, at least the chip mounting portion 2b of the frame member 2a of the lead frame 2 has been coated with silver plating 3, and the silver plating 3 has a lattice-shaped recess. 3a are formed.

Thereafter, a semiconductor chip 1 having a thin gold film deposited on the back surface 1 a is prepared, and the semiconductor chip 1 is arranged on the chip mounting portion 2 b of the lead frame 2.

Subsequently, a number of voids 6 are formed in the silver plating 3 by the concave portions 3a, and pellet bonding for joining the semiconductor chip 1 and the chip mounting portion 2b by the silver plating 3 is performed.

That is, the bonding portion 7 between the semiconductor chip 1 and the chip mounting portion 2b is heated, and ultrasonic bonding is performed under predetermined bonding conditions, so that the gold thin film deposited on the back surface 1a of the semiconductor chip 1 is mounted on the chip mounting portion. Part 2
Eutectic bonding is performed with the silver plating 3 of b.

Thus, the semiconductor chip 1 and the chip mounting portion 2b are joined by the silver plating 3.

Here, at the time of pellet bonding, the lattice-shaped concave portions 3a formed in the silver plating 3 cause the silver plating 3 of the bonding portion 7 after the bonding of the semiconductor chip 1 to have a grid-like shape, as shown in FIG. The bonding is performed so that the gap 6 remains (is formed).

As a result, many voids 6 are formed in the silver plating 3.
And the semiconductor chip 1 and the chip mounting portion 2b can be joined by the silver plating 3.

Thereafter, as shown in FIG. 1, wire bonding for electrically connecting the surface electrodes of the semiconductor chip 1 and the lead portions 2c of the frame member 2a with thin metal wires 8 formed of gold or the like is performed.

Subsequently, the semiconductor chip 1 and the peripheral portion 4 including the fine metal wires 8 are resin-sealed with an epoxy-based thermosetting resin or the like, thereby forming a sealing body 5.

The recess 3a of the silver plating 3 on the outer peripheral portion of the semiconductor chip 1 is relatively largely crushed as compared with the recess 3a inside the back surface 1a of the semiconductor chip 1.
It is difficult to form the gap 6 in the outer peripheral portion, so that the sealing resin does not enter the gap 6 formed inside the back surface 1a of the semiconductor chip 1 during resin sealing.

After that, the frame member 2 a on which the semiconductor chip 1 is mounted is separated from the lead frame 2.

That is, after resin sealing, each dam bar 2d is cut, and the outer lead portion 2f of the lead portion 2c and the outer frame portion 2e are cut and separated.

Thus, the frame member 2a can be separated from the lead frame 2.

Thereafter, the outer lead portion 2f protruding from the sealing main body portion 5 is bent and formed into a desired shape.
The semiconductor device shown in FIG. 5, that is, a small chip diode can be manufactured.

The small chip diode shown in FIG. 5 has a plane size including the outer lead portion 2f (a size as viewed from above) of, for example, about 2.1 × 0.8 mm.

According to the semiconductor device of this embodiment and the method of manufacturing the same, the following operation and effect can be obtained.

That is, when the semiconductor chip 1 and the chip mounting portion 2b of the frame member 2a are joined, the silver plating 3 joining them has a large number of voids 6, so that the semiconductor chip 1 and the chip While bonding with the mounting part 2b, the degree of adhesion can be suppressed low.

That is, the semiconductor chip 1 and the chip mounting portion 2
b is joined by the silver plating 3, and the two can be divided by the voids 6 of the silver plating 3.

Therefore, when the frame member 2a is heated to a high temperature, for example, when the chip diode is mounted on the mounting substrate, and the thermal stress is applied to the semiconductor chip 1 and the chip mounting portion 2b, the gap portion of the silver plating 3 is formed. 6, the thermal stress can be reduced.

As a result, the difference in the coefficient of thermal expansion between the semiconductor chip 1 and the chip mounting portion 2b of the frame member 2a can be absorbed, thereby preventing chip cracks from being formed in the semiconductor chip 1.

It is to be noted that since chip cracks can be prevented from being formed in the semiconductor chip 1, the manufacturing margin of chip diodes can be improved. In particular, it is effective in a small chip diode as described in the present embodiment.

Furthermore, since the formation of chip cracks in the semiconductor chip 1 can be prevented, the quality of the chip diode can be improved. As described above, the quality can be improved particularly in a small chip diode.

Further, a large number of voids 6 are formed in the silver plating 3 with regularity, and the frame members 2a
Since the voids 6 are dispersedly provided on the chip mounting portion 2b, when the semiconductor chip 1 and the chip mounting portion 2b are subjected to thermal stress, the thermal stress can be dispersed.

Since the voids 6 of the silver plating 3 are provided in a lattice pattern as in the present embodiment, the thermal stress in the vertical and horizontal directions applied to the semiconductor chip 1 or the chip mounting portion 2b is substantially evenly distributed. Can be done.

As a result, even when a large thermal stress is applied, it is possible to disperse the thermal stress almost uniformly, and it is possible to prevent local concentration of the thermal stress.

Since the thermal stress can be reduced by the voids 6 of the silver plating 3, a copper alloy having a relatively large difference in thermal expansion coefficient from the semiconductor chip 1 (silicon) is used as the material of the frame member 2a. Can be used.

Thus, the frame member 2a can be formed from a copper alloy, and the cost of the frame member 2a can be reduced.

As a result, the manufacturing cost of the chip diode can be reduced.

Further, by forming the concave portion 3a in the silver plating 3 on the chip mounting portion 2b by stamping with a forming press, the concave portion 3a can be formed in the silver plating 3 in the cutting and forming step of the frame member 2a. .

Thus, a chip diode having a void 6 in the silver plating 3 can be manufactured without newly increasing the manufacturing process of the chip diode and without performing complicated processing on the back surface 1a of the semiconductor chip 1. can do.

Although the invention made by the inventor has been specifically described based on the embodiments of the present invention, the present invention is not limited to the above embodiments of the invention, and does not depart from the gist of the invention. It is needless to say that various changes can be made.

For example, in the above embodiment, the case where the semiconductor device is a small chip diode has been described. However, the chip diode is an ultra-small chip diode as in the other embodiments shown in FIG. There may be.

Here, in the ultra-small chip diode shown in FIG. 6, the mounting form of the semiconductor chip 1 is opposite to that of the chip diode described in the above embodiment, and the outer lead portion 2f is included. The plane size (the size as viewed from above) is, for example, a very small size of about 1.6 × 0.8 mm.

The ultra-small chip diode shown in FIG. 6 is manufactured by the same manufacturing method as that of the chip diode of the above-described embodiment. The chip mounting portion 2b of the member 2a is joined by silver plating 3, and a void 6 (see FIG. 2) is formed in the silver plating 3 after joining.

Here, since the ultra-small chip diode shown in FIG. 6 is smaller than the chip diode described in the above embodiment, it is possible to further increase the operation and effect obtained by the ultra-small chip diode. it can.

Further, in the above embodiment, the case where the concave portions 3a formed in the joining material (silver plating 3) are lattice-like, and the planar shape of the convex portions 3b around the concave portions 3a is square has been described. However, the planar shape of the convex portion 3b is not limited to a quadrangle, and may be circular as in the semiconductor device of another embodiment shown in FIG. 7, or may be another polygon other than the quadrangle. You may.

Further, as in the other embodiment shown in FIG. 8, the lattice arrangement by the concave portions 3a may be arranged at an angle of approximately 45 ° (may be other than 45 °) with respect to the chip mounting portion 2b. Good.

In this case, only the mounting angle of the thin plate 9 at the time of embossing is changed by 45 ° as compared with the case of the above-described embodiment, and the formation of the concave portion 3a can be performed relatively easily.

Note that the same effects as those of the semiconductor device described in the above embodiment can be obtained also in the semiconductor device shown in FIGS.

Here, in the above-described embodiment, the case where the concave portion 3a is formed by stamping of a press die has been described. However, the concave portion 3a may be formed by using a roller other than stamping.

In the above embodiment, the case where the semiconductor device is a chip diode has been described. However, the semiconductor device is not limited to a chip diode, and may be, for example, a three-pole transistor. ,
Alternatively, as in the semiconductor device according to the other embodiment shown in FIG.
It may be an FP (Quad Flat Package) or the like.

That is, in the semiconductor device, the semiconductor chip 1 is mounted on the chip mounting portion 2b of the frame member 2a, and the semiconductor device is connected to the semiconductor chip 1 by a bonding material such as silver plating 3 (see FIG. 2). As long as the bonding material has a large number of voids 6 (see FIG. 2) formed after bonding the semiconductor chip 1 to the chip mounting portion 2b, it may be other than a chip diode.

In the above embodiment, the case where the bonding material is silver plating 3 has been described. However, the bonding material may be, for example, silver paste or the like, or may be formed of silver or gold. It may be a thin film sheet member or the like.

That is, the thin film sheet member provided with a large number of holes in a dispersed manner is used as a bonding material.

In this case, when mounting (fixing) the semiconductor chip 1 on the chip mounting portion 2b of the frame member 2a, the semiconductor chip 1 is mounted (fixed) via the thin film sheet member. It is sufficient if a large number of the formed voids 6 are formed at the junction 7 between the semiconductor chip 1 and the chip mounting portion 2b, and thus, the same operation as in the case of the semiconductor device (chip diode) of the above embodiment is achieved. The effect is obtained.

[0115]

Advantageous effects obtained by typical ones of the inventions disclosed in the present application will be briefly described.
It is as follows.

(1). When the semiconductor chip and the chip mounting portion of the frame member are joined, since a large number of voids are provided in the joining material for joining the two, the two are joined by the joining material, and both are joined by the gap. It can be divided. Therefore, when thermal stress is applied to the semiconductor chip and the chip mounting portion, the thermal stress can be relaxed by the gap,
This makes it possible to absorb the difference in the coefficient of thermal expansion between the semiconductor chip and the chip mounting portion. As a result, it is possible to prevent chip cracks from being formed in the semiconductor chip.

(2). Since a chip crack can be prevented from being formed in the semiconductor chip, a manufacturing margin of the semiconductor device can be improved. In particular, it is effective in a small semiconductor device.

(3). Since the formation of chip cracks in the semiconductor chip can be prevented, the quality of the semiconductor device can be improved. In particular, the quality of a small semiconductor device can be improved.

(4). Since the voids of the bonding material are provided in a lattice pattern, the thermal stress applied to the semiconductor chip or the chip mounting portion in the vertical and horizontal directions can be substantially uniformly dispersed. As a result, even when a large thermal stress is applied, it is possible to distribute the thermal stress almost uniformly,
Local concentration of thermal stress can be prevented.

(5). Since the thermal stress can be relieved by the voids of the joining material, a copper alloy can be used as the material of the frame member. This makes it possible to reduce the cost of the frame member,
As a result, the manufacturing cost of the semiconductor device can be reduced.

(6). When silver plating is used as the joining material, by forming a recess in the silver plating on the chip mounting portion by stamping a forming press, a recess can be formed in the silver plating in the step of cutting and forming the frame member. Thus, the semiconductor device can be manufactured without newly increasing the manufacturing process of the semiconductor device and without performing complicated processing on the back surface of the semiconductor chip.

[Brief description of the drawings]

FIG. 1 is a sectional view showing an example of an embodiment of a structure of a semiconductor device according to the present invention.

FIG. 2 is an enlarged partial cross-sectional view showing an example of an embodiment of a structure of a bonded state between a semiconductor chip and a chip mounting portion in the semiconductor device of the present invention.

FIG. 3 is a partial plan view showing an example of an embodiment of a thin plate structure forming a lead frame used in the semiconductor device of the present invention.

FIGS. 4A and 4B are diagrams showing an example of an embodiment of a structure of a lattice-shaped recess formed in a bonding material on a chip mounting portion in a semiconductor device of the present invention, and FIGS. 2 is an enlarged partial plan view, and FIG. 2B is an enlarged sectional view showing an AA section of FIG.

FIG. 5 is a perspective view showing an example of an embodiment of the structure of a semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view illustrating a structure of a semiconductor device according to another embodiment of the present invention.

FIG. 7 is an enlarged partial plan view illustrating a structure of a lattice-shaped recess formed in a bonding material on a chip mounting portion in a semiconductor device according to another embodiment of the present invention.

FIG. 8 is an enlarged partial plan view showing a structure of a lattice-shaped recess formed in a bonding material on a chip mounting portion in a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a perspective view showing a partial cross section of a structure of a semiconductor device according to another embodiment of the present invention;

[Explanation of symbols]

 Reference Signs List 1 semiconductor chip 1a back surface 2 lead frame 2a frame member 2b chip mounting portion 2c lead portion 2d dam bar 2e outer frame portion 2f outer lead portion 3 silver plating (joining material) 3a concave portion 3b convex portion 4 peripheral portion 5 sealing body portion 6 gap portion 7 Joint 8 Thin metal wire 9 Thin plate

Claims (9)

[Claims] 1. A semiconductor device having a semiconductor chip mounted thereon, comprising: a frame member having a chip mounting portion for supporting the semiconductor chip; and a bonding material for bonding the semiconductor chip and the chip mounting portion. A semiconductor device, wherein when the semiconductor chip and the chip mounting portion are joined by the joining material, a large number of voids are provided in the joining material. 2. The semiconductor device according to claim 1, wherein silver plating is used as said bonding material. 3. The semiconductor device according to claim 1, wherein a large number of said voids are formed with regularity, and are provided separately on said chip mounting portion. A semiconductor device characterized by the above-mentioned. 4. The semiconductor device according to claim 1, wherein said gaps are provided in a lattice. 5. The semiconductor device according to claim 1, wherein said frame member is formed of a copper alloy. 6. The semiconductor device according to claim 1, wherein the semiconductor device is a chip diode on which the semiconductor chip is mounted. 7. A method for manufacturing a semiconductor device having a semiconductor chip mounted thereon, the method comprising: preparing a lead frame having a frame member provided with a chip mounting portion for supporting the semiconductor chip; Disposing a bonding material having a hole in the semiconductor chip or the chip mounting portion; forming a number of voids in the bonding material by the concave portion or the hole; A method of manufacturing a semiconductor device, comprising: a step of joining the chip mounting portion; and a step of separating the frame member mounting the semiconductor chip on the chip mounting portion from the lead frame. 8. A method for manufacturing a semiconductor device having a semiconductor chip mounted thereon, the method comprising: preparing a lead frame having a frame member provided with a chip mounting portion for supporting the semiconductor chip; Applying silver plating, which is a bonding material for joining the chip mounting portion, to at least the chip mounting portion of the lead frame; forming a large number of recesses in the silver plating on the chip mounting portion; Forming a large number of voids in the silver plating by the concave portion, and joining the semiconductor chip and the chip mounting portion by the silver plating; and Separating the semiconductor device from the lead frame. 9. The method of manufacturing a semiconductor device according to claim 8, wherein the recess is formed in at least the silver plating on the chip mounting portion by stamping a molding press. Method.