JPH10274968A - Signal waveform shaping circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shape the waveform of a video data signal of a p-SiTFTLCD. SOLUTION: This circuit is constituted of a delay circuit 11 delaying an input signal by four dots period, a subtraction circuit 12 subtracting this signal DL from the data signal VD, a correction amount adjustment circuit 13 amplifying amplitude of this difference signal DF fitted to the size of this amplitude, an addition/subtraction circuit 14 adding or subtracting an output from the correction amount adjustment circuit 13 and the data signal VD, a division signal forming circuit 15 dividing the data signal VD and a correction data signal RD outputted from the addition/subtraction circuit 14 to four signals of a 1/4 frequency and a multiplication circuit 18 switch outputting the divided data signals and correction data signals at the prescribed timing. Then, the data signal VD is divided to four signals, and rise and fall edge parts are emphasized to be waveform shaped.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a signal waveform shaping circuit and a drive circuit of a display device having the signal waveform shaping circuit.

[0002]

2. Description of the Related Art In recent years, televisions and VTRs (video ta
Display devices are being actively developed due to the spread of pe recorders, computers, and car navigation systems. In particular, a liquid crystal display device using a liquid crystal as a light modulation member, that is, an LCD is advantageous in terms of small size, thinness, low power consumption, and the like, and is widely used in AV equipment and OA equipment. Hereinafter, an LCD will be described as a display device.

FIG. 11 is a block diagram showing a configuration of a conventional LCD module. The matrix circuit on the left side of the figure is L
The gate lines (G
L) and a drain line (DL) as a signal line are arranged vertically and horizontally and intersect, and a field-effect thin film transistor or TFT (SE) is formed at each intersection. Each TFT (SE) has a liquid crystal capacitance (LC) and an auxiliary capacitance (S
C) are connected and formed in parallel with each other. These TFT
(SE), gate line (GL), drain line (D
L), one electrode of the storage capacitor (SC), and one electrode of the liquid crystal capacitor (LC) are formed on one substrate, and the other electrode of the liquid crystal capacitor is formed integrally with the other substrate. These two
Liquid crystal is interposed between the two substrates, and forms a dielectric layer of a liquid crystal capacitance (LC). The gate line (GL) is mainly driven by a gate driver (GD) composed of a shift register, and the drain line (DL) is mainly driven by a drain driver (DD) composed of a shift register, a sampling circuit and, if necessary, a hold circuit. Is done.

The right side of the figure is a controller. A composite video signal received from the outside is input to a video interface circuit (VDINT) that performs color demodulation, luminance correction, and the like, where an original image signal is created and supplied to a drain driver (DD). The composite video signal is also input to a sync separation circuit (SYN) to extract vertical and horizontal sync signals. In the sync separation circuit (SYN), a horizontal sync pulse and a vertical sync pulse are created, and the horizontal sync pulse is further input to a phase comparator (PD). The phase comparator (PD) forms a closed loop together with a voltage controlled oscillator (VCO) and a low-pass filter (LPF), and a well-known PL.
An L (phase locked loop) circuit is configured. The VCO transmission clock whose phase is adjusted by the synchronization pulse and controlled to a stable transmission frequency is input to a horizontal timing control unit (HCD) including a horizontal counter and a horizontal decoder. Here, the VCO oscillation clock is divided and counted, a horizontal clock pulse and a horizontal start pulse are created and supplied to a drain driver (DD), and a vertical clock pulse is created and sent to a gate driver (GD). Supplied. Horizontal timing controller (H
The clock pulse of CD) is further supplied to a vertical timing control unit (VCD) including a vertical counter and a vertical decoder, and is divided to generate a vertical start pulse, a polarity inversion signal, and the like. The vertical synchronizing pulse is supplied to a vertical timing controller (VCD), and is synchronized with the original image signal by resetting a counter. The vertical start pulse is supplied to a gate driver (GD).

As described above, the PLL oscillation clock phase-controlled by the synchronization signal is frequency-divided by the horizontal counter and the vertical counter to generate a clock pulse synchronized with one horizontal period or one vertical period and each start pulse. . The gate driver generates a gate line (GL) for each horizontal period obtained by dividing one vertical period by the number of scanning lines.
Are sequentially selected and scanned to apply H level. On the other hand, in the drain driver (DD), an original image signal in which pixel signal voltages allocated to respective pixels are arranged in series is supplied from a video interface (VDINT). Then, the pixel signal voltage is sampled from the original image signal for each period obtained by further dividing one horizontal period by the number of signal lines. In some cases, the pixel signal voltage is temporarily held in a hold capacitor until all data for one line is collected. Supply to the drain line (DL). At this time, the TFT (S) on the gate line (GL) selected in synchronization with one horizontal period
E) are all turned on, and a voltage is applied to each liquid crystal capacitance (LC). By sequentially performing such work for one vertical period also for all scanning lines, a screen for one frame is created, and by repeating such work, rewriting for all pixels is continued.
The video is displayed.

Recently, a pixel switching TFT (SE) has been developed by using a technique of forming polycrystalline silicon (p-Si) having a mobility of several hundred cm 2 / V · s on a transparent substrate. In addition, by forming N-ch and P-ch TFTs to form a CMOS, a gate driver (GD) and a drain driver (D
D) is also fabricated on the same substrate, and the driver (GD,
DD) part with built-in drive circuit built in LCD panel
CDs are being developed.

In the drive circuit built-in type, all transistor elements in all LCD panels are formed by p-Si TFTs. The operation speed of the p-Si TFT is sufficient for switching of the pixel portion, but the driver (GD,
It is somewhat insufficient to constitute the DD) section. That is, p-
Although a driver circuit can be formed by the SiTFT, it cannot be said that the operation speed is sufficient. Therefore, a device has been devised in which the original image signal is divided into a plurality of signals and supplied at the lowest possible frequency.

FIG. 12 shows a configuration example of a drain driver (DD) of a p-Si TFT LCD. The upper part has a shift register (S / H), the middle part has video data lines (VL1, 2, 3, 4) to which original picture signals have been supplied, and the lower part has a sampling transfer gate (SW). Here, the dot sequential driving is mentioned. That is, the ON / OFF of the sampling gate (SW) is controlled by the output of each stage from the shift register (S / R), and each column is converted from the original image data supplied to each video data line (VL1, 2, 3, 4). Is selected and transmitted to each drain line (DL).

FIG. 13 shows original image data VDL 1, 2, 3,
FIG. 4 is a timing chart showing a relationship between the pixel data PXD and pixel data PXD. In this example, the image data is divided into four, and pixel data of every four pixels is serially supplied to each video data line (VL1, 2, 3, 4) as an analog signal of 1/4 frequency. That is, the same pixel data is supplied for four dot periods. Since the sampling period is the last one dot period of these four dot periods, the delay of the original image signal is recovered at the time of sampling, and an accurate pixel signal voltage is sampled.

[0010]

The original image signal is distorted in waveform by an integration circuit including a parasitic resistance and a parasitic capacitance in a drain driver (DD). Such distortion causes the amplitude of the pixel signal voltage to be reduced. This causes a problem that the luminance or the contrast ratio decreases. In particular, it has become remarkable with an end portion far from the supply end of the original image signal, a central portion of the screen, and a larger substrate.

Such a problem can be solved to some extent by dividing the original picture signal into a plurality of parts and lowering the frequency as shown in FIGS. Further, when the difference between the previous pixel signal voltage and the subsequent pixel signal voltage is large,
There is a problem that the influence of the previous pixel signal voltage on the subsequent pixel signal voltage is greater than when the difference between the previous pixel signal voltage and the subsequent pixel signal voltage is small. In other words, if the difference between the previous pixel signal voltage and the subsequent pixel signal voltage is large, it takes a long time to change the original image signal voltage, so that the subsequent pixel signal voltage changes according to the level of the previous pixel signal voltage. I will.

In the case of four divisions, the display of a certain column affects the column after four columns. In the dot sequential driving, furthermore, after sampling, that is, the parasitic resistance and the parasitic capacitance of the drain line (DL), and Since the signal is also distorted by the integration circuit including the TFT (SE), the liquid crystal capacitor (LC), and the auxiliary capacitor (SC), the distortion of the data finally written to the pixel cannot be ignored. If the display information at a certain position also affects a distant display position as described above, the entire display screen is visually recognized as a ghost, and the display quality is deteriorated.

Although such a ghost can be solved by increasing the number of divisions, the processing of the original image signal and the complexity of the drain driver (DD) are caused, which is not preferable in terms of cost.

[0014]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has been made in view of the above-mentioned problems, and a signal waveform shaping circuit for shaping the waveform of an output signal by emphasizing the rising or falling edge of the waveform of an input signal. A delay means for delaying the input signal by n (n is a natural number) cycle periods;
Subtraction means for taking a difference between the delay signal output from the delay means and the input signal; and a difference signal output from the subtraction means being input, the amplitude of the difference signal being adjusted in accordance with the amplitude of the difference signal. Amplitude amplifying means for amplifying the width; dividing means for dividing the input signal and the correction signal output from the amplitude amplifying means into n signals of n times cycle including information of n cycles each; Multiplying means for controlling the multiplication of each of the n divided input signals by the divided correction signal, and the n divided input signals having the desired width amplified amplitude of a predetermined position period in each cycle period of the divided input signal. Is generated.

[0015] Thus, since the optimum correction is performed in accordance with the magnitude of the amplitude difference before and after the rise or fall, distortion due to signal delay is eliminated, and a signal having a waveform closer to the original signal is obtained. In addition, since the waveform shaping is performed on the low frequency information signal divided into a plurality including the information for each of a plurality of cycles, the room for recovering the signal delay by the low frequency division is expanded and the signal processing itself is simplified. Was done.

[0016]

FIG. 1 is a block diagram of a signal waveform shaping circuit according to an embodiment of the present invention. A delay circuit (1) for delaying the data signal VD to be shaped by, for example, four periods, a subtraction circuit (2) for subtracting the delay signal DL output from the delay circuit (1) from the data signal VD, and a subtraction circuit (2)
An amplitude amplifying circuit (3) for amplifying the delay signal DL with an amplification factor corresponding to the amplitude of the differential signal DF output from the FD-D, and converting the data signal VD to a 1/4 frequency signal having information for every four cycles.
A data signal dividing circuit (4) that divides the signal into two signals vd1, 2, 3, and 4, and a correction signal RD output from the amplitude amplifying circuit (3) is divided into four like the data signal dividing circuit (3). A correction signal dividing circuit (5), a data signal dividing circuit (4), and a correction signal dividing circuit (5).
By switching and selecting the divided data signals vd1, 2, 3, and 4 and the divided correction signals rd1, 2, 3, and 4 having the same phase, respectively, based on a clock having the same frequency as the data signal VD or a frequency-divided clock thereof. , Each of which outputs four divided and shaped signals VDL1, 2, 3, and 4 whose amplitude is amplified in a part of one cycle of the data signal.

This signal waveform shaping circuit is employed, for example, in a p-Si TFT LCD of a plurality of divided / dot sequential driving.
In the video interface (VDINT) of FIG.
Each video data signal is divided into four for each of G and B, and waveform shaping is performed. FIG. 2 shows that the same video data signal VD supplied to the drain driver (DD) has a relatively small amplitude difference before and after the rising (or falling), so that the video data line (VL) in the driver can be used. This is a comparison of actual signal waveforms.

FIG. 2A shows the waveform of one divided video data signal vd divided by four in the data signal dividing circuit (4), and FIG. 2B shows each video data output from the multiplying circuit (6). The signal VDL, that is, the signal waveform shaped according to the present invention, and FIG. 2C is the actual output waveform whose signal waveform is delayed by the drain driver (DD). FIG. 2D shows a conventional case where the waveform of the video data signal VD is not shaped, and FIG. 2E shows an output waveform at that time.
FIG. 2F shows a comparative example in which waveform shaping of the video data signal is performed with a fixed correction amount, and FIG. 2G shows an output waveform at that time.

2 (b) and 2 (c), the waveform is shaped so that the edge of the rising (falling) portion is optimally emphasized, so that even if the signal is delayed, the distortion is suppressed to a small level. I have. In FIGS. 2D and 2E, waveform shaping is not performed. However, since the width of change before and after rising (falling) is small, the frequency of each video data line is reduced by a plurality of divided structures, Since there is room for recovery of the delay, there is no effect at the time of sampling.

However, as shown in FIGS. 2F and 2G, the difference before and after the rising (falling) is small.
Due to a constant correction, in this case a correction that is too large, the effect of the emphasized edge remains until the sampling, and it can be seen that, in the end, the previous pixel signal voltage affects the subsequent pixel signal voltage. . FIG. 3 shows the case where the same video data signal supplied to the drain driver (DD) has a relatively large amplitude difference before and after the rising (or falling) and the actual video data line (VL) in the driver. Are compared.

The signal processing for each waveform in FIG. 3 is the same as in FIG. However, in FIG. 2A, the amplitude of the video data signal is large, and accordingly, the correction amount in FIG. 3B is larger than that in FIG. For this reason, as can be seen from FIG. 3C, even if the change width of the video data signal is large, the correction amount is sufficiently large in accordance with the change amount, so that the influence of the signal delay disappears during sampling. ing.

In FIGS. 3D and 3E, since the amount of change in the video data signal is large, the signal delay cannot be recovered in time by merely lowering the frequency, and the sampling time is affected. In FIGS. 3F and 3G, since the difference before and after the rise (fall) is large, a certain correction, in this case,
Due to the correction being too small, the effect of the emphasized edge is insufficient, and again the previous pixel signal voltage affects the subsequent pixel signal voltage during sampling.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, an example in which the present invention is applied to a p-Si TFT LCD will be described in detail. FIG. 4 is a partial block diagram of the video interface circuit (VDINT) of FIG. R, G, B data signals R, G, B color demodulated
Are respectively connected to a data signal dividing / composing device of the present invention via a contrast adjusting circuit (50) and a gamma correcting circuit (51).
The signal is sent to the waveform shaping circuit (52). The data signal division / waveform shaping circuit (52) includes 1/4
4 frequency divided video data signals VDL1, 2, 3, 4
Is created. These divided video data signals VDL1,
In 2, 3, and 4, a predetermined polarity alignment for dot inversion is performed by a D / A converter (53) and an analog switch circuit (54), and a predetermined current is provided in a buffer circuit (55). R, G, B video data signals VR, VG, V
B is supplied to a drain driver (DD).

FIG. 5 is a detailed block diagram of the data signal dividing / shaping circuit (52) of the present invention shown in FIG. The data signal VD has four flip-flops (1
The signal is delayed by 4 dot periods in the delay circuit (11) composed of 9) and sent to the subtraction circuit (12). Subtraction circuit (12)
Then, the difference between the data signal VD and the data signal DL four dot periods before sent from the delay circuit (11) is calculated and sent to the correction amount adjustment circuit (13) via the flop flop (19). The correction amount adjustment circuit (13) holds correction data in a ROM, and a subtraction circuit (1).
The address is controlled by the difference data DF output from 2), and correction data corresponding to the difference is output. The correction data is sent to an addition / subtraction circuit (14), where addition or subtraction is performed on the data signal based on the polarity thereof, and the correction data signal R whose data signal amplitude is amplified.
D is created.

These data signals VD and
The corrected data signal RD whose amplitude has been amplified is divided into four by a division circuit (16) (17) and a multiplication circuit (18).
Four video data signals VDL sent to two divided data signal creation circuits (15) and having data for every four dots
1, 2, 3, and 4 are created. These video data signals VDL1,2,3,4 are in phase and at the same time each video data line (VL1,
2, 3, 4).

FIG. 6 is a more detailed block diagram of the divided data signal generating circuit (15) shown in FIG. Two DFs forming a division circuit (16) for the data signal VD
F (21) and (22), and two D-FFs (23) and (24) constituting a division circuit (17) for the correction data signal;
Further, it comprises two AND gates (25) and (26) and an OR gate (27) constituting the multiplication circuit (18).

Further, a horizontal frequency synchronizing pulse HSYNC and a dot clock DCK are supplied to the clock frequency dividing circuit (28), so that the frequency of the dot clock is frequency-divided by 、 and the phase is different by 90 °. Four-duty divided clocks CK1, 2, 3, and 4 are created. Three of the four divided data signal generation circuits (15) have the same configuration as in FIG. 6, and among them, the first divided data signal generation circuit (15) has the clock CK1 and the clock CK1 supplied from the clock frequency dividing circuit (28). CK4 is supplied. That is, the clock CK1 is supplied to the clock input of the D-FFs (21) and (23), and the clock CK4 is supplied to the D-FFs (22) and (24).

The data signal VD is applied to the D-FF (21).
The Q output (LT1) is input to the next D-FF (2
D is input to 2), and its Q output (vd1) is supplied to one input terminal of an AND gate (25). The correction data signal RD is D-input to a D-FF (23), its Q output (LT1) is D-input to the next D-FF (24), and its Q output (rd1) is input to an AND gate (26). It is supplied to one input end.

The other input terminal of each of the AND gates (25) and (26) has a selected clock SE based on the clock CK4.
L, for example, an inverted clock and a non-inverted clock of the clock CK4 are supplied. The outputs of these AND gates (25) and (26) are supplied to an OR gate (27) and output as a divided and shaped video data signal VDL1.

Instead of the clock CK1, clocks CK2 and CK3 having different phases are supplied to the second and third divided data signal generating circuits (15) to generate divided and shaped video data signals VDL2 and VDL3, respectively. Is done. FIG. 7 is a block diagram of the remaining one of the divided data signal generation circuits (15). A D-FF (21) forming a dividing circuit (16) for the data signal VD, a D-FF forming a dividing circuit (17) for the correction data signal, and
The two AND gates (2
5) Consists of (26) and OA gate (27). D-FF
(21) The clock input of (23) is supplied with the clock CK4.

FIGS. 8 and 9 are timing charts showing how the data signal VD and the correction data signal RD are divided and divided by such dividing circuits (16) and (17), respectively. FIG. 10 shows these divided data signals v
d1, 2, 3, 4 and the divided correction data signals rd1, 2,
From the three and four, four divided and shaped video data signals V
FIG. 4 is a timing chart showing how DLs 1, 2, 3, and 4 are created.

The data at a predetermined position of the data signal VD before the division is compared, and as a result, a corrected data signal RD that is optimally corrected is created. These data signal VD and the corrected data signal RD are parallelized. Is similarly divided into four.
Then, the divided data are multiplied in correspondence with each other, switched to the correction data RDn in the first 周期 period of one cycle period, and output, and similar to the original data VDn in the remaining ／ period period. By performing the alternate output, waveform shaping is performed in such a manner that the amplitude immediately after the rising (falling) of the divided data signal vd is amplified.

At this time, since one cycle period is a four-dot period, data correction of 1: 3 can be performed by using the divided clock CK4 as it is. Alternatively, for example 1:
When the correction of 1 is performed, the clock dividing circuit (28) creates a 1/2 duty selection clock, and the clock selection circuit (29) switches to this.

[0034]

As is apparent from the above description, the original picture signal to be supplied to the display device or the like is divided into a plurality of pieces including information of a plurality of cycles, and the rising of the divided original picture signal and Correction according to the amount of change before and after the fall was performed, and signal waveform shaping optimal for the display device became possible. That is, in order to match the speed of the drive circuit of the display device, the original image signal to be supplied is divided to lower the frequency, and at the same time, the edges of the rising and falling portions of the divided original image signal are emphasized, so that it is more effective. Waveform shaping was realized.

Further, problems such as complication of signal processing due to an increase in the number of divisions, an increase in cost, and occurrence of a signal error due to an increase in a correction amount for obtaining a sufficient shaping effect can be suppressed. Was.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a signal waveform shaping circuit according to an embodiment of the present invention.

FIG. 2 is a waveform chart showing the operation and effect of the present invention.

FIG. 3 is a waveform chart showing the operation and effect of the present invention.

FIG. 4 is a configuration diagram of a controller unit of the LCD according to the embodiment of the present invention.

FIG. 5 is a configuration diagram of a signal waveform shaping circuit according to an embodiment of the present invention.

FIG. 6 is a configuration diagram of a divided signal generation circuit according to an embodiment of the present invention.

FIG. 7 is a configuration diagram of a divided signal generation circuit according to an embodiment of the present invention.

FIG. 8 is a timing chart of the divided signal generation circuit.

FIG. 9 is a timing chart of the divided signal generation circuit.

FIG. 10 is a timing chart of the multiplication circuit.

FIG. 11 is a configuration diagram of a conventional LCD module.

FIG. 12 is a configuration diagram of a drain driver.

FIG. 13 is a waveform diagram of the drain driver.

[Explanation of symbols]

 Reference Signs List 1,11 delay circuit 2,12 subtraction circuit 3 amplitude amplification circuit 4,5 division circuit 6 multiplication circuit 13 correction amount adjustment circuit 14 addition / subtraction circuit 15 division signal generation circuit 16,17 division circuit 18 multiplication circuit 19 flop flop

Claims (2)

[Claims] 1. A signal waveform shaping circuit for shaping a waveform of an output signal by emphasizing a rising edge and / or a falling edge of the waveform of the input signal, wherein the input signal is delayed by n (n is a natural number) cycle periods. Delay means, subtraction means for taking a difference between the delay signal output from the delay means and the input signal, and a difference signal output from the subtraction means, wherein the difference signal is adjusted according to the amplitude of the difference signal Amplifying means for amplifying the amplitude of the input signal by a desired width, and signal division for dividing the input signal and the correction signal output from the amplitude amplifying means into n signals of n times cycle including information of n cycles each. Means for controlling the multiplication of each of the n divided input signals and the divided correction signal, wherein the amplitude of the divided input signal in a predetermined position period within each cycle period is Waveform shaping circuit, characterized in that to create the desired width of n shaping signal amplified. 2. The signal dividing means includes n divided signal generating circuits, and receives first to n-th divided clocks obtained by dividing a reference clock of the input signal by n and sequentially shifting by 1 / n period. The k (k is a natural number smaller than n) divided signal generation circuit latches the input signal as data and uses a k-th divided clock as a clock input. A k-th input signal dividing circuit for latching the Q output data and receiving the n-th divided clock as a clock input, and outputting the k-th divided input signal; A first latch circuit that latches data and inputs the k-th divided clock as a clock input; and a data latch of a Q output of the first latch circuit,
A second latch circuit that receives the n-th divided clock as a clock input, and outputs a k-th divided correction signal.
Wherein the n-th divided signal generation circuit has a latch circuit for latching the input signal and inputting the n-th divided clock as a clock input, and the n-th divided input circuit. An n-th input signal dividing circuit that outputs a signal; a latch circuit that latches the correction signal as data and receives the n-th divided clock as a clock input; and outputs an n-th divided correction signal. 2. The signal waveform shaping circuit according to claim 1, further comprising a correction signal dividing circuit.