JPH10270554A - Semiconductor device and manufacture thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device and the manufacturing method thereof for preventing the deffective connection of wirings. SOLUTION: When the alloy comprising the laminated layer of Ti and TiN is deposited by applying heat treatment on a second interlayer insulating film 12, the discharging of the gas (HF and H2 O), which is formed from the moisture absorbed in the second interlayer insulating film 12 by the heat of the deposition, from the second interlayer insulating film 12 is suppressed. A first interlayer insulating film 16 and a third interlayer insulating film 17 suppress the diffusion of fluorine into the interface of a first wiring 11 and a second wiring 15 from the inside of the second interlayer insulating film 12. By the suppression of the discharging of the gas and the diffusion of fluorine, the separation of the second wiring 15 from the third interlayer insulating film 17 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device, which prevent connection failure of wiring.

[0002]

2. Description of the Related Art A conventional semiconductor device and its manufacturing method will be described with reference to FIG. An isolation oxide film 2 is formed on a part of the surface of a silicon semiconductor substrate 1. Next, a gate oxide film 3, a polycrystalline silicon film 4, and a silicon oxide film 5 are formed. Next, first implantation of impurity ions is performed using the gate oxide film 3, the polycrystalline silicon film 4, and the silicon oxide film 5 as a mask. Next, sidewalls 7 are formed on the side walls of the gate oxide film 3, the polycrystalline silicon film 4 and the silicon oxide film 5.
To form Next, impurity diffusion layers 6 are formed by performing a second implantation of impurity ions using the gate oxide film 3, the polycrystalline silicon film 4, the silicon oxide film 5, and the sidewalls 7 as a mask.

Next, a BPSG film 8 having a flat surface is formed. Next, a required portion of the BPSG film 8 is opened as a first connection hole. Next, Ti and T are formed by sputtering.
Alloy (first barrier metal) consisting of iN laminated
It is deposited on the surface of the SG film 8 (including the surface in the first connection hole). Next, a tungsten (W) plug 10 is formed in the first connection hole by the CVD method and the RIE method. next,
For example, an aluminum copper alloy film is deposited on the first barrier metal surface and the exposed plug 10 surface by a sputtering method. Then, the first wiring 11 (wiring layer) is formed by patterning the first barrier metal and the aluminum copper alloy film by photolithography and RIE.

Next, an interlayer insulating film 12 having a flat surface is formed so as to cover the main surface of the silicon semiconductor substrate 1. Next, a required portion of the interlayer insulating film 12 is opened as a second connection hole. Next, Ti and TiN are formed by sputtering.
(A second barrier metal) is deposited on the surface of the interlayer insulating film 12 (including the surface in the second connection hole). Next, a tungsten (W) plug 14 is formed in the second connection hole by the CVD method and the RIE method. next,
For example, an aluminum copper alloy film is deposited on the surface of the second barrier metal and the exposed surface of the plug 14 by a sputtering method. Then, the second wiring 15 (wiring layer) is formed by patterning the second barrier metal and the aluminum copper alloy film by photolithography and RIE.

In recent years, speeding up of LSI has been achieved by miniaturization. However, recently, not only miniaturization but also 1
In a state-of-the-art logic device having a processing speed exceeding 00 MHz, attention has been paid to the reduction of the parasitic capacitance between the first wiring 11 and the second wiring 15 for speeding up. To reduce this parasitic capacitance, the first wiring 11 and the second wiring 1
It is necessary to lower the dielectric constant of the interlayer insulating film 12 interposed between the layers 5. Therefore, there has conventionally been a method of lowering the dielectric constant by including fluorine in the interlayer insulating film 12.

[0006]

However, when fluorine is contained in the interlayer insulating film 12, the following problems occur. Since the interlayer insulating film 12 is exposed, it takes in moisture and absorbs moisture. Then, the heat in depositing the second barrier metal facilitates the diffusion of fluorine in the interlayer insulating film 12. Therefore, fluorine diffuses from the inside of interlayer insulating film 12 to the outside. In addition, moisture absorbed in the interlayer insulating film 12 becomes gas (HF or H ₂ O) and is released from the interlayer insulating film 12 by heat generated when the second barrier metal is deposited. Due to the diffusion of fluorine and the release of gas, the first wiring 11 and the second wiring 15 (including the plug 14) are separated from the interlayer insulating film 12, so that the connection of the first wiring 11 and the second wiring 15 is performed. There is a problem that defects occur.
This problem causes a decrease in the yield of the semiconductor device and a decrease in the reliability.

SUMMARY OF THE INVENTION The present invention has been made to solve this problem, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same, which prevent poor connection of wiring.

[0008]

Means for Solving the Problems According to a first aspect of the present invention, there is provided a method for forming a first wiring on a base layer, the step of covering the surface of the first wiring, and forming the first wiring thinner on the outside. Forming an interlayer insulating film containing fluorine at a high concentration by applying heat treatment to the interlayer insulating film to release gas from the interlayer insulating film; and subjecting the interlayer insulating film to heat treatment. Forming a second wiring on the surface of the substrate.

[0009] In the means for solving problems according to claim 2 of the present invention, the step of forming the interlayer insulating film includes the steps of: forming a first interlayer insulating film covering a surface of the first wiring; Forming a second interlayer insulating film containing fluorine and covering the surface of the second interlayer insulating film, and forming a third interlayer insulating film covering the surface of the second interlayer insulating film.

In the means for solving problems according to claim 3 of the present invention, the step of forming the interlayer insulating film includes a step of forming a first interlayer insulating film containing fluorine which covers a surface of the first wiring; Forming a second interlayer insulating film containing fluorine covering the surface of the first interlayer insulating film, and forming a third interlayer insulating film covering the surface of the second interlayer insulating film; Prepare.

In a fourth aspect of the present invention, the temperature of the heat treatment is equal to or higher than a maximum temperature at the time of forming the second wiring.

In the means for solving problems according to claim 5 of the present invention, the temperature of the heat treatment is 400 ° C. or more.

[0013] The problem solving means according to claim 6 of the present invention comprises:
A first wiring formed on the base layer, an interlayer insulating film formed to cover the surface of the first wiring and containing fluorine having a thin concentration on the outside and a high concentration on the inside, and And a second wiring formed on the substrate, wherein the interlayer insulating film is subjected to a heat treatment for releasing gas.

[0014]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment. FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention, and FIG. 2 is a cross-sectional view illustrating a method for manufacturing the semiconductor device. First, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described. Referring to FIG. 2, isolation oxide film 2 having a thickness of about 300 nm to 800 nm is formed on a portion of the surface of silicon semiconductor substrate 1 by a local oxidation method.

Next, a lamination composed of a gate oxide film, a polycrystalline silicon film and a silicon oxide film is formed as follows on a portion where the surface of the silicon semiconductor substrate 1 is exposed. That is, a gate oxide film having a thickness of about 5 nm to 30 nm is formed by a thermal oxidation method. Next, a polycrystalline silicon film is deposited and formed on the surface of the gate oxide film by a vapor deposition method. The polycrystalline silicon film contains phosphorus and arsenic. Next, a silicon oxide film is deposited and formed on the surface of the polycrystalline silicon film by a vapor deposition method.

Next, the lamination is formed into a gate oxide film 3, a polycrystalline silicon film 4 and a silicon oxide film 5 shown in FIG. 2 by photolithography and RIE. Next, first implantation of impurity ions is performed using the gate oxide film 3, the polycrystalline silicon film 4, and the silicon oxide film 5 as a mask.

Next, about 50 nm-3
A silicon oxide film having a thickness of about 00 nm is formed. Next, the silicon oxide film is etched by the RIE method to form sidewalls 7 on the side walls of the gate oxide film 3, the polycrystalline silicon film 4, and the silicon oxide film 5.

Next, impurity diffusion layers 6 are formed by performing a second implantation of impurity ions using the gate oxide film 3, the polycrystalline silicon film 4, the silicon oxide film 5, and the sidewalls 7 as a mask. The impurity diffusion layer 6 has a portion where impurities are relatively dense and a portion where impurities are relatively thin due to the first and second implantation of impurity ions.

Gate oxide film 3, polycrystalline silicon film 4, silicon oxide film 5, side wall 7, and impurity diffusion layer 6 constitute a MOS transistor. Further, a gate oxide film 3, a polycrystalline silicon film 4, a silicon oxide film 5, and a sidewall 7 are also formed on the isolation oxide film 2.

Next, a BPSG film is deposited and formed by a vapor deposition method so as to cover the main surface of the silicon semiconductor substrate 1. Next, about 800 ° to 1 ° with respect to the BPSG film.
By performing a heat treatment at a temperature of 000 degrees, a BPSG film 8 (first interlayer insulating film) having a flat surface is formed as a base layer as shown in FIG.

Next, photolithography and RIE
A required portion of the BPSG film 8 is formed as a first connection hole by a method. Next, an impurity is injected into the first connection hole.
Next, heat treatment is performed to activate the impurities. Next, W
A tungsten film is deposited and formed by a vapor deposition method using F6 or the like as a material. Next, the plug 10 is formed in the first connection hole by etching by the RIE method.

Next, for example, an aluminum copper alloy film is deposited on the surface of the BPSG film 8 and the exposed surface of the plug 10 by a sputtering method. Then, the first wiring 11 (wiring layer) is formed by patterning the aluminum copper alloy film by photolithography and RIE.

Next, referring to FIG. 1, a second interlayer insulating film which is formed so as to cover the surface of the first wiring 11 and which contains thin fluorine on the outside and a high concentration on the inside is formed, for example, as follows. I do. That is, the first interlayer insulating film 16 having a thickness of about 500 Å is deposited and formed so as to cover the main surface of the silicon semiconductor substrate 1. The first interlayer insulating film 16 is a nitride film. Next, an oxide film containing fluorine covering the surface of the first interlayer insulating film 16 is formed to a thickness of about 20,000.
It is formed by deposition so as to have a thickness of about Å. Next, the oxide film is subjected to the CMP method as shown in FIG.
As shown in FIG. 5, a second interlayer insulating film 12 having a flat surface as an oxide film is formed. Next, a third interlayer insulating film 17 covering the surface of the second interlayer insulating film 12 is deposited and formed. Third
The interlayer insulating film 17 is a nitride film. First interlayer insulating film 16, second interlayer insulating film 12, and third interlayer insulating film 17
Constitutes a second interlayer insulating film. At this point, the concentration of fluorine in the second interlayer insulating film is thin outside (0% at the interface between the second interlayer insulating film and the first wiring 11 and the second wiring 15) and high inside. The surface of the second interlayer insulating film, that is, the surface of the third interlayer insulating film 17 is formed flat.

Next, the gas is released from the second interlayer insulating film by performing a heat treatment for releasing the gas from the second interlayer insulating film.

Next, photolithography and RIE
A required portion of the second interlayer insulating film 12 is formed as a second connection hole by a method. Next, an alloy (barrier metal) composed of a stack of Ti and TiN is deposited by a sputtering method. Next, a tungsten (W) plug 14 is formed in the second connection hole by the CVD method and the RIE method. The deposition temperature in the CVD method is about 400 to 450 degrees.

Next, for example, an aluminum copper alloy film is deposited and formed on the barrier metal surface and the exposed plug 14 surface by a sputtering method. And
The second wiring 15 (wiring layer) is formed by patterning the barrier metal and the aluminum copper alloy film by photolithography and RIE. Second
Of the plug 14, the first wiring 11, and the plug 1
0, it is electrically connected to the impurity diffusion layer 6.

Next, the heat treatment for releasing gas from the second interlayer insulating film will be described in detail. First, by performing this heat treatment, fluorine diffuses from the second interlayer insulating film 12 into the first interlayer insulating film 16 and the third interlayer insulating film 17. Therefore, the amount of fluorine in the second interlayer insulating film 12 decreases. Since the amount of fluorine diffusing into the surface of the second connection hole 13 of the second interlayer insulating film 12 is also reduced, peeling of the plug 14 from the second interlayer insulating film 12 is suppressed.

FIG. 3 is a graph showing an example of the concentration of fluorine in the third interlayer insulating film 17 and the second interlayer insulating film 12. In FIG. 3, the vertical axis represents the concentration of fluorine, the horizontal axis represents the depth from the surface of the third interlayer insulating film 17, and the curve 101 represents the case where no heat treatment is performed and the second interlayer insulating film 12 does not absorb moisture. A curve 102 indicates a case where the heat treatment (at 450 ° C. for 15 minutes) is performed and the second interlayer insulating film 12 does not absorb moisture, and a curve 103 indicates a case where the heat treatment is not performed and the second interlayer insulating film 12
Curve 104 shows a heat treatment (450 ° C.)
For 15 minutes) and the second interlayer insulating film 12 absorbs moisture. The third interlayer insulating film 17 extends from the origin to about 0.3 μm on the horizontal axis, and the second interlayer insulating film 12 is located deeper than this. As shown in FIG. 3, when moisture is absorbed, the diffusion of fluorine tends to be larger than when moisture is not absorbed. When heat treatment is performed, the diffusion of fluorine tends to be larger than when heat treatment is not performed.

Therefore, when the second interlayer insulating film 12 absorbs moisture and is subjected to a heat treatment, the first interlayer insulating film 16 and the third interlayer insulating film are removed from within the second interlayer insulating film 12. 17, the first wiring 1
There is a possibility that the first and second wirings 15 may be separated from the second interlayer insulating film. To prevent this peeling,
The thicknesses of the first interlayer insulating film 16 and the third interlayer insulating film 17 need to be sufficiently large.

FIG. 4 shows the distribution of atoms in the second wiring 15 and the second interlayer insulating film 12 when the second wiring 15 is peeled off from the second interlayer insulating film 12 in a conventional semiconductor device. 6 is a graph showing an example of the above. In FIG. 4, the vertical axis represents the distribution intensity, the horizontal axis represents the depth from the surface of the alloy (barrier metal) made of a laminate of Ti and TiN in the second wiring 15,
1 is a distribution of nitrogen (N), 202 is a distribution of fluorine (F),
Numeral 203 indicates the distribution of titanium (Ti). More specifically, the horizontal axis indicates that 500 Å from the origin is TiN, 50 Å.
Ti from 0 Å to 700 Å is Ti, and a portion deeper than 700 Å is SiO _{2 as} the second interlayer insulating film 12. At this time, T
The concentration of fluorine at the interface between i and the second interlayer insulating film 12 is
Atomic percentage was 4.1%.

Therefore, in consideration of FIG. 4, in order to prevent the first wiring 11 and the second wiring 15 from being separated from the second interlayer insulating film, the first wiring 11 and the third wiring
Concentration in the interlayer insulating film 17 is 4.0% in atomic percentage.
It is desirable to make it less than. The film thickness of the first interlayer insulating film 16 and the third interlayer insulating film 17 that can make the concentration of fluorine in an atomic percentage less than 4.0% is 1000
Angstroms or more is enough.

Further, by this heat treatment, the moisture absorbed in the second interlayer insulating film 12 becomes gas (HF or H ₂ O) and is released from the second interlayer insulating film 12. Therefore, the moisture absorbed in the second interlayer insulating film 12 becomes gas (HF or H ₂ O) by the heat generated when depositing the alloy composed of the stacked layers of Ti and TiN, and the second interlayer insulating film 12
Is suppressed. Further, the third interlayer insulating film 17 also has an action of preventing the second interlayer insulating film 12 from absorbing moisture.

The temperature of the heat treatment is preferably
It is desirable that the temperature be equal to or higher than the maximum temperature when forming the second wiring 17. If the heat treatment is performed at a temperature lower than the temperature at which the second wiring 15 is formed, the second interlayer insulating film 12
When the second wiring 17 is formed, the moisture remaining in the second interlayer insulating film 12 becomes gas (HF or H ₂ O) to form a second interlayer insulating film. This is because they are released from No. 12. Further, the temperature of the heat treatment needs to be lower than the temperature at which the first wiring 11 or the second wiring 15 melts. In addition, since the maximum temperature at the time of forming the second wiring 15 is generally about 400 ° C., if the temperature of the heat treatment is 400 ° C. or more, in most cases, when forming the second wiring 15, Almost no gas is released from the second interlayer insulating film.

The effects of this embodiment are as follows. That is, by performing a heat treatment for releasing a gas from the second interlayer insulating film, when the barrier metal is deposited, the moisture absorbed in the second interlayer insulating film by the heat of this deposition causes the gas (HF, H ₂ O) and being released from the second interlayer insulating film. Further, by performing a heat treatment for releasing gas from the second interlayer insulating film, fluorine is diffused from the inside to the outside of the second interlayer insulating film, so that the first wiring 11 and the second wiring 15 There is a risk of peeling off from the two-layer insulating film. However, before the heat treatment for releasing gas from the second interlayer insulating film is performed, the concentration of fluorine in the second interlayer insulating film is small outside and high inside, so that the first layer from the inside of the second interlayer insulating film is first. The amount of diffusion of fluorine to the interface between the wiring 11 and the second wiring 15 is suppressed. By suppressing the release of these gases and the amount of diffusion of fluorine, separation of the first wiring 11 and the second wiring 15 from the second interlayer insulating film can be suppressed. Therefore, poor connection between the first wiring 11 and the second wiring 15 can be prevented.

Modified example. The method for forming the first interlayer insulating film 16, the third interlayer insulating film 17, the first wiring 11, the second wiring 15, the plug 10, and the plug 14 may be a method other than that described in the embodiment. .

The material of the plug 10 and the plug 14 may be aluminum. The first interlayer insulating film 16 and the third
The material of the interlayer insulating film 17 may be a silicon oxide film.

In the embodiment, the first wiring 11 and the second wiring 11
Although the example in which the present invention is applied to a semiconductor device having two wiring layers composed of the wiring 15 described above has been described, the present invention may be applied to a semiconductor device having three or more wiring layers. That is, in a semiconductor device having three or more layers of wiring, the first interlayer insulating film 16, the second interlayer insulating film 12, and the third interlayer insulating film 17 are interposed between the wirings.

In FIG. 1, the second interlayer insulating film 1
The position of the interface between the second and third interlayer insulating films 17 may be a position deeper from the surface of the third interlayer insulating film 12 than the position shown in FIG. For example, the second interlayer insulating film 12
The position of the interface between the second interlayer insulating film 17 and the third interlayer insulating film 17 is approximately the same as the position of the interface between the second interlayer insulating film 12 and the first interlayer insulating film 16. May be formed thin, and the third interlayer insulating film 17 may be formed thick.

Further, the case of forming the first interlayer insulating film 16 containing no fluorine has been described. Alternatively, the first interlayer insulating film 16 containing fluorine may be formed. However, the concentration of this fluorine is lower than the concentration of fluorine in the second interlayer insulating film 12 so that the first wiring 11
Need not be separated from the second interlayer insulating film.

[0040]

According to the first aspect of the present invention, when a heat treatment for releasing gas from the interlayer insulating film is performed, when depositing the barrier metal, the heat of this deposition causes
Moisture absorbed in the interlayer insulating film is prevented from becoming a gas and being released from the interlayer insulating film. Further, since the concentration of fluorine in the interlayer insulating film is low outside before the heat treatment for releasing gas from the interlayer insulating film, even if the heat treatment is performed, the first wiring and the first wiring are removed from within the interlayer insulating film. The amount of diffusion of fluorine to the interface of the second wiring is suppressed. By suppressing the release of these gases and the amount of diffusion of fluorine, separation of the first and second wirings from the interlayer insulating film can be suppressed.
Therefore, there is an effect that a semiconductor device which prevents poor connection between the first wiring and the second wiring can be obtained.

According to the second aspect of the present invention, there is an effect that an interlayer insulating film containing fluorine having a thin concentration on the outside and a high concentration on the inside can be easily formed.

According to the third aspect of the present invention, an interlayer insulating film containing fluorine having a thin concentration on the outside and a high concentration on the inside can be easily formed, and the first interlayer insulating film also contains fluorine to further increase the dielectric constant. This has the effect that the rate can be reduced.

According to the fourth aspect of the present invention, if the temperature is equal to or higher than the maximum temperature at the time of forming the second wiring, it is possible to substantially release gas from the interlayer insulating film.

According to the fifth aspect of the present invention, since the heat for forming the second wiring is generally about 400 ° C.,
When the temperature of the heat treatment is set to 400 ° C. or higher, in most cases, there is an effect that almost no gas is released from the interlayer insulating film when the second wiring is formed.

According to the sixth aspect of the present invention, since the heat treatment is performed and the fluorine concentration outside the interlayer insulating film is low, the first wiring and the second wiring can be prevented from peeling off. This has the effect of preventing poor connection of the second wiring.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view illustrating the method for manufacturing the semiconductor device according to the embodiment of the present invention;

FIG. 3 is a graph showing an example of the concentration of fluorine in a third interlayer insulating film 17 and a second interlayer insulating film 12;

FIG. 4 is a graph showing an example of the concentration of elements in the second wiring 15 and the interlayer insulating film 12 when the second wiring 15 is separated from the interlayer insulating film 12.

FIG. 5 is a sectional view showing a conventional semiconductor device.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Silicon semiconductor substrate, 11 1st wiring, 12 2nd interlayer insulating film, 15 2nd wiring, 16 1st interlayer insulating film, 17 3rd interlayer insulating film.

Claims (6)

[Claims] A step of forming a first wiring on a base layer; a step of forming an interlayer insulating film covering the surface of the first wiring and containing a thin layer of fluorine on the outside and a high concentration of fluorine on the inside; Performing a heat treatment on the interlayer insulating film to release gas from the interlayer insulating film; and after performing the heat treatment, a second step is performed on a surface of the interlayer insulating film.
Forming a wiring of the semiconductor device. 2. The step of forming the interlayer insulating film includes: forming a first interlayer insulating film covering a surface of the first wiring; and covering a surface of the first interlayer insulating film with fluorine. Second including
2. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming an interlayer insulating film; and forming a third interlayer insulating film covering a surface of the second interlayer insulating film. 3. The step of forming the interlayer insulating film, the step of forming a first interlayer insulating film containing fluorine covering the surface of the first wiring, and the step of covering the surface of the first interlayer insulating film. Second containing fluorine
2. The method of manufacturing a semiconductor device according to claim 1, further comprising: forming an interlayer insulating film; and forming a third interlayer insulating film covering a surface of the second interlayer insulating film. 4. The method according to claim 1, wherein a temperature of the heat treatment is equal to or higher than a maximum temperature at which the second wiring is formed. 5. The method according to claim 4, wherein the temperature of the heat treatment is 400 ° C. or higher. 6. A first wiring formed on a base layer, an interlayer insulating film formed so as to cover a surface of the first wiring and containing thin fluorine on the outside and a high concentration of fluorine on the inside; A second wiring formed on a surface of an insulating film, wherein the interlayer insulating film is subjected to a heat treatment for releasing gas.