JPH10261642A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent the destruction of bump electrodes and the peeling of barrier metal and enhance the reliability life of connection between a semiconductor chip and a circuit wiring board by forming the bump electrodes on bonding pads with a first metallic layer in-between which contains oxygen of higher concentration in the peripheral region than in the inner region. SOLUTION: A first metal layer 3 which contains oxygen of higher concentration at least in its peripheral region b than in its inner region a is formed on bonding pads 5, formed on a semiconductor chip 1. Then projected bump electrodes 2, composed of a second metal layer, are formed on the first metal layer 3. For example, a first metallic layer 3, composed of titanium which contains oxygen of higher concentration in its peripheral region b than in its inner region an and acts as barrier metal layer, is formed on bonding pads 5. Bump electrodes 2 composed of a second metal layer are formed thereon with a third metallic layer 4 which is highly wettable to solder metal.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device,
In particular, the present invention relates to a technique for flip-chip mounting a semiconductor chip on a circuit wiring board.

[0002]

2. Description of the Related Art In recent years, as the degree of integration of semiconductor devices has increased, there has been a demand for higher density semiconductor packaging technology. Typical examples of the high-density mounting technology of this semiconductor device include a wire bonding technology and a TAB technology. As the highest-density mounting technology, flip-chip mounting technology is used. It is often used as a technology for mounting on a computer.

[0003] Flip chip mounting technology is disclosed in US Pat.
Since the disclosure of Japanese Patent No. 401126 and US Pat. No. 3,429,040, the technique has been widely known. For example, as shown in FIG. 26, the basic structure of the semiconductor chip 1 is a bonding pad 5 provided on the semiconductor chip 1, a peripheral portion of the bonding pad 5, a passivation film 6 covering the surface of the semiconductor chip 1, and a bonding pad 5. A barrier metal layer 35 provided from above on the passivation film 6 on the periphery of the bonding pad 5 and the bump electrode 2 protrudingly formed on the barrier metal layer 35
And the wiring board 11, the terminal electrode 13 provided on the wiring board 11, the peripheral edge of the terminal electrode 13, and the solder resist film 12 formed on the wiring board 11, are joined by the bump electrode 2 and the terminal electrode 13. For example, a sealing resin 14 is provided in a space between the semiconductor chip 1 and the wiring board 11.
Is provided.

In flip-chip mounting technology, when the constituent material of a semiconductor chip is different from the constituent material of a circuit wiring board on which the semiconductor chip is mounted, a displacement caused by a difference in thermal expansion coefficient often occurs in the semiconductor device and the circuit wiring board. Occur. The generated displacement causes stress distortion in a bump electrode connecting the semiconductor device and the circuit wiring board. This stress strain destroys the bump electrode to be flip-chip mounted and shortens the reliability life. For this reason, conventionally, for example, by changing the arrangement of the bump electrodes, reducing the distance from the center point of the semiconductor device to the center point of the bump electrodes, and considering the material of the circuit wiring board, the coefficient of thermal expansion of the semiconductor device is determined. To make the temperature change of a flip-chip mounted semiconductor device small as in Japanese Patent Application Laid-Open No. 58-23462, and to make the semiconductor device and circuit wiring similar to Japanese Patent Application Laid-Open No. 61-194732. Improvements have been made such as filling the gaps between the substrates with a resin.

[0005] Proposals have also been made to make the bump electrode itself a structure that is robust against stress strain. FIG. 27 is a schematic diagram showing an example of a configuration around a conventional bump electrode. FIG.
As shown in FIG. 7, a passivation film 6 is usually formed on the semiconductor chip 1 on which the bonding pads 5 are provided and on the periphery of the bonding pads 5, and then a barrier metal layer 35 is provided on the bonding pads 5 and, for example, A bump electrode 2 made of solder is formed.

For example, Microelectronics Packaging Han
As described in the dbook, many proposals have been made to increase the bump height. Also, regarding the barrier metal that is formed to prevent the diffusion of the solder of the bump material and the aluminum of the bonding pad material, the barrier metal structure and its material configuration are limited to a structure that is strong against stress strain. Many proposals have been made to improve the reliability life.

For example, Japanese Patent Application Laid-Open No. 1-128545,
As described in Japanese Patent Application Laid-Open No. 1-10038, etc., the barrier metal to be formed is formed to be larger than the opening size of the bonding pad, or conversely, formed to be smaller than the bonding pad size to reduce the stress distortion generated in the bump. Let
Proposals have been made to improve reliability.

Further, Japanese Patent Application Laid-Open Nos. Sho 56-5506 and
Japanese Patent Application Laid-Open No. 6-37636 proposes a method for manufacturing a barrier metal in which bump electrodes are formed with high precision in order to improve bump connection reliability.

Further, as in US Pat. No. 4,299,079, a method of forming a slope at the edge of the barrier metal to gradually reduce stress strain is disclosed in Japanese Patent Application Laid-Open No. 1-209746. A method of providing a stress relaxation layer has also been proposed, and stress relaxation to a barrier metal has been performed together with relaxation of stress distortion generated in the bump electrode itself.

This is because it has been clarified that the bump electrode is destroyed due to the stress strain, and that the stress is also generated at the edge of the barrier metal, which also destroys the barrier metal. For this purpose, it is important to relieve the stress of the bump electrode and the barrier metal.

FIG. 28 is a schematic diagram showing another example of the configuration around the conventional bump electrode. For such a problem,
In JP-A-59-121955, as shown in FIG. 28, a titanium layer 35 in which oxygen is dispersed is formed as a first barrier metal layer, and a solder-connectable metal layer 45 is formed on the titanium layer 35. And a method of providing a bump electrode 2 thereon is proposed.

Titanium is a well-known metal as an adhesive layer metal constituting a barrier metal.
JP 61346 A also discloses a structure using titanium.

Japanese Patent Application Laid-Open No. Sho 59-121955, in which oxygen is dispersed in titanium, proposes a titanium layer containing oxygen having compressive stress in order to alleviate the tensile stress of a material originally having tensile stress. Is disclosed. Here, the oxygen concentration contained in titanium is set to 5
× is the oxygen concentration obtained when depositing titanium in an atmosphere containing 10 ^-5 ~5 × 10 ^-6 Torr partial pressure oxygen. With such a concentration, an effect is obtained that the barrier metal does not peel off due to the stress strain generated at the edge of the barrier metal.

However, as the bump dimensions become finer, the method described in Japanese Patent Application Laid-Open No. Sho 59-121955 becomes inadequate, and there is a problem that the barrier metal peels off at the edge of the barrier metal. Was. This is because the barrier metal becomes finer as the bump size becomes finer, and the method of relaxing the uniform tensile stress of the entire barrier metal as before can no longer cope with the problem of barrier metal peeling. That is the cause.

On the other hand, for example, Japanese Patent Application Laid-Open No. Sho 59-1219
No. 55, it is conceivable to increase the oxygen concentration contained in the titanium layer to increase the compressive stress, but if the oxygen concentration in the titanium film is increased, titanium is oxidized more than necessary, Since the connection resistance of the bump electrode is increased, it is not effective in electrical characteristics.

[0016]

As described above, the flip-chip mounting technique for interconnecting the bump electrodes formed on the semiconductor chip and the electrode pads of the circuit wiring board involves the following.
The stress strain resulting from the difference in the coefficient of thermal expansion between the circuit wiring board and the semiconductor chip is concentrated on the bump electrode, which has caused the destruction of the bump electrode and the separation of the barrier metal. This problem has been particularly important in miniaturization of bump electrodes accompanying miniaturization of semiconductor devices.

The present invention has been made in view of the above problems, and has been made in consideration of a thermal expansion coefficient of a semiconductor chip and a circuit wiring board in a semiconductor device using a technique of flip-chip mounting a semiconductor chip on a circuit wiring board using bump electrodes. By reducing the stress distortion caused by the difference, preventing the destruction of the bump electrode and the separation of the barrier metal, the connection reliability life between the semiconductor chip and the circuit wiring board is improved, and the circuit wiring board, the semiconductor chip and the bump electrode are improved. It is an object of the present invention to provide a semiconductor device which can sufficiently cope with miniaturization of semiconductor devices.

[0018]

According to the present invention, there is provided:
A semiconductor chip, a bonding pad provided on the semiconductor chip, and a first metal layer formed on the bonding pad, wherein at least a peripheral region of the first metal layer contains a higher concentration of oxygen than an inner region thereof And a bump electrode made of a second metal layer protrudingly formed on the first metal layer.

According to the present invention, secondly, a semiconductor chip, a bonding pad provided on the semiconductor chip, and a bonding pad formed on the bonding pad and having at least a peripheral area higher than an inner area thereof. A first metal layer containing oxygen at a concentration and containing at least one metal selected from the group consisting of titanium, tungsten, and chromium as a main component, and a first metal layer protruding on the first metal layer. And a bump electrode made of two metal layers.

In the present invention, preferably, a third metal layer having good wettability with solder can be further provided between the first metal layer and the second metal layer. In the present invention, preferably, the third metal layer is nickel,
It contains at least one selected from the group consisting of copper, palladium, gold, chromium, molybdenum, ruthenium, and alloys thereof.

[0021]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present inventors have improved a barrier metal structure of a bump electrode formed on a bonding pad of a semiconductor chip. According to a first aspect of the present invention, a bump electrode including a first metal layer composed of a group of thin-film metals on a bonding pad and a second metal layer electrically connected to a circuit wiring board on the first metal layer In the semiconductor chip having the above, oxygen is contained at a higher concentration in the peripheral portion than in the first metal layer.

For this reason, in the semiconductor device according to the first aspect, the stress strain at the edge of the barrier metal can be effectively alleviated, and peeling can be prevented. Further, in the semiconductor device of the present invention, the oxygen concentration only in the peripheral portion of the barrier metal is increased, and the oxygen concentration in the entire barrier metal is not increased, so that the connection resistance of the bump portion is increased as compared with the past. Thus, flip-chip mounting can be performed with a low resistance value.

More specifically, when oxygen is not contained, the stress strain at the edge of the barrier metal is relaxed by using a thin film metal containing oxygen having a compressive stress as the thin film metal originally having a tensile stress. Is done. In particular, due to the structure in which oxygen is dispersed at a high concentration only on the outer periphery of the barrier metal, many metals having high resistivity are stacked only on the passivation film covering the bonding pad edge, and the bonding pad is formed on the bonding pad. Has a structure that is not laminated, so that connection can be made with a low resistance without increasing the connection resistance.

In the present invention, a metal film containing titanium, tungsten, or chromium as a main component is preferably used as the metal film in contact with the bonding pad of the first metal layer. When these metals are used, the effect is significantly improved as compared with other metals.

Further, in the first metal layer, the area in which oxygen is dispersed and arranged at a high concentration has a value of 50% or less with respect to the area determined from the entire outer dimensions of the metal layer to be formed. Is preferred.

The concentration of oxygen contained is 5 × 10 ^-5 ~
It is preferable that the oxygen concentration is equal to or higher than the concentration when formed at a degree of vacuum of 5 × 10 ⁻⁶ Torr. At this time, the effect of the present invention is remarkably improved, and the problems so far can be easily solved.

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a schematic sectional view showing a part of a semiconductor device according to the present invention. As shown in FIG. 1, the semiconductor device of the present invention has a bonding pad 5 provided on a semiconductor chip 1 and a coating formed on a peripheral portion of the bonding pad 5 excluding a connection portion of the bonding pad 5 and on a surface of the semiconductor chip 1. A first metal layer 3 made of, for example, titanium, which is provided on the passivation film 6 and the bonding pad 5 and serves as a barrier metal layer, and is provided on the first metal layer 3, and has a wettability with solder metal. A third metal layer 4 made of a good metal, and a bump electrode 2 made of a second metal layer protruding from the third metal layer 4. In the first metal layer 3 of the semiconductor device, the peripheral region indicated by the reference numeral b contains oxygen at a higher concentration than the inner region indicated by the reference numeral a in the figure.

FIG. 2 is a diagram for explaining the inner region and the peripheral region described above, and shows a state in which FIG. 1 is seen through from above. As shown in FIG. 2, a region b of the first metal layer 3 outside the region a surrounded by a dashed line contains a high concentration of oxygen.

FIGS. 3 and 4 are views showing a state in which the semiconductor chip having the bump electrodes shown in FIG. 1 is mounted on a wiring board. As shown in FIG. 3, the semiconductor chip 1 has bump electrodes 2 connected on a plurality of bonding pads 5 by the configuration shown in FIG. 1, and is formed on a wiring board 11 via the bump electrodes. Are connected to the plurality of terminal electrodes 13. The terminal electrode 1 on the surface of the wiring board 11
3 and the peripheral edge of the terminal electrode 13 are covered with the solder resist film 12.

As shown in FIG. 4, the semiconductor chip 1 of FIG.
A sealing resin 14 can be sealed in the gap between the wiring board 11 and the wiring board 11. By using the sealing resin 14, it is possible to reduce a phenomenon in which stress distortion caused by a difference in thermal expansion coefficient between the semiconductor chip 1 and the wiring board 11 is concentrated on the bump electrode and the barrier metal.

A semiconductor device having a bump electrode according to the present invention is implemented by the steps shown in FIGS. 5 to 11, 13 to 15, and 20 to 23 described below. FIG.
As shown in FIG. 1, first, a bonding pad 5 is formed on a semiconductor chip 1 and is made of, for example, PSG (phosphorus silica glass) or SiN (silicon nitride) except for a part of the bonding pad 5 of 50 μm × 50 μm. A semiconductor device wafer on which a passivation film 6 is formed is prepared, and, for example, Ti is formed on the entire surface as a first metal layer 3 serving as a barrier metal to a thickness of 1000 Å.

The titanium film 3 has a thickness of 5 × 10 ^{−5 to} 5 × 10 ⁻⁶ T
The film is formed at a vacuum lower than the vacuum formed by the presence of oxygen or water vapor at a vacuum lower than the orr partial pressure. By forming a titanium film at this degree of vacuum, a titanium film that originally has a tensile stress exhibits a property of having a compressive stress.

It is also possible to form a titanium film under a mixed gas such as pure oxygen, water vapor, oxygen + nitrogen, oxygen + helium, oxygen + argon, etc. When the titanium film 3 is deposited under the above conditions, the titanium film 3
Oxygen molecules are adsorbed on the surface of. Since the lattice solubility of oxygen in the titanium film 3 is relatively high as compared with other metals, oxygen penetrates into the titanium film 3 to generate a compressive stress in the titanium film 3. In order to increase the diffusion of oxygen molecules into the titanium film 3, it is preferable to deposit the titanium film 3 in a temperature range of about 100 to 300 ° C.

As the first metal layer, tungsten, chromium or the like can be preferably used in addition to titanium. Next, a positive resist OFPR-800 (manufactured by Tokyo Ohka Co., Ltd.) is formed on the entire surface by spin coating to obtain a resist layer. Further, after exposing using a glass mask (not shown) having a pattern having an opening of 40 μm × 40 μm around the bonding pad 5, the developing solution NMD
-3 (manufactured by Tokyo Ohkasha Co., Ltd.), as shown in FIG.
A resist pattern 21 having an opening having a size of m × 40 μm is formed.

Thereafter, as shown in FIG. 7, the wafer on which such a pattern is formed is, for example, N ₂ / H ₂ = 7 /
350 ° C. forming gas atmosphere 2 composed of 3
2, the titanium film portion 27 exposed from the resist pattern 21 is reduced, and the bonding pad 5
The oxygen concentration in the titanium film 3 corresponding to the center is reduced.

Subsequently, as shown in FIG. 8, the resist film on the wafer is dissolved and removed using, for example, acetone. For removing the resist film, it is also possible to use Peeling-10 (manufactured by Tokyo Ohka Co., Ltd.).

Next, as shown in FIG. 9, on the wafer surface from which the resist film has been removed, for example, a Cu film 4 of 1 μm is formed as a third metal layer over the entire surface. C formed on the entire surface
The thickness of the u film 4 is not particularly limited, but there is no particular problem as long as the ratio with the thickness of the titanium has a value of Cu film thickness / titanium film thickness = 1 to 10. However, this Cu
Since the thin film serves as a cathode metal when the solder to be formed later as the second metal layer is subjected to electroplating, when the wafer system has a large diameter exceeding 8 inches, the ratio with the titanium film thickness is 5 to 5. Preferably, the range has a value of 10.

Then, as shown in FIG. 10, a thick resist AZ4903 (manufactured by Hoechst Japan Co., Ltd.) is formed by spin coating to form a resist film 23 having a thickness of 100 μm. 80 μm having a size that is 30 μm larger on one side than 5 μm
An opening 24 of mx80 μm is formed in the resist film 23 on Cu / Ti. The exposure is performed by irradiating a sufficient amount of exposure energy even if the thickness of the resist film 23 is large, and the development is performed by an AZ400K developer (manufactured by Hoechst Japan). The angle adjustment of the portion of the resist surface in contact with the thin-film metal is performed, for example, by using the 13th IEEE / IEMT Symp.
As described in Osium pp 288, 1992, the control is performed by adjusting the exposure energy, the distance between the resist surface and the glass mask, and the concentration of the developing solution.

Thus, the silicon wafer having the resist film 23 provided with the opening 24 at a portion corresponding to the bonding pad is immersed in a sulfonic acid solder plating solution comprising the following solution, and the Cu / Ti is used as a cathode to form a plating solution. Electroplating is performed using, for example, a high-purity eutectic solder plate having a corresponding composition as an anode. Current density is 1 to 4 (A / dm ² )
As shown in FIG. 11, the solder composition (Pb / Pb /
A plating metal layer made of a solder alloy having a composition whose Sn) is substantially equal to the eutectic composition or slightly shifted to the Pb side or the Sn side is deposited on Cu by 70 μm.

FIG. 12 is a schematic sectional view of an electroplating apparatus used in the electroplating step. As shown in the figure, this apparatus is provided with a plating apparatus main body 50 having a cup-type plating tank, an anode electrode 55 and a cathode electrode 54 provided on the upper peripheral wall of the plating tank, and provided below the plating tank. And an anode plate 51 having a plurality of apertures connected to the anode electrode 55.

An anode pin 52 connected to a driving power source,
A predetermined voltage is applied by bringing the cathode pin 53 into contact with the anode electrode 55 and the cathode electrode 54, respectively. The substrate 100 to be subjected to plating is disposed above the plating tank, facing the anode plate 51 with its main surface 101 downward, and connected to the cathode electrode 54.

The plating solution is supplied to the inlet 6 at the bottom of the plating tank.
8, flows toward the substrate 100 connected to the cathode electrode 54 through the opening 70 of the anode plate 51, plating is performed on the substrate 100, and plating metal is deposited. Thereafter, the waste liquid after the plating treatment is discharged from a discharge port (not shown) provided at the upper part of the peripheral wall of the plating bath.

By using such an apparatus, an electroplated metal layer having a uniform thickness can be obtained. An example of the composition of the plating solution used is shown below.

Composition of Sulfonic Acid Solder Plating Solution Tin ion (Sn ²⁺ ) 12 vol% Lead ion (Pb ²⁺ ) 30 vol% Aliphatic sulfonic acid 41 vol% Nonionic surfactant 5 vol% Cationic surfactant 5% by volume Isopropyl alcohol 7% by volume As described above, the semiconductor wafer on which the solder alloy has been electroplated on the bonding pad 5 of the semiconductor device is immersed in an acetone solution to form a resist AZ490 on the wafer.
3 is dissolved away.

Next, on a semiconductor wafer on which a solder alloy plating metal layer is formed, for example, a solution of which image inversion type resist AZ5214E (manufactured by Hoechst Japan Co., Ltd.) is adjusted in viscosity is spin-coated, and an etching resist film 26 is formed. To form The viscosity is adjusted to be high in order to perform etching with high accuracy even when the thickness of the metal layer to be plated is large. At this time, the resist film 26 is formed corresponding to the surface shape of the plating metal layer. The resist film thickness was 10 μm on the plating metal layer, and 55 μm in the portion where no bump metal was formed.

Next, exposure is performed after a glass mask having an opening pattern of 84 μm on one side having an opening size of 4 μm larger than the bump electrode size of 80 μm is positioned at a required position. Exposure is 2000 mJ / cm of exposure energy
Carried out in ^2, baking the wafer on a hot plate at 0.99 ° C. after exposure. Next, the baked wafer is immersed in a developer and developed.

By performing the above steps, an etching resist 26 is selectively formed only on the bump metal as shown in FIG. Although the image inversion type resist is used in this embodiment, a positive type resist OFPR-800 (manufactured by Tokyo Ohka Co., Ltd.) having an aspect ratio shape capable of forming a resist up to the side surface of the first metal layer or the second metal layer is used. ) Or a negative resist OMR-85 (manufactured by Tokyo Ohkasha) can be used.

Next, a necessary portion of copper is removed by etching with a mixed solution composed of ammonium persulfate, sulfuric acid, and ethanol, or a mixed solution composed of citric acid, hydrogen peroxide, and a surfactant. A necessary portion of titanium is removed by etching with a mixed solution composed of acetic acid and hydrogen peroxide, and then the coated etching resist 26 is dissolved and removed using acetone.
As shown in FIG. 14, a columnar bump metal 25 is obtained.

Note that an etching resist is not always necessary, and if selective etching with the bump metal material formed as the second metal layer is possible, the cathode metal can be etched using the second metal itself as a mask. .

For example, Cu /
When etching the Ti cathode metal with the above-mentioned etching solution, the selectivity of solder and Cu / Ti is Ni / Ti.
However, the etching resist is not necessarily required because it is higher than the above.

Cu / Ti is finally formed as a barrier metal of the bump electrode by forming a bump electrode by electroplating and then etching a necessary portion. Thin film metal is Cu
It is not necessary to limit to Cu / Ti, but Cu / Ti
And The metal formed on the titanium film is preferably, for example, at least one selected from nickel, copper, palladium, molybdenum, ruthenium, or an alloy thereof. Further, silicon is preferably used for the wafer, but other materials such as gallium arsenide, sapphire, glass epoxy, alumina ceramic, and aluminum nitride can also be used.

Next, the wafer on which the solder alloy has been formed is heated to 250 ° C. in a nitrogen atmosphere to melt the solder. By performing the heat treatment in this manner, as shown in FIG. 15, the bump electrode is made spherical, the adhesion to the barrier metal is improved, and a highly reliable bump electrode is formed.

By performing the above steps, a bump electrode having a diameter of 100 μm and having a structure having a high oxygen concentration is selectively formed only on the peripheral portion of the barrier metal on the bonding pad.

The solder alloy and the metal having high wettability can be formed by using an electroplating method. In this case, as the cathode metal material, a titanium film in which the oxygen concentration is selectively changed can be used, but it is preferable to form Cu / Ti as the cathode metal as described in the present embodiment. .

When the electroplating method is used, Cu having high wettability with solder is formed as follows. The silicon wafer in which the resist film at the portion corresponding to the bonding pad is opened is immersed in a copper sulfate plating solution comprising the following solution, and a phosphorous containing (0.03 Using a high-purity copper plate as an anode, copper is formed by electroplating of 30 μm with gentle stirring at a current density of 1 to 5 (A / dm ² ). The electroplating apparatus used in the electrocopper plating step is as shown in the schematic sectional view of FIG.

Copper sulfate pentahydrate 2 oz / gallon Sulfuric acid 30 oz / gallon Hydrochloric acid 10 ppm Thioxanthate-S-propanesulfonic acid (or thioxanthatesulfonic acid) 20 ppm Polyethylene glycol (molecular weight: 400,000) 40 ppm Reaction product of polyethyleneimine (molecular weight: 600) with benzyl chloride 2 ppm For example, nickel is formed as follows.

For nickel plating, an electroplating apparatus similar to that shown in FIG. 12 is used, a Cu / Ti film formed on a wafer is connected to a cathode of the electroplating apparatus, and a high-purity nickel plate is used as an anode. It can be formed by using. The electroplating is performed at a liquid temperature of 55 ° C., a current density of 1 to 2 (A / dm ² ), and a nickel plating film having a thickness of about 30 μm is formed while gently stirring the nickel plating solution with a pump.

The following solutions can be used as the nickel plating solution. Nickel sulfate hexahydrate 300 g / l Nickel chloride hexahydrate 60 g / l boric acid 50 g / l saccharin 500 ppm-5000 ppm formalin 1000 ppm-2000 ppm Thus, the use of the electroplating method requires a cathode metal etching removal step. , A metal having good wettability with solder can be deposited.

When the adhesion strength of the bump electrodes on the semiconductor chip formed as described above was evaluated, the following results were obtained. That is, a bump electrode composed of Pb / Sn = 40/60 was formed on a 10 mm × 10 mm semiconductor chip used for explaining a method of manufacturing a semiconductor device.
When the shear strength of 256 bump electrodes formed with a diameter of 100 μm on / Ti was measured, the bump electrode according to the present invention had a strength of 80 kg / mm ² .

Compared with the conventional structure in which oxygen is not dispersed, the structure according to the present invention has a strength of 40 kg / mm ² , and the structure in which the oxygen concentration is uniformly dispersed has a strength of 60 kg / mm ^2. Obviously, the connection strength of the bump to the semiconductor chip has been improved, and it has been confirmed that the reliability is high.

In particular, the adhesion strength when titanium is used as the first metal layer is about 10% higher than the evaluation result separately performed using tungsten or the like.
The effectiveness of using the titanium film as the adhesion metal of the barrier metal was confirmed.

Furthermore, the ratio of the area of the titanium film containing oxygen at a high concentration to the area determined from the external dimensions of the first metal layer, the relationship with the compressive stress, the ratio of the area, the connection resistance, The relationship was measured. Graphs showing the results are shown in FIGS. 16 and 17, respectively.

As shown in FIG. 16, the compressive stress shows a constant value of about 520 kg / mm ² irrespective of the area-region ratio. Further, as shown in FIG. 17, when this ratio is 50% or less, the bump connection resistance shows a constant value of about 10 mΩ, but when the area exceeds 50%, the connection resistance increases with the increase of the area. Shows a tendency to increase sharply.

From these results, it was confirmed that the region where oxygen in the titanium film is dispersed at a high concentration is preferably 50% or less with respect to the area determined from the outer dimensions of the first metal layer.

Further, the relationship between the pressure of the oxygen atmosphere and the compressive stress during the formation of the titanium film and the relationship between the pressure and the connection resistance were measured. FIG. 18 is a graph showing the results.
And FIG.

From these figures, 5 × 10 ^{−5 to} 5 × 10 ⁻⁶
When the oxygen concentration is equal to or higher than that when formed at a degree of vacuum of Torr, the compressive stress remaining in the titanium film is 520 k
g / mm ² , which is about 1.5 times the value of 350 kg / mm ² when formed at a degree of vacuum of 5 × 10 ^{−5 to} 5 × 10 ⁻⁶ Torr or less. About 3
It was confirmed that it improved twice.

The connection resistance depends on the area ratio of oxygen contained in the titanium film at a high concentration with respect to the area determined from the outer dimensions of the first metal layer. As shown in the figure, the area ratio increases with an increase in the oxygen atmosphere concentration, but the area ratio is 50% or less.
%, A constant value of about 10 mΩ was confirmed as shown in the graph 193. This means that the area ratio is 5
A value of 0% or less indicates that the connection resistance does not depend on the partial pressure of the oxygen atmosphere.

On the other hand, a circuit wiring board on which a semiconductor chip is mounted is formed by using a known technique such as US Pat. No. 4,811,028 or a normal glass epoxy board.

For example, as shown in FIG. 20, a printed circuit board SLC (Surface Laminar Circuit) of a system in which an insulating layer and a conductive layer are built up on a glass epoxy substrate 120
) A substrate 11 is prepared. The circuit wiring board 11 has one connection terminal portion 13 corresponding to the bump electrode 2 of the semiconductor chip 1.
A hole having a diameter of 00 μm is provided, and Cu is exposed.
A portion other than the terminal portion 13 of the substrate is covered with the solder resist 12.

Next, as shown in FIG. 21, the semiconductor chip 1 and the circuit wiring board 11 are aligned using a flip chip holder 31 having a half mirror, which is a known technique (not shown). Then, the connection terminals 13 between the bump electrodes 2 and the circuit wiring board 11 are brought into electrical and mechanical contact. At this time, the circuit wiring board 11
Is held on a stage 32 having a heating mechanism, and P
It is preheated in a nitrogen atmosphere to 200 ° C. higher than the melting point of b / Sn = 40/60.

Further, the semiconductor chip 1 and the circuit wiring board 1
By heating the collet 31 holding the semiconductor chip 1 in a state where the semiconductor chip 1 is in contact with the stage 32 on which the substrate 11 is mounted, the bump electrode 2 is melted by heating the bump electrode 2 at the same temperature of 200 ° C. in a nitrogen atmosphere. And the electrode 13 of the circuit wiring board 11 are electrically and mechanically temporarily connected.

Finally, electrical and mechanical connection is realized by passing the circuit wiring board on which the semiconductor chip is mounted in a reflow furnace heated to 250 ° C. in a nitrogen atmosphere. As shown in FIG. 22, at this time, a self-alignment effect occurs due to the solder surface tension, and a slight displacement generated at the time of mounting is corrected, so that bonding can be performed at an accurate position.

As shown in FIG. 23, the semiconductor device 1 and the circuit wiring board 11 which are flip-chip mounted as required.
It is also possible to dispose a sealing resin 14, which is a known technique, in the gap created by the sealing resin.

As a resin to be sealed, for example, an epoxy resin containing a bisphenol-based epoxy, an imidazole curing catalyst, an acid anhydride curing agent and a spherical quartz filler in a weight ratio of 45% by weight can be used.

Also, for example, 100 parts by weight of a cresol novolac type epoxy resin (ECON-195XL; manufactured by Sumitomo Chemical Co., Ltd.), a phenol resin 54 as a curing agent
100 parts by weight of fused silica as a filler, 0.5 parts by weight of benzylmethylamine as a catalyst, 3 parts by weight of carbon black and 3 parts by weight of a silane coupling agent as other additives were pulverized, mixed and melted. It is also possible to use an epoxy resin melt, and its material is not particularly limited.

By performing the steps described above, FIG.
Can be realized. Here, the connection reliability of the semiconductor device according to the present invention formed as described above was examined.

A Pb / S is applied to the main surface of a 10 mm × 10 mm semiconductor chip used for explaining the method of manufacturing a semiconductor device.
The reliability was evaluated using a sample in which 256 n = 40/60 connection electrodes were formed with a diameter of 100 μm and mounted on a circuit wiring board.

A case where the connection was opened at even one of the 256 pins was regarded as defective, and the vertical axis shows the cumulative failure rate and the horizontal axis shows the temperature cycle. The number of samples is 1000, and the conditions of the temperature cycle test are (-55 ° C (30 min) to 2
5 ° C (5min)-125 ° C (30min)-25 ° C
(5 min)). Fig. 2 shows a graph showing the test results.
It is shown in FIG.

In the figure, reference numeral 241 denotes a titanium layer containing no oxygen, and 242 denotes a titanium layer containing oxygen.
Is a graph showing the results of the titanium layer according to the present invention. In the semiconductor device having a structure in which oxygen is not dispersed in the barrier metal, a connection failure occurred in 1500 cycles, and the failure became 100% in 2000 cycles. Further, a semiconductor device in which oxygen is uniformly dispersed at a predetermined concentration,
Although the reliability is improved up to 2500 cycles, 50% failure occurs at 3000 cycles. These defects are:
It occurs at the interface between the barrier metal forming the bump electrode and the bonding pad, and both are caused by the stress and strain at the barrier metal interface.

However, in the structure according to the present invention, 3500
No failure occurred until the cycle, and it was confirmed that the reliability was extremely improved. In addition, 85 samples according to the invention
The same test was performed by storing at 85 ° C., 85% RH and V _DD = 5 V. FIG. 25 shows a graph showing the test results.

In the figure, 251 is a titanium layer containing no oxygen, 252 is a titanium layer containing oxygen, 253
Is a graph showing the results of the titanium layer according to the present invention. As is clear from FIG. 25, in a conventional semiconductor device having a structure in which oxygen is not dispersed in a barrier metal, a corrosion failure occurs at 500H, and the failure is 10 at 1500H.
It became 0%. In the case of a semiconductor device having a structure in which oxygen is uniformly dispersed, no defect occurs up to 2500H and the reliability is improved, but the defect becomes 100% at 3000H. These defects were all caused by the electrical corrosion of the titanium film formed on the bonding pad and the aluminum of the bonding pad material.

However, in the structure according to the present invention, 3000
No failure occurred up to H, indicating that the reliability was extremely high. In particular, a metal with good solderability and wettability is arranged on a titanium film that exhibits effectiveness against bump stress strain, and the metal is selected from nickel, copper, palladium, gold, chromium, molybdenum, ruthenium Alternatively, it was confirmed that when these alloys were used, the connection reliability was significantly improved. Furthermore, nickel with good wettability with solder is nickel,
The order of copper, palladium, gold, chromium, molybdenum, and ruthenium was also confirmed.

Therefore, it was understood from the above evaluation results that the semiconductor device according to the present invention was a highly reliable mounting structure having excellent resistance to a heat cycle and a high temperature and high humidity test. It should be noted that the present invention is not limited to the above-described embodiment, and can be variously modified without departing from the gist thereof. For example, the circuit wiring board configuration is not limited to SLC, and a ceramic substrate can be used.
The material of the bump is not limited to Pb / Sn, but can be variously changed.

[0084]

According to the present invention, since the peripheral portion of the first metal layer formed as the barrier metal layer on the bonding pad contains oxygen at a higher concentration than the inner peripheral portion. Basically, the stress of the first metal layer having the tensile stress can be converted into the compressive stress, and the stress strain at the edge of the barrier metal can be effectively reduced. Therefore, the problem of peeling at the edge of the barrier metal due to stress and strain, which has been a problem when forming a fine bump electrode, can be easily and reliably solved.

In particular, in the present invention, the oxygen concentration only at the peripheral portion of the barrier metal is increased, and the oxygen concentration of the entire barrier metal is not increased, so that the connection resistance at the bump portion does not increase as compared with the prior art. Thus, flip-chip mounting can be performed with a low resistance value. This is because a metal layer having a high resistivity is selectively stacked only on the passivation film covering the bonding pad end portion, and is not stacked on the bonding pad that performs electrical connection.

Further, since the film density at the edge of the barrier metal is high, an additional effect of improving the moisture resistance as compared with the conventional structure also occurs. Therefore, by using the semiconductor device of the present invention, fine bump electrodes can be mounted with high reliability and high density easily as compared with the case where the conventional technology is used.

[Brief description of the drawings]

FIG. 1 is a sectional view showing a configuration of an example of a semiconductor device according to the present invention.

FIG. 2 is a perspective view of FIG. 1 as viewed from above.

FIG. 3 is a diagram showing a state in which the semiconductor chip of the present invention is mounted on a wiring board;

FIG. 4 is a diagram showing a state in which the semiconductor chip of the present invention is mounted on a wiring board;

FIG. 5 is a view for explaining a manufacturing process of the semiconductor device of the present invention.

FIG. 6 is a view for explaining a manufacturing process of the semiconductor device of the present invention.

FIG. 7 is a diagram illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 8 is a diagram for explaining a manufacturing process of the semiconductor device of the present invention.

FIG. 9 is a diagram for explaining a manufacturing process of the semiconductor device of the present invention.

FIG. 10 is a diagram illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 11 is a diagram illustrating a manufacturing process of the semiconductor device according to the present invention;

FIG. 12 is a schematic cross-sectional view illustrating an example of an electroplating apparatus used in a manufacturing process of a semiconductor device according to the present invention.

FIG. 13 is a view illustrating a manufacturing process of the semiconductor device according to the present invention;

FIG. 14 is a diagram illustrating a manufacturing process of the semiconductor device of the present invention.

FIG. 15 is a diagram illustrating a manufacturing process of the semiconductor device according to the present invention;

FIG. 16 is a graph showing a relationship between an oxygen-containing region area ratio and a compressive stress.

FIG. 17 is a graph showing a relationship between an oxygen-containing region area ratio and connection resistance.

FIG. 18 is a graph showing the relationship between the degree of vacuum in an oxygen atmosphere and compressive stress.

FIG. 19 is a graph showing the relationship between the degree of vacuum in an oxygen atmosphere and the connection resistance.

FIG. 20 is a view illustrating a manufacturing process of the semiconductor device according to the present invention;

FIG. 21 is a diagram illustrating a manufacturing process of the semiconductor device according to the present invention;

FIG. 22 is a diagram illustrating a manufacturing process of the semiconductor device according to the present invention;

FIG. 23 is a diagram illustrating a manufacturing process of the semiconductor device according to the present invention;

FIG. 24 is a graph showing the relationship between the cumulative failure rate and the temperature cycle.

FIG. 25 is a graph showing the relationship between the cumulative failure rate and the temperature cycle.

FIG. 26 is a diagram showing a state where a conventional semiconductor chip is mounted on a wiring board;

FIG. 27 is a sectional view showing an example of a conventional semiconductor device.

FIG. 28 is a sectional view illustrating another example of a conventional semiconductor device.

[Explanation of symbols]

 1,100 semiconductor chip 2 ... bump electrode 3 ... first metal layer 4 ... second metal layer 5 ... bonding pad 6 ... passivation film 7 ... high concentration oxygen dispersion region 8 ... low concentration oxygen dispersion region 11 ... circuit wiring board 12 ... Solder resist 13 ... Terminal electrode 14 ... Sealing resin 21 ... Concentration control resist 22 ... Reducing atmosphere 23 ... Plating resist 24 ... Bump forming hole 25 ... Solder metal 26 ... Etching resist 31 ... Collet 32 ... Heater 50 ... Plating tank 51 ... Anode plate 52: Anode pin 53: Cathode pin 54: Cathode electrode 55: Anode electrode 68: Inlet 110: Plating solution

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Soichi Homma 33, Shinisogo-cho, Isogo-ku, Yokohama-shi, Kanagawa Pref.

Claims (4)

[Claims] 1. A semiconductor chip, a bonding pad provided on the semiconductor chip, and a first pad formed on the bonding pad, wherein at least a peripheral region of the semiconductor chip contains a higher concentration of oxygen than a region inside the semiconductor chip. And a bump electrode formed of a second metal layer protruding above the first metal layer. 2. A semiconductor chip, a bonding pad provided on the semiconductor chip, and oxygen formed on the bonding pad, wherein at least a peripheral region of the semiconductor chip contains oxygen at a higher concentration than an inner region thereof, and titanium Electrode consisting of a first metal layer mainly composed of at least one metal selected from the group consisting of tungsten, chromium and chromium, and a second metal layer protrudingly formed on the first metal layer And a semiconductor device comprising: 3. The semiconductor device according to claim 1, wherein a third metal layer having good wettability with solder is further provided between said first metal layer and said second metal layer. 4. The method according to claim 1, wherein the third metal layer contains at least one selected from the group consisting of nickel, copper, palladium, gold, chromium, molybdenum, ruthenium, and alloys thereof. 4. The semiconductor device according to 3.