WO2011074158A1 - Semiconductor chip and semiconductor device provided with said semiconductor chip - Google Patents

Semiconductor chip and semiconductor device provided with said semiconductor chip Download PDF

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Publication number
WO2011074158A1
WO2011074158A1 PCT/JP2010/005392 JP2010005392W WO2011074158A1 WO 2011074158 A1 WO2011074158 A1 WO 2011074158A1 JP 2010005392 W JP2010005392 W JP 2010005392W WO 2011074158 A1 WO2011074158 A1 WO 2011074158A1
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WIPO (PCT)
Prior art keywords
semiconductor chip
protective film
bump
barrier metal
metal film
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PCT/JP2010/005392
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French (fr)
Japanese (ja)
Inventor
仲野純章
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パナソニック株式会社
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Publication of WO2011074158A1 publication Critical patent/WO2011074158A1/en

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    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01082—Lead [Pb]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013—Alloys
    • H01L2924/014—Solder alloys

Definitions

  • the present invention relates to a semiconductor chip having an under barrier metal film and a bump, and a semiconductor device including the semiconductor chip.
  • Flip chip mounting is a mounting method in which bumps of a semiconductor chip and a mounting substrate are electrically connected. The bump is formed on the under barrier metal film.
  • the bump base conductor layer is formed of a first conductor layer made of titanium (Ti) or a titanium alloy formed on the extraction electrode, and a second conductor formed on the first conductor layer and containing palladium (Pd). And have a layer.
  • the material of the second conductor layer in the bump base conductor layer is Pd instead of conventional copper (Cu).
  • a brittle alloy layer such as Cu—Sn is not formed in the joint region between the second conductor layer and the bump as in the case where the material of the second conductor layer is Cu. Connection strength can be improved. For this reason, it can suppress that a bump peels. Thereby, the reliability of the semiconductor device is improved.
  • the bump base conductor layer is formed by a sputtering method. This makes it possible to improve the uniformity of the thickness of the bump base conductor layer in the plane of the semiconductor wafer. For this reason, since the uniformity of the formation conditions of the plurality of bumps in the semiconductor wafer surface can be improved, the plurality of bumps in the semiconductor wafer surface can be favorably formed. Thereby, the reliability of the semiconductor device is improved.
  • the connection strength of the bumps is improved by using Pd as the material of the second conductor layer (in other words, the portion of the under-barrier metal film that joins the bumps) in the bump base conductor layer.
  • the bumps are favorably formed by improving the uniformity of the thickness of the bump base conductor layer. As a result, the reliability of the bumps is improved, and as a result, the reliability of the semiconductor device is improved.
  • the reliability of semiconductor devices is improved from the viewpoint of the material and thickness of the under-barrier metal film.
  • the side of the bump can be satisfactorily filled with sealing resin. Therefore, there is a problem in that the reliability of the semiconductor device is deteriorated.
  • the flux is used for bonding the bump to the under barrier metal film.
  • the sealing resin is filled between the mounting substrate and the semiconductor chip.
  • an object of the present invention is to prevent a residue of flux from remaining around a side portion of a bump in a semiconductor chip and a semiconductor device including the semiconductor chip.
  • the present invention is an invention made based on the knowledge found by the present inventors.
  • a semiconductor chip is formed on a substrate, an electrode pad formed on the substrate, and a peripheral portion of the substrate and the electrode pad.
  • a first protective film having a first opening exposing a central portion of the electrode pad; and a central portion of the electrode pad and a portion located at a periphery of the first opening in the first protective film.
  • the under barrier metal film formed and a bump formed on the under barrier metal film are provided.
  • the first protective film includes a substrate portion formed on the upper surface of the substrate, the side surface of the electrode pad, and the electrode pad.
  • a pad portion formed on a peripheral portion of the upper surface, a side portion in contact with the first protective film in the under barrier metal film, and a side portion in contact with the under barrier metal film in the bump are the first protective film Pad in Wherein the the are located on the outer surface.
  • the side portion of the under barrier metal film and the side portion of the bump are located on the outer surface of the pad portion in the first protective film.
  • the shape of the structure around the side of the bump is devised. For this reason, no gap is formed around the side of the bump so that the flux residue enters. Therefore, when removing the flux residue, the flux residue remaining around the bump side is effectively removed. Can be removed. For this reason, it is possible to prevent the flux residue from remaining around the sides of the bumps. Therefore, a highly reliable semiconductor chip can be realized.
  • the first protective film can prevent the electrode pad, the under barrier metal film, the bump, and the like from peeling from the semiconductor chip.
  • the side surface of the under barrier metal film is a tapered surface that extends downward from above, and the bump is formed to cover the side surface and the top surface of the under barrier metal film. preferable.
  • the semiconductor chip according to one aspect of the present invention preferably further includes a second protective film formed on the first protective film and having a second opening.
  • the second protective film is preferably made of polyimide.
  • the first protective film is preferably made of silicon nitride.
  • the electrode pads are preferably arranged in a lattice pattern.
  • a semiconductor device includes a semiconductor chip according to one aspect of the present invention and a mounting substrate on which the semiconductor chip is mounted, and is provided between the mounting substrate and the semiconductor chip. Is characterized by being filled with a sealing resin.
  • the side portion of the under barrier metal film and the side portion of the bump are located on the outer surface of the pad portion in the first protective film. For this reason, no gap is formed around the side of the bump so that the flux residue enters. Therefore, when removing the flux residue, the flux residue remaining around the bump side is effectively removed. Can be removed. For this reason, it is possible to prevent the flux residue from remaining around the sides of the bumps.
  • the sealing resin when the sealing resin is filled, the sealing resin can be satisfactorily filled around the side of the bump from which the flux residue has been effectively removed. For this reason, it is possible to prevent the sealing resin from being satisfactorily filled around the side of the bump and causing poor filling due to the flux residue remaining around the side of the bump.
  • the semiconductor chip according to the present invention it is possible to prevent the residue of flux from remaining around the sides of the bumps, so that a highly reliable semiconductor chip can be realized.
  • the semiconductor device of the present invention it is possible to prevent the residue of the flux from remaining around the side portion of the bump, so that the sealing resin can be satisfactorily filled around the side portion of the bump. Therefore, a highly reliable semiconductor device can be realized.
  • FIG. 1 is a cross-sectional view showing the structure of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 2 is a plan view showing the structure of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
  • 4A to 4D are cross-sectional views showing a method of manufacturing a semiconductor chip according to an embodiment of the present invention in the order of steps.
  • FIG. 5 is a cross-sectional view showing the structure of a semiconductor chip according to a comparative example.
  • FIG. 1 is a cross-sectional view showing the structure of a semiconductor chip according to an embodiment of the present invention.
  • FIG. 1 is a cross-sectional view taken along the line II shown in FIG. 2, and is a cross-sectional view showing the structure of one bump and its vicinity in the semiconductor chip.
  • FIG. 2 is a plan view showing the structure of a semiconductor chip according to an embodiment of the present invention.
  • the first and second protective films are not shown for the sake of simplicity.
  • an electrode pad 2 made of, for example, aluminum (Al) is formed on a substrate 1 made of, for example, silicon (Si).
  • a first protective film 3 made of, for example, silicon nitride (Si 3 N 4 ) is formed on the peripheral portions of the substrate 1 and the electrode pads 2.
  • the first protective film 3 is formed with a first opening 3o that exposes the central portion (portion other than the peripheral portion) of the electrode pad 2.
  • the first protective film 3 includes a substrate portion 3A formed on the upper surface of the substrate 1, and a pad portion 3B formed on the side surface of the electrode pad 2 and the peripheral portion on the upper surface of the electrode pad 2.
  • the substrate portion 3A in the first protective film 3 has an I-shaped cross section.
  • the pad portion 3B in the first protective film 3 has an L-shaped cross section.
  • the inner surface of the pad portion 3B in the first protective film 3 is exposed in the first opening 3o.
  • a second protective film 4 made of, for example, polyimide is formed on the first protective film 3.
  • a second opening 4 o is formed in the second protective film 4.
  • An under barrier metal (UBM) film 5 containing, for example, nickel (Ni) is formed on the central portion of the electrode pad 2 and the portion of the first protective film 3 located at the periphery of the first opening 3o. ing.
  • the side surface of the under barrier metal film 5 is a tapered surface that spreads from the top to the bottom.
  • the side portion 5 p in contact with the first protective film 3 in the under barrier metal film 5 is located on the outer surface S 3 B of the pad portion 3 B in the first protective film 3.
  • the “side surface” of the under barrier metal film 5 refers to the side surface of the portion other than the portion formed in the first opening 3 o in the under barrier metal film 5.
  • a bump 6 made of a solder material such as tin (Sn), silver (Ag), or copper (Cu) is formed on the under barrier metal film 5 via a flux (not shown).
  • the side portion 6p of the bump 6 that contacts the under barrier metal film 5 is located on the outer surface S3B of the pad portion 3B of the first protective film 3. In other words, the side portion 6 p of the bump 6 is located on the side portion 5 p of the under barrier metal film 5.
  • the bump 6 is formed so as to cover the side surface and the upper surface of the under barrier metal film 5.
  • a plurality of bumps 6 each connected to an electrode pad are arranged in a grid.
  • the planar shape of the bump 6 is circular.
  • FIG. 3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
  • the semiconductor chip according to the present embodiment is mounted on the mounting substrate 8 by flip chip mounting.
  • a sealing resin 7 made of, for example, an underfill is filled between the mounting substrate 8 and the semiconductor chip.
  • 4A to 4D are cross-sectional views showing a method of manufacturing a semiconductor chip according to an embodiment of the present invention in the order of steps.
  • an electrode pad 2 made of, for example, Al is formed on a substrate 1 made of, for example, Si.
  • a first protective film made of, for example, Si 3 N 4 is formed on the substrate 1 and the electrode pad 2.
  • the part formed on the center part of the electrode pad 2 in a 1st protective film is removed.
  • a first opening 3 o that exposes the central portion of the electrode pad 2 is formed in the first protective film 3.
  • the first protective film 3 having the substrate portion 3A formed on the upper surface of the substrate 1 and the pad portion 3B formed on the side surface of the electrode pad 2 and the peripheral portion on the upper surface of the electrode pad 2 is formed. To do.
  • a second protective film made of polyimide for example, is uniformly formed on the electrode pad 2 and the first protective film 3 by using, for example, a spinner (not shown). Apply to. Subsequently, for example, prebaking is performed at 70 ° C. for 50 seconds, 90 ° C. for 50 seconds, or 105 ° C. for 110 seconds. Thereafter, an opening pattern for forming the second opening 4o is exposed on the second protective film. Thereafter, baking is performed at 80 ° C. for 50 seconds, for example. Thereafter, development is performed.
  • the material of the second protective film is positive photosensitive polyimide
  • the exposed portion of the opening pattern in the second protective film is removed (or in the case of negative photosensitive polyimide).
  • the portion other than the portion where the opening pattern is exposed in the second protective film is removed).
  • curing is performed at 140 ° C. for 170 seconds or at 350 ° C. for 3600 seconds.
  • the second protective film 4 having the second opening 4o having the width W4o wider than the width W2 of the electrode pad 2 is formed.
  • the oxide film (not shown) formed on the upper surface of the electrode pad 2 is removed by, for example, soft etching. Thereafter, for example, zinc (Zn) particles (not shown) are deposited on the electrode pad 2 by immersion in a zincate treatment solution. Thereafter, for example, an Ni film having a thickness of about 5 ⁇ 10 ⁇ 3 mm is formed on the electrode pad 2 and the pad portion 3B of the first protective film 3 by immersion in an electroless nickel plating solution. In this way, the under barrier metal film 5 containing Ni is formed on the electrode pad 2 and the pad portion 3B in the first protective film 3.
  • the under barrier metal film 5 is formed so that the side part 5p of the under barrier metal film 5 is located on the outer surface S3B of the pad part 3B in the first protective film 3. At this time, the under barrier metal film 5 is formed so that the side surface of the under barrier metal film 5 becomes a tapered surface extending from the top to the bottom.
  • the thickness T5 of the under barrier metal film 5 is preferably about 1 ⁇ 10 ⁇ 3 mm to 7 ⁇ 10 ⁇ 3 mm, for example.
  • a metal printing mask having an opening corresponding to the under barrier metal film 5 and having a thickness of, for example, about 0.02 mm to 0.04 mm (not shown).
  • the flux (not shown) is printed on the under barrier metal film 5 by using, for example, a rubber or metal squeegee (not shown).
  • a ball-shaped bump is mounted on the under barrier metal film 5 via a flux using a mounting mask (not shown) having an opening corresponding to the under barrier metal film 5.
  • the bump is remelted (reflowed) by heat treatment, and the bump 6 is bonded to the under barrier metal 5 film.
  • the bumps 6 are formed on the under barrier metal film 5 via the flux by the ball mount method.
  • the bump 6 is formed so that the side portion 6p in contact with the under barrier metal film 5 in the bump 6 is located on the outer surface S3B of the pad portion 3B in the first protective film 3.
  • the bumps 6 are formed so that the side portions 6p of the bumps 6 are located on the side portions of the under barrier metal film 5 (see FIG. 4 (c): 5p).
  • the flux mainly has two functions of holding the bump and removing the oxide film during the reflow of the bump. For this reason, it is preferable to use, for example, a rosin flux or a water-soluble flux as the flux, and it is particularly preferable to use a halogen-free rosin flux.
  • the width W6 of the bump 6 is preferably about 0.07 mm to 0.125 mm, for example.
  • the average value of the width in the longitudinal direction and the width in the short direction of the bump is preferably about 0.07 mm to 0.125 mm, for example.
  • flux residue for example, flux residue remaining around the side portion 6p of the bump 6 is removed by cleaning.
  • the side portion 5p of the under barrier metal film 5 and the side portion 6p of the bump 6 are located on the outer surface S3B of the pad portion 3B in the first protective film 3.
  • a favorable space S can be secured around the side portion 6 p of the bump 6.
  • a gap s into which a flux residue enters is not formed between the pad portion 3 ⁇ / b> B and the bump 6 in the first protective film 3. For this reason, the residue of the flux remaining around the side portion 6p of the bump 6 can be effectively removed.
  • the semiconductor chip according to this embodiment can be manufactured.
  • a semiconductor chip is mounted on the mounting substrate 8. Thereafter, a sealing resin 7 made of, for example, an underfill is filled between the mounting substrate 8 and the semiconductor chip. At this time, the space from which the flux residue is effectively removed (see FIG. 4 (d): S) can be effectively filled with the sealing resin 7. d): The sealing resin 7 can be satisfactorily filled around 6p).
  • the side portion 5p of the under barrier metal film 5 and the side portion 6p of the bump 6 are located on the outer surface S3B of the pad portion 3B in the first protective film 3. Therefore, a gap (see FIG. 5: s) where flux residue enters around the side portion 6p of the bump 6 is not formed. Therefore, when the flux residue is removed, the side portion 6p of the bump 6 is removed. It is possible to effectively remove the residue of the flux remaining around. For this reason, it is possible to prevent the residue of the flux from remaining around the side portion 6p of the bump 6. Therefore, a highly reliable semiconductor chip can be realized.
  • the sealing resin 7 when the sealing resin is filled, the sealing resin 7 can be satisfactorily filled around the side portion 6p of the bump 6 from which the flux residue has been effectively removed. Therefore, it is possible to prevent the sealing resin 7 from being satisfactorily filled with the sealing resin 7 around the side portion 6p of the bump 6 due to the residual flux remaining around the side portion 6p of the bump 6. can do. Therefore, a highly reliable semiconductor device can be realized.
  • the first protective film 3 it is possible to prevent the electrode pad 2, the under barrier metal film 5, the bump 6, and the like from peeling from the semiconductor chip.
  • the second protective film 4 it is possible to further prevent the electrode pad 2, the under barrier metal film 5, the bump 6, and the like from peeling from the semiconductor chip.
  • a Ni film having a thickness of about 5 ⁇ 10 ⁇ 3 mm is formed by immersion in an electroless nickel plating solution, for example, and an underlayer containing Ni is formed.
  • an electroless nickel plating solution for example, and an underlayer containing Ni is formed.
  • a Ni film having a thickness of about 5 ⁇ 10 ⁇ 3 mm is formed by immersion in an electroless nickel plating solution.
  • a gold (Au) film having a thickness of about 5 ⁇ 10 ⁇ 5 mm is formed on the Ni film by immersion in an electroless gold plating solution, and an under barrier metal film containing Ni and Au is formed. May be. That is, after applying electroless nickel plating, so-called flash gold plating may be applied.
  • a resist pattern having openings corresponding to the electrode pads is formed on the substrate portion of the first protective film. Thereafter, using the resist pattern as a mask, a Ni film or the like is formed on the electrode pad exposed in the opening of the resist pattern and the pad portion of the first protective film by sputtering or vapor deposition, and an under barrier containing Ni or the like A metal film may be formed.
  • the bump 6 is formed on the under barrier metal film 5 by, for example, a ball mount method has been described as a specific example. Is not limited to this.
  • the bumps may be formed on the under barrier metal film by a plating method or a dispensing method.
  • polyimide used as the material of the second protective film 4
  • benzoxazole or a silicone-based resin may be used. Good.
  • the present invention can prevent the residue of flux from remaining around the sides of the bumps, and is useful for a semiconductor chip and a semiconductor device including the semiconductor chip.

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Abstract

Disclosed is a semiconductor device provided with a semiconductor chip and a mounting substrate (8). A sealing resin (7) is filled between the mounting substrate and the semiconductor chip. The semiconductor chip is provided with: a substrate (1); an electrode pad (2) formed on the substrate; a first protective film (3) which is formed on the peripheral section of the substrate and the electrode pad, and has a first opening (3o) for exposing the center section of the electrode pad; an under-barrier metal film (5) formed on the center section of the electrode pad and on the portion positioned at the periphery of the first opening in the first protective film; and a bump (6) formed on the under-barrier metal film. The first protective film has a substrate section (3A) formed at the top surface of the substrate, and a pad section (3B) formed at the peripheral section at the side surface of the electrode pad and the top surface of the electrode pad. A side section (5p), which is in the under-barrier metal film and is in contact with the first protective film, and a side section (6p), which is in the bump and is in contact with the under-barrier metal film, are positioned on the outside surface (S3B) of the pad section in the first protective film.

Description

半導体チップ及び該半導体チップを備えた半導体装置Semiconductor chip and semiconductor device provided with the semiconductor chip
　本発明は、アンダーバリアメタル膜及びバンプを有する半導体チップ、並びに該半導体チップを備えた半導体装置に関する。 The present invention relates to a semiconductor chip having an under barrier metal film and a bump, and a semiconductor device including the semiconductor chip.
　実装基板に半導体チップを実装する実装方法として、フリップチップ実装がある。フリップチップ実装とは、半導体チップのバンプと、実装基板とを電気的に接続する実装方法である。バンプは、アンダーバリアメタル膜の上に形成されている。 There is a flip chip mounting as a mounting method for mounting a semiconductor chip on a mounting substrate. Flip chip mounting is a mounting method in which bumps of a semiconductor chip and a mounting substrate are electrically connected. The bump is formed on the under barrier metal film.
　バンプのアンダーバリアメタル膜への接続強度を向上させる技術として、以下に示す技術が提案されている（例えば、特許文献１を参照）。 The following technique has been proposed as a technique for improving the connection strength of the bump to the under barrier metal film (see, for example, Patent Document 1).
　従来の半導体装置は、基板の上に形成された引出し電極と、引出し電極の上に形成されたバンプ下地導体層（＝アンダーバリアメタル膜）と、バンプ下地導体層の上に形成され錫を含有するバンプとを備えている。バンプ下地導体層は、引出し電極の上に形成されチタン（Ｔｉ）又はチタン合金からなる第１の導体層と、第１の導体層の上に形成されパラジウム（Ｐｄ）を含有する第２の導体層とを有している。 A conventional semiconductor device includes a lead electrode formed on a substrate, a bump base conductor layer (= under barrier metal film) formed on the lead electrode, and tin formed on the bump base conductor layer. It has a bump to do. The bump base conductor layer is formed of a first conductor layer made of titanium (Ti) or a titanium alloy formed on the extraction electrode, and a second conductor formed on the first conductor layer and containing palladium (Pd). And have a layer.
　従来では、バンプ下地導体層における第２の導体層の材料を、従来の銅（Ｃｕ）に代えてＰｄとする。これにより、第２の導体層の材料をＣｕとした場合のように第２の導体層とバンプとの接合領域にＣｕ－Ｓｎのような脆い合金層が形成されることがないので、バンプの接続強度を向上させることが可能となる。このため、バンプが剥離することを抑制することができる。これにより、半導体装置の信頼性の向上を図る。 Conventionally, the material of the second conductor layer in the bump base conductor layer is Pd instead of conventional copper (Cu). As a result, a brittle alloy layer such as Cu—Sn is not formed in the joint region between the second conductor layer and the bump as in the case where the material of the second conductor layer is Cu. Connection strength can be improved. For this reason, it can suppress that a bump peels. Thereby, the reliability of the semiconductor device is improved.
　また、従来では、バンプ下地導体層を、スパッタリング法によって形成する。これにより、半導体ウエハの面内におけるバンプ下地導体層の厚さの均一性を向上させることが可能となる。このため、半導体ウエハ面内における複数のバンプの形成条件の均一性を向上させることができるので、半導体ウエハ面内における複数のバンプを良好に形成することができる。これにより、半導体装置の信頼性の向上を図る。 Conventionally, the bump base conductor layer is formed by a sputtering method. This makes it possible to improve the uniformity of the thickness of the bump base conductor layer in the plane of the semiconductor wafer. For this reason, since the uniformity of the formation conditions of the plurality of bumps in the semiconductor wafer surface can be improved, the plurality of bumps in the semiconductor wafer surface can be favorably formed. Thereby, the reliability of the semiconductor device is improved.
　このように、従来では、バンプ下地導体層における第２の導体層（言い換えれば、アンダーバリアメタル膜におけるバンプと接合する部分）の材料をＰｄとすることにより、バンプの接続強度を向上させる。また、バンプ下地導体層の厚さの均一性を向上させることにより、バンプを良好に形成する。これにより、バンプの信頼性の向上を図り、延いては、半導体装置の信頼性の向上を図る。 Thus, conventionally, the connection strength of the bumps is improved by using Pd as the material of the second conductor layer (in other words, the portion of the under-barrier metal film that joins the bumps) in the bump base conductor layer. Further, the bumps are favorably formed by improving the uniformity of the thickness of the bump base conductor layer. As a result, the reliability of the bumps is improved, and as a result, the reliability of the semiconductor device is improved.
特開平１０－２３３３９９号公報Japanese Patent Laid-Open No. 10-233399
　しかしながら、従来では、以下に示す問題がある。 However, conventionally, there are the following problems.
　従来では、アンダーバリアメタル膜の材料及び厚さという観点から、半導体装置の信頼性の向上を図る。 Conventionally, the reliability of semiconductor devices is improved from the viewpoint of the material and thickness of the under-barrier metal film.
　しかしながら、本願発明者が検討を重ねた結果、以下のことを見出した。 However, as a result of repeated studies by the present inventor, the following has been found.
　バンプにおけるアンダーバリアメタル膜と接触する側部（後述の図１：６ｐ参照）の周囲に、フラックスの残渣が残留すると、バンプの側部の周囲に、封止樹脂を良好に充填することができずに充填不良を招くため、半導体装置の信頼性の低下を招くという問題がある。ここで、フラックスは、バンプをアンダーバリアメタル膜に接合する為に用いられる。またここで、封止樹脂は、実装基板と半導体チップとの間に充填される。 If flux residue remains around the side of the bump that contacts the under-barrier metal film (see FIG. 1: 6p described later), the side of the bump can be satisfactorily filled with sealing resin. Therefore, there is a problem in that the reliability of the semiconductor device is deteriorated. Here, the flux is used for bonding the bump to the under barrier metal film. Here, the sealing resin is filled between the mounting substrate and the semiconductor chip.
　前記の問題に鑑み、本発明の目的は、半導体チップ及び該半導体チップを備えた半導体装置において、バンプの側部の周囲に、フラックスの残渣が残留することを防止することである。 In view of the above problems, an object of the present invention is to prevent a residue of flux from remaining around a side portion of a bump in a semiconductor chip and a semiconductor device including the semiconductor chip.
　本願発明者が検討を重ねた結果、バンプの側部の周囲に、フラックスの残渣が残留することを防止するには、バンプの側部の周囲の構造の形状を工夫することが有効であることを見出した。本願発明は、本願発明者が見出した知見に基づいて成された発明である。 As a result of repeated studies by the inventors of the present application, it is effective to devise the shape of the structure around the side of the bump in order to prevent the residue of the flux from remaining around the side of the bump. I found. The present invention is an invention made based on the knowledge found by the present inventors.
　具体的には、前記の目的を達成するため、本発明の一側面に係る半導体チップは、基板と、基板の上に形成された電極パッドと、基板及び電極パッドの周縁部の上に形成され、電極パッドの中央部を露出する第１の開口部を有する第１の保護膜と、電極パッドの中央部、及び第１の保護膜における第１の開口部の周縁に位置する部分の上に形成されたアンダーバリアメタル膜と、アンダーバリアメタル膜の上に形成されたバンプとを備え、第１の保護膜は、基板の上面に形成された基板部と、電極パッドの側面及び電極パッドの上面における周縁部に形成されたパッド部とを有し、アンダーバリアメタル膜における第１の保護膜と接触する側部、及びバンプにおけるアンダーバリアメタル膜と接触する側部が、第１の保護膜におけるパッド部の外側面上に位置していることを特徴とする。 Specifically, in order to achieve the above object, a semiconductor chip according to one aspect of the present invention is formed on a substrate, an electrode pad formed on the substrate, and a peripheral portion of the substrate and the electrode pad. A first protective film having a first opening exposing a central portion of the electrode pad; and a central portion of the electrode pad and a portion located at a periphery of the first opening in the first protective film. The under barrier metal film formed and a bump formed on the under barrier metal film are provided. The first protective film includes a substrate portion formed on the upper surface of the substrate, the side surface of the electrode pad, and the electrode pad. A pad portion formed on a peripheral portion of the upper surface, a side portion in contact with the first protective film in the under barrier metal film, and a side portion in contact with the under barrier metal film in the bump are the first protective film Pad in Wherein the the are located on the outer surface.
　本発明の一側面に係る半導体チップによると、アンダーバリアメタル膜の側部及びバンプの側部が、第１の保護膜におけるパッド部の外側面上に位置している。言い換えれば、バンプの側部の周囲の構造の形状を工夫している。このため、バンプの側部の周囲に、フラックスの残渣が入り込む間隙が形成されることがないため、フラックスの残渣の除去の際に、バンプの側部の周囲に残留するフラックスの残渣を効果的に除去することができる。このため、バンプの側部の周囲に、フラックスの残渣が残留することを防止することができる。従って、信頼性が高い半導体チップを実現することができる。 According to the semiconductor chip according to one aspect of the present invention, the side portion of the under barrier metal film and the side portion of the bump are located on the outer surface of the pad portion in the first protective film. In other words, the shape of the structure around the side of the bump is devised. For this reason, no gap is formed around the side of the bump so that the flux residue enters. Therefore, when removing the flux residue, the flux residue remaining around the bump side is effectively removed. Can be removed. For this reason, it is possible to prevent the flux residue from remaining around the sides of the bumps. Therefore, a highly reliable semiconductor chip can be realized.
　さらに、第１の保護膜により、電極パッド、アンダーバリアメタル膜及びバンプ等が、半導体チップから剥離することを防止することができる。 Furthermore, the first protective film can prevent the electrode pad, the under barrier metal film, the bump, and the like from peeling from the semiconductor chip.
　本発明の一側面に係る半導体チップにおいて、アンダーバリアメタル膜の側面は、上方から下方に広がるテーパー面であり、バンプは、アンダーバリアメタル膜の側面及び上面を覆うように形成されていることが好ましい。 In the semiconductor chip according to one aspect of the present invention, the side surface of the under barrier metal film is a tapered surface that extends downward from above, and the bump is formed to cover the side surface and the top surface of the under barrier metal film. preferable.
　本発明の一側面に係る半導体チップにおいて、第１保護膜の上に形成され、第２の開口部を有する第２の保護膜をさらに備えていることが好ましい。 The semiconductor chip according to one aspect of the present invention preferably further includes a second protective film formed on the first protective film and having a second opening.
　このようにすると、電極パッド、アンダーバリアメタル膜及びバンプ等が、半導体チップから剥離することをさらに防止することができる。 In this way, it is possible to further prevent the electrode pad, the under barrier metal film, the bump and the like from being peeled off from the semiconductor chip.
　本発明の一側面に係る半導体チップにおいて、第２の保護膜は、ポリイミドからなることが好ましい。 In the semiconductor chip according to one aspect of the present invention, the second protective film is preferably made of polyimide.
　本発明の一側面に係る半導体チップにおいて、第１の保護膜は、窒化ケイ素からなることが好ましい。 In the semiconductor chip according to one aspect of the present invention, the first protective film is preferably made of silicon nitride.
　本発明の一側面に係る半導体チップにおいて、電極パッドは、格子状に配列されていることが好ましい。 In the semiconductor chip according to one aspect of the present invention, the electrode pads are preferably arranged in a lattice pattern.
　このように、電極パッドと接続するバンプが、格子状に配列されて、ピッチ（隣り合うバンプの中心部同士の間隔）が狭くても、フラックスの残渣の除去の際に、バンプの側部の周囲に残留するフラックスの残渣を効果的に除去することができる。 In this way, even when the bumps connected to the electrode pads are arranged in a grid pattern and the pitch (the distance between the central portions of adjacent bumps) is narrow, the side of the bumps are removed when the flux residue is removed. The residue of the flux remaining around can be effectively removed.
　前記の目的を達成するため、本発明の一側面に係る半導体装置は、本発明の一側面に係る半導体チップと、半導体チップが実装された実装基板とを備え、実装基板と半導体チップとの間には、封止樹脂が充填されていることを特徴とする。 In order to achieve the above object, a semiconductor device according to one aspect of the present invention includes a semiconductor chip according to one aspect of the present invention and a mounting substrate on which the semiconductor chip is mounted, and is provided between the mounting substrate and the semiconductor chip. Is characterized by being filled with a sealing resin.
　本発明の一側面に係る半導体装置によると、アンダーバリアメタル膜の側部及びバンプの側部が、第１の保護膜におけるパッド部の外側面上に位置している。このため、バンプの側部の周囲に、フラックスの残渣が入り込む間隙が形成されることがないため、フラックスの残渣の除去の際に、バンプの側部の周囲に残留するフラックスの残渣を効果的に除去することができる。このため、バンプの側部の周囲に、フラックスの残渣が残留することを防止することができる。 According to the semiconductor device of one aspect of the present invention, the side portion of the under barrier metal film and the side portion of the bump are located on the outer surface of the pad portion in the first protective film. For this reason, no gap is formed around the side of the bump so that the flux residue enters. Therefore, when removing the flux residue, the flux residue remaining around the bump side is effectively removed. Can be removed. For this reason, it is possible to prevent the flux residue from remaining around the sides of the bumps.
　加えて、封止樹脂の充填の際に、フラックスの残渣が効果的に除去されたバンプの側部の周囲に、封止樹脂を良好に充填することができる。このため、バンプの側部の周囲に残留するフラックスの残渣により、バンプの側部の周囲に、封止樹脂を良好に充填することができずに充填不良を招くことを防止することができる。 In addition, when the sealing resin is filled, the sealing resin can be satisfactorily filled around the side of the bump from which the flux residue has been effectively removed. For this reason, it is possible to prevent the sealing resin from being satisfactorily filled around the side of the bump and causing poor filling due to the flux residue remaining around the side of the bump.
　従って、信頼性が高い半導体装置を実現することができる。 Therefore, a highly reliable semiconductor device can be realized.
　本発明に係る半導体チップによると、バンプの側部の周囲に、フラックスの残渣が残留することを防止することができるため、信頼性が高い半導体チップを実現することができる。 According to the semiconductor chip according to the present invention, it is possible to prevent the residue of flux from remaining around the sides of the bumps, so that a highly reliable semiconductor chip can be realized.
　本発明に係る半導体装置によると、バンプの側部の周囲に、フラックスの残渣が残留することを防止することができるため、バンプの側部の周囲に、封止樹脂を良好に充填することができるので、信頼性が高い半導体装置を実現することができる。 According to the semiconductor device of the present invention, it is possible to prevent the residue of the flux from remaining around the side portion of the bump, so that the sealing resin can be satisfactorily filled around the side portion of the bump. Therefore, a highly reliable semiconductor device can be realized.
図１は、本発明の一実施形態に係る半導体チップの構造を示す断面図である。FIG. 1 is a cross-sectional view showing the structure of a semiconductor chip according to an embodiment of the present invention. 図２は、本発明の一実施形態に係る半導体チップの構造を示す平面図である。FIG. 2 is a plan view showing the structure of a semiconductor chip according to an embodiment of the present invention. 図３は、本発明の一実施形態に係る半導体装置の構造を示す断面図である。FIG. 3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention. 図４(a) ～(d) は、本発明の一実施形態に係る半導体チップの製造方法を工程順に示す断面図である。4A to 4D are cross-sectional views showing a method of manufacturing a semiconductor chip according to an embodiment of the present invention in the order of steps. 図５は、比較例に係る半導体チップの構造を示す断面図である。FIG. 5 is a cross-sectional view showing the structure of a semiconductor chip according to a comparative example.
　以下に、本発明の一実施形態について図面を参照しながら説明する。 Hereinafter, an embodiment of the present invention will be described with reference to the drawings.
　（一実施形態）
　以下に、本発明の一実施形態に係る半導体チップの構造について、図１及び図２を参照しながら説明する。図１は、本発明の一実施形態に係る半導体チップの構造を示す断面図である。具体的には、図１は、図２に示すI-I線における断面図であり、該半導体チップにおける、１コのバンプ及びその近傍部分の構造を示す断面図である。図２は、本発明の一実施形態に係る半導体チップの構造を示す平面図である。なお、図２において、簡略的に図示する為に、第１，第２の保護膜の図示を省略している。 (One embodiment)
The structure of the semiconductor chip according to one embodiment of the present invention will be described below with reference to FIGS. FIG. 1 is a cross-sectional view showing the structure of a semiconductor chip according to an embodiment of the present invention. Specifically, FIG. 1 is a cross-sectional view taken along the line II shown in FIG. 2, and is a cross-sectional view showing the structure of one bump and its vicinity in the semiconductor chip. FIG. 2 is a plan view showing the structure of a semiconductor chip according to an embodiment of the present invention. In FIG. 2, the first and second protective films are not shown for the sake of simplicity.
　図１に示すように、例えばシリコン（Ｓｉ）からなる基板１の上には、例えばアルミニウム（Ａｌ）からなる電極パッド２が形成されている。基板１及び電極パッド２の周縁部の上には、例えば窒化ケイ素（Ｓｉ3Ｎ4）からなる第１の保護膜３が形成されている。第１の保護膜３には、電極パッド２の中央部（周縁部以外の部分）を露出する第１の開口部３ｏが形成されている。第１の保護膜３は、基板１の上面に形成された基板部３Ａと、電極パッド２の側面及び電極パッド２の上面における周縁部に形成されたパッド部３Ｂとを有している。第１の保護膜３における基板部３Ａは、断面形状がＩ字状である。第１の保護膜３におけるパッド部３Ｂは、断面形状がＬ字状である。第１の保護膜３におけるパッド部３Ｂの内側面は、第１の開口部３ｏ内に露出している。 As shown in FIG. 1, an electrode pad 2 made of, for example, aluminum (Al) is formed on a substrate 1 made of, for example, silicon (Si). A first protective film 3 made of, for example, silicon nitride (Si 3 N 4 ) is formed on the peripheral portions of the substrate 1 and the electrode pads 2. The first protective film 3 is formed with a first opening 3o that exposes the central portion (portion other than the peripheral portion) of the electrode pad 2. The first protective film 3 includes a substrate portion 3A formed on the upper surface of the substrate 1, and a pad portion 3B formed on the side surface of the electrode pad 2 and the peripheral portion on the upper surface of the electrode pad 2. The substrate portion 3A in the first protective film 3 has an I-shaped cross section. The pad portion 3B in the first protective film 3 has an L-shaped cross section. The inner surface of the pad portion 3B in the first protective film 3 is exposed in the first opening 3o.
　第１保護膜３の上には、例えばポリイミドからなる第２の保護膜４が形成されている。第２の保護膜４には、第２の開口部４ｏが形成されている。 A second protective film 4 made of, for example, polyimide is formed on the first protective film 3. A second opening 4 o is formed in the second protective film 4.
　電極パッド２の中央部、及び第１の保護膜３における第１の開口部３ｏの周縁に位置する部分の上には、例えばニッケル（Ｎｉ）を含むアンダーバリアメタル（ＵＢＭ）膜５が形成されている。アンダーバリアメタル膜５の側面は、上方から下方に広がるテーパー面である。アンダーバリアメタル膜５における第１の保護膜３と接触する側部５ｐは、第１の保護膜３におけるパッド部３Ｂの外側面Ｓ3B上に位置している。ここで、アンダーバリアメタル膜５の「側面」とは、アンダーバリアメタル膜５における第１の開口部３ｏ内に形成された部分以外の部分の側面をいう。 An under barrier metal (UBM) film 5 containing, for example, nickel (Ni) is formed on the central portion of the electrode pad 2 and the portion of the first protective film 3 located at the periphery of the first opening 3o. ing. The side surface of the under barrier metal film 5 is a tapered surface that spreads from the top to the bottom. The side portion 5 p in contact with the first protective film 3 in the under barrier metal film 5 is located on the outer surface S 3 B of the pad portion 3 B in the first protective film 3. Here, the “side surface” of the under barrier metal film 5 refers to the side surface of the portion other than the portion formed in the first opening 3 o in the under barrier metal film 5.
　アンダーバリアメタル膜５の上には、フラックス（図示省略）を介して、例えば錫（Ｓｎ）、銀（Ａｇ）又は銅（Ｃｕ）等のはんだ材料からなるバンプ６が形成されている。バンプ６におけるアンダーバリアメタル膜５と接触する側部６ｐは、第１の保護膜３におけるパッド部３Ｂの外側面Ｓ3B上に位置している。言い換えれば、バンプ６の側部６ｐは、アンダーバリアメタル膜５の側部５ｐに位置している。バンプ６は、アンダーバリアメタル膜５の側面及び上面を覆うように形成されている。 A bump 6 made of a solder material such as tin (Sn), silver (Ag), or copper (Cu) is formed on the under barrier metal film 5 via a flux (not shown). The side portion 6p of the bump 6 that contacts the under barrier metal film 5 is located on the outer surface S3B of the pad portion 3B of the first protective film 3. In other words, the side portion 6 p of the bump 6 is located on the side portion 5 p of the under barrier metal film 5. The bump 6 is formed so as to cover the side surface and the upper surface of the under barrier metal film 5.
　図２に示すように、基板１の上には、各々が電極パッドと接続する複数のバンプ６が、グリッド状に配列されている。バンプ６の平面形状は、円形状である。 As shown in FIG. 2, on the substrate 1, a plurality of bumps 6 each connected to an electrode pad are arranged in a grid. The planar shape of the bump 6 is circular.
　以下に、本発明の一実施形態に係る半導体装置、言い換えれば、本実施形態に係る半導体チップを備えた半導体装置の構造について、図３を参照しながら説明する。図３は、本発明の一実施形態に係る半導体装置の構造を示す断面図である。 Hereinafter, the structure of the semiconductor device according to the embodiment of the present invention, in other words, the semiconductor device including the semiconductor chip according to the embodiment will be described with reference to FIG. FIG. 3 is a cross-sectional view showing the structure of a semiconductor device according to an embodiment of the present invention.
　図３に示すように、フリップチップ実装により、実装基板８の上には、本実施形態に係る半導体チップが実装されている。実装基板８と半導体チップとの間には、例えばアンダーフィルからなる封止樹脂７が充填されている。 As shown in FIG. 3, the semiconductor chip according to the present embodiment is mounted on the mounting substrate 8 by flip chip mounting. A sealing resin 7 made of, for example, an underfill is filled between the mounting substrate 8 and the semiconductor chip.
　以下に、本発明の一実施形態に係る半導体チップの製造方法について、図４(a) ～(d) を参照しながら説明する。図４(a) ～(d) は、本発明の一実施形態に係る半導体チップの製造方法を工程順に示す断面図である。 Hereinafter, a semiconductor chip manufacturing method according to an embodiment of the present invention will be described with reference to FIGS. 4 (a) to 4 (d). 4A to 4D are cross-sectional views showing a method of manufacturing a semiconductor chip according to an embodiment of the present invention in the order of steps.
　まず、図４(a) に示すように、例えばＳｉからなる基板１の上に、例えばＡｌ等からなる電極パッド２を形成する。その後、基板１及び電極パッド２の上に、例えばＳｉ3Ｎ4等からなる第１の保護膜を形成する。その後、第１の保護膜における電極パッド２の中央部の上に形成された部分を除去する。これにより、第１の保護膜３に、電極パッド２の中央部を露出する第１の開口部３ｏを形成する。このようにして、基板１の上面に形成された基板部３Ａと、電極パッド２の側面及び電極パッド２の上面における周縁部に形成されたパッド部３Ｂとを有する第１の保護膜３を形成する。 First, as shown in FIG. 4A, an electrode pad 2 made of, for example, Al is formed on a substrate 1 made of, for example, Si. Thereafter, a first protective film made of, for example, Si 3 N 4 is formed on the substrate 1 and the electrode pad 2. Then, the part formed on the center part of the electrode pad 2 in a 1st protective film is removed. As a result, a first opening 3 o that exposes the central portion of the electrode pad 2 is formed in the first protective film 3. In this way, the first protective film 3 having the substrate portion 3A formed on the upper surface of the substrate 1 and the pad portion 3B formed on the side surface of the electrode pad 2 and the peripheral portion on the upper surface of the electrode pad 2 is formed. To do.
　次に、図４(b) に示すように、例えばスピンナ（図示省略）を用いて、電極パッド２及び第１の保護膜３の上に、例えばポリイミドからなる第２の保護膜用膜を均一に塗布する。続いて、例えば７０℃で５０秒間、９０℃で５０秒間又は１０５℃で１１０秒間、プリベークを行う。その後、第２の保護膜用膜に、第２の開口部４ｏを形成する為の開口パターンを露光する。その後、例えば８０℃で５０秒間、ベークを行う。その後、現像を行う。これにより、第２の保護膜用膜の材料が、ポジ型感光性ポリイミドの場合、第２の保護膜用膜における、開口パターンが露光された部分を除去する（又はネガ型感光性ポリイミドの場合、第２の保護膜用膜における、開口パターンが露光された部分以外の部分を除去する）。その後、例えば１４０℃で１７０秒間又は３５０℃で３６００秒間、キュアを行う。このようにして、電極パッド２の幅Ｗ2よりも広い幅Ｗ4oを持つ第２の開口部４ｏを有する第２の保護膜４を形成する。 Next, as shown in FIG. 4B, a second protective film made of polyimide, for example, is uniformly formed on the electrode pad 2 and the first protective film 3 by using, for example, a spinner (not shown). Apply to. Subsequently, for example, prebaking is performed at 70 ° C. for 50 seconds, 90 ° C. for 50 seconds, or 105 ° C. for 110 seconds. Thereafter, an opening pattern for forming the second opening 4o is exposed on the second protective film. Thereafter, baking is performed at 80 ° C. for 50 seconds, for example. Thereafter, development is performed. Thereby, when the material of the second protective film is positive photosensitive polyimide, the exposed portion of the opening pattern in the second protective film is removed (or in the case of negative photosensitive polyimide). The portion other than the portion where the opening pattern is exposed in the second protective film is removed). Thereafter, for example, curing is performed at 140 ° C. for 170 seconds or at 350 ° C. for 3600 seconds. In this way, the second protective film 4 having the second opening 4o having the width W4o wider than the width W2 of the electrode pad 2 is formed.
　次に、図４(c) に示すように、例えばソフトエッチングにより、電極パッド２の上面に形成された酸化膜（図示省略）を除去する。その後、例えばジンケート処理液への浸漬により、電極パッド２の上に、亜鉛（Ｚｎ）粒子（図示省略）を析出させる。その後、例えば無電解ニッケルめっき液への浸漬により、電極パッド２及び第１の保護膜３におけるパッド部３Ｂの上に、例えば厚さが５×１０-3ｍｍ程度のＮｉ膜を形成する。このようにして、電極パッド２及び第１の保護膜３におけるパッド部３Ｂの上に、Ｎｉを含むアンダーバリアメタル膜５を形成する。このとき、アンダーバリアメタル膜５の側部５ｐが、第１の保護膜３におけるパッド部３Ｂの外側面Ｓ3B上に位置するように、アンダーバリアメタル膜５を形成する。またこのとき、アンダーバリアメタル膜５の側面が、上方から下方に広がるテーパー面となるように、アンダーバリアメタル膜５を形成する。アンダーバリアメタル膜５の厚さＴ5は、例えば１×１０-3ｍｍ～７×１０-3ｍｍ程度であることが好ましい。 Next, as shown in FIG. 4C, the oxide film (not shown) formed on the upper surface of the electrode pad 2 is removed by, for example, soft etching. Thereafter, for example, zinc (Zn) particles (not shown) are deposited on the electrode pad 2 by immersion in a zincate treatment solution. Thereafter, for example, an Ni film having a thickness of about 5 × 10 −3 mm is formed on the electrode pad 2 and the pad portion 3B of the first protective film 3 by immersion in an electroless nickel plating solution. In this way, the under barrier metal film 5 containing Ni is formed on the electrode pad 2 and the pad portion 3B in the first protective film 3. At this time, the under barrier metal film 5 is formed so that the side part 5p of the under barrier metal film 5 is located on the outer surface S3B of the pad part 3B in the first protective film 3. At this time, the under barrier metal film 5 is formed so that the side surface of the under barrier metal film 5 becomes a tapered surface extending from the top to the bottom. The thickness T5 of the under barrier metal film 5 is preferably about 1 × 10 −3 mm to 7 × 10 −3 mm, for example.
　次に、図４(d) に示すように、アンダーバリアメタル膜５と対応する開口部を有し且つ厚さが例えば０．０２ｍｍ～０．０４ｍｍ程度の金属製の印刷用マスク（図示省略）を用いて、例えばゴム製又は金属製のスキージ（図示省略）により、アンダーバリアメタル膜５の上に、フラックス（図示省略）を印刷する。その後、アンダーバリアメタル膜５と対応する開口部を有する搭載用マスク（図示省略）を用いて、アンダーバリアメタル膜５の上に、フラックスを介して、例えばボール形状のバンプを搭載する。その後、熱処理により、バンプを再溶融（リフロー）し、バンプ６をアンダーバリアメタル５膜に接合する。このように、ボールマウント法により、アンダーバリアメタル膜５の上に、フラックスを介して、バンプ６を形成する。このとき、バンプ６におけるアンダーバリアメタル膜５と接触する側部６ｐが、第１の保護膜３におけるパッド部３Ｂの外側面Ｓ3B上に位置するように、バンプ６を形成する。言い換えれば、バンプ６の側部６ｐが、アンダーバリアメタル膜５の側部（図４(c)：５ｐ参照）に位置するように、バンプ６を形成する。 Next, as shown in FIG. 4D, a metal printing mask having an opening corresponding to the under barrier metal film 5 and having a thickness of, for example, about 0.02 mm to 0.04 mm (not shown). The flux (not shown) is printed on the under barrier metal film 5 by using, for example, a rubber or metal squeegee (not shown). Thereafter, for example, a ball-shaped bump is mounted on the under barrier metal film 5 via a flux using a mounting mask (not shown) having an opening corresponding to the under barrier metal film 5. Thereafter, the bump is remelted (reflowed) by heat treatment, and the bump 6 is bonded to the under barrier metal 5 film. Thus, the bumps 6 are formed on the under barrier metal film 5 via the flux by the ball mount method. At this time, the bump 6 is formed so that the side portion 6p in contact with the under barrier metal film 5 in the bump 6 is located on the outer surface S3B of the pad portion 3B in the first protective film 3. In other words, the bumps 6 are formed so that the side portions 6p of the bumps 6 are located on the side portions of the under barrier metal film 5 (see FIG. 4 (c): 5p).
　ここで、フラックスは、バンプの保持、及びバンプのリフロー時での酸化膜の除去という２つの機能を主に有する。このため、フラックスとして、例えばロジン系フラックス又は水溶性フラックス等を用いることが好ましく、特に、ハロゲンフリータイプのロジン系フラックスを用いることが好ましい。 Here, the flux mainly has two functions of holding the bump and removing the oxide film during the reflow of the bump. For this reason, it is preferable to use, for example, a rosin flux or a water-soluble flux as the flux, and it is particularly preferable to use a halogen-free rosin flux.
　またここで、バンプ６の材料として、例えばＳｎ、Ａｇ又はＣｕ等のはんだ材料を用いることが好ましい。バンプ６の形状がボール形状である場合、バンプ６の幅Ｗ6は、例えば０．０７ｍｍ～０．１２５ｍｍ程度であることが好ましい。また、バンプの形状が方形状である場合、バンプの長手方向の幅と短手方向の幅との平均値が、例えば０．０７ｍｍ～０．１２５ｍｍ程度であることが好ましい。 Here, it is preferable to use a solder material such as Sn, Ag or Cu as the material of the bump 6. When the shape of the bump 6 is a ball shape, the width W6 of the bump 6 is preferably about 0.07 mm to 0.125 mm, for example. Further, when the shape of the bump is a square shape, the average value of the width in the longitudinal direction and the width in the short direction of the bump is preferably about 0.07 mm to 0.125 mm, for example.
　次に、洗浄により、フラックスの残渣、例えば、バンプ６の側部６ｐの周囲に残留するフラックスの残渣を除去する。このとき、アンダーバリアメタル膜５の側部５ｐ及びバンプ６の側部６ｐが、第１の保護膜３におけるパッド部３Ｂの外側面Ｓ3B上に位置している。このため、バンプ６の側部６ｐの周囲に、良好な空間Ｓを確保することができる。言い換えれば、図５に示すように、例えば、第１の保護膜３におけるパッド部３Ｂとバンプ６との間に、フラックスの残渣が入り込む間隙ｓが形成されることがない。このため、バンプ６の側部６ｐの周囲に残留するフラックスの残渣を効果的に除去することができる。 Next, flux residue, for example, flux residue remaining around the side portion 6p of the bump 6 is removed by cleaning. At this time, the side portion 5p of the under barrier metal film 5 and the side portion 6p of the bump 6 are located on the outer surface S3B of the pad portion 3B in the first protective film 3. For this reason, a favorable space S can be secured around the side portion 6 p of the bump 6. In other words, as shown in FIG. 5, for example, a gap s into which a flux residue enters is not formed between the pad portion 3 </ b> B and the bump 6 in the first protective film 3. For this reason, the residue of the flux remaining around the side portion 6p of the bump 6 can be effectively removed.
　以上のようにして、本実施形態に係る半導体チップを製造することができる。 As described above, the semiconductor chip according to this embodiment can be manufactured.
　以下に、本発明の一実施形態に係る半導体装置の製造方法について、図３を参照しながら説明する。 Hereinafter, a method for manufacturing a semiconductor device according to an embodiment of the present invention will be described with reference to FIG.
　まず、図３に示すように、実装基板８の上に、半導体チップを実装する。その後、実装基板８と半導体チップとの間に、例えばアンダーフィルからなる封止樹脂７を充填する。このとき、フラックスの残渣が効果的に除去された空間（図４(d)：Ｓ参照）に、封止樹脂７を効果的に充填することができるため、バンプ６の側部（図４(d)：６ｐ参照）の周囲に、封止樹脂７を良好に充填することができる。 First, as shown in FIG. 3, a semiconductor chip is mounted on the mounting substrate 8. Thereafter, a sealing resin 7 made of, for example, an underfill is filled between the mounting substrate 8 and the semiconductor chip. At this time, the space from which the flux residue is effectively removed (see FIG. 4 (d): S) can be effectively filled with the sealing resin 7. d): The sealing resin 7 can be satisfactorily filled around 6p).
　本実施形態によると、アンダーバリアメタル膜５の側部５ｐ及びバンプ６の側部６ｐが、第１の保護膜３におけるパッド部３Ｂの外側面Ｓ3B上に位置している。このため、バンプ６の側部６ｐの周囲に、フラックスの残渣が入り込む間隙（図５：ｓ参照）が形成されることがないため、フラックスの残渣の除去の際に、バンプ６の側部６ｐの周囲に残留するフラックスの残渣を効果的に除去することができる。このため、バンプ６の側部６ｐの周囲に、フラックスの残渣が残留することを防止することができる。従って、信頼性が高い半導体チップを実現することができる。 According to this embodiment, the side portion 5p of the under barrier metal film 5 and the side portion 6p of the bump 6 are located on the outer surface S3B of the pad portion 3B in the first protective film 3. Therefore, a gap (see FIG. 5: s) where flux residue enters around the side portion 6p of the bump 6 is not formed. Therefore, when the flux residue is removed, the side portion 6p of the bump 6 is removed. It is possible to effectively remove the residue of the flux remaining around. For this reason, it is possible to prevent the residue of the flux from remaining around the side portion 6p of the bump 6. Therefore, a highly reliable semiconductor chip can be realized.
　加えて、封止樹脂の充填の際に、フラックスの残渣が効果的に除去されたバンプ６の側部６ｐの周囲に、封止樹脂７を良好に充填することができる。このため、バンプ６の側部６ｐの周囲に残留するフラックスの残渣により、バンプ６の側部６ｐの周囲に、封止樹脂７を良好に充填することができずに充填不良を招くことを防止することができる。従って、信頼性が高い半導体装置を実現することができる。 In addition, when the sealing resin is filled, the sealing resin 7 can be satisfactorily filled around the side portion 6p of the bump 6 from which the flux residue has been effectively removed. Therefore, it is possible to prevent the sealing resin 7 from being satisfactorily filled with the sealing resin 7 around the side portion 6p of the bump 6 due to the residual flux remaining around the side portion 6p of the bump 6. can do. Therefore, a highly reliable semiconductor device can be realized.
　さらに、第１の保護膜３を設けることにより、電極パッド２、アンダーバリアメタル膜５及びバンプ６等が、半導体チップから剥離することを防止することができる。加えて、第２の保護膜４を設けることにより、電極パッド２、アンダーバリアメタル膜５及びバンプ６等が、半導体チップから剥離することをさらに防止することができる。 Furthermore, by providing the first protective film 3, it is possible to prevent the electrode pad 2, the under barrier metal film 5, the bump 6, and the like from peeling from the semiconductor chip. In addition, by providing the second protective film 4, it is possible to further prevent the electrode pad 2, the under barrier metal film 5, the bump 6, and the like from peeling from the semiconductor chip.
　なお、本実施形態では、図４(c) に示すように、例えば無電解ニッケルめっき液への浸漬により、例えば厚さが５×１０-3ｍｍ程度のＮｉ膜を形成し、Ｎｉを含むアンダーバリアメタル膜５を形成する場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。 In this embodiment, as shown in FIG. 4 (c), for example, a Ni film having a thickness of about 5 × 10 −3 mm is formed by immersion in an electroless nickel plating solution, for example, and an underlayer containing Ni is formed. Although the case where the barrier metal film 5 is formed has been described as a specific example, the present invention is not limited to this.
　第１に例えば、本実施形態と同様に、無電解ニッケルめっき液への浸漬により、厚さが５×１０-3ｍｍ程度のＮｉ膜を形成する。その後、無電解金めっき液への浸漬により、Ｎｉ膜の上に、厚さが５×１０-5ｍｍ程度の金（Ａｕ）膜を形成し、Ｎｉ及びＡｕを含むアンダーバリアメタル膜を形成してもよい。即ち、無電解ニッケルメッキを施した後、無電解金メッキを施す、所謂、フラッシュ金めっきを施してもよい。 First, for example, similarly to this embodiment, a Ni film having a thickness of about 5 × 10 −3 mm is formed by immersion in an electroless nickel plating solution. Thereafter, a gold (Au) film having a thickness of about 5 × 10 −5 mm is formed on the Ni film by immersion in an electroless gold plating solution, and an under barrier metal film containing Ni and Au is formed. May be. That is, after applying electroless nickel plating, so-called flash gold plating may be applied.
　第２に例えば、第１の保護膜における基板部の上に、電極パッドと対応する開口部を有するレジストパターンを形成する。その後、レジストパターンをマスクとして、スパッタ又は蒸着等により、レジストパターンの開口部内に露出する電極パッド及び第１の保護膜におけるパッド部の上に、Ｎｉ膜等を形成し、Ｎｉ等を含むアンダーバリアメタル膜を形成してもよい。 Second, for example, a resist pattern having openings corresponding to the electrode pads is formed on the substrate portion of the first protective film. Thereafter, using the resist pattern as a mask, a Ni film or the like is formed on the electrode pad exposed in the opening of the resist pattern and the pad portion of the first protective film by sputtering or vapor deposition, and an under barrier containing Ni or the like A metal film may be formed.
　なお、本実施形態では、図４(d) に示すように、例えばボールマウント法により、アンダーバリアメタル膜５の上に、バンプ６を形成する場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。例えば、めっき法又はディスペンス法等により、アンダーバリアメタル膜の上に、バンプを形成してもよい。 In the present embodiment, as shown in FIG. 4D, a case where the bump 6 is formed on the under barrier metal film 5 by, for example, a ball mount method has been described as a specific example. Is not limited to this. For example, the bumps may be formed on the under barrier metal film by a plating method or a dispensing method.
　また、本実施形態では、第２の保護膜４の材料として、ポリイミドを用いた場合を具体例に挙げて説明したが、ポリイミドに代えて、例えばベンゾオキサゾール又はシリコーン系の樹脂等を用いてもよい。 In the present embodiment, the case where polyimide is used as the material of the second protective film 4 has been described as a specific example. However, instead of polyimide, for example, benzoxazole or a silicone-based resin may be used. Good.
　また、本実施形態では、第１の保護膜３の上に、第２の保護膜４を形成する場合を具体例に挙げて説明したが、本発明はこれに限定されるものではない。 In the present embodiment, the case where the second protective film 4 is formed on the first protective film 3 has been described as a specific example, but the present invention is not limited to this.
　本発明は、バンプの側部の周囲に、フラックスの残渣が残留することを防止することができ、半導体チップ及び該半導体チップを備えた半導体装置に有用である。 The present invention can prevent the residue of flux from remaining around the sides of the bumps, and is useful for a semiconductor chip and a semiconductor device including the semiconductor chip.
１　基板
２　電極パッド
３　第１の保護膜
３Ａ　基板部
３Ｂ　パッド部
３ｏ　第１の開口部
４　第２の保護膜
４ｏ　第２の開口部
５　アンダーバリアメタル膜
６　バンプ
７　封止樹脂
８　実装基板
Ｓ3B　外側面
５ｐ　アンダーバリアメタル膜の側部
６ｐ　バンプの側部
Ｓ　空間
Ｗ2，Ｗ4o，Ｗ6　幅
Ｔ5　厚さ
ｓ　間隙 DESCRIPTION OF SYMBOLS 1 Substrate 2 Electrode pad 3 1st protective film 3A Substrate part 3B Pad part 3o 1st opening part 4 2nd protective film 4o 2nd opening part 5 Under barrier metal film 6 Bump 7 Sealing resin 8 Mounting board S3B Outer side surface 5p Under barrier metal film side 6p Bump side S Space W2, W4o, W6 Width T5 Thickness s Gap

Claims (7)

  1. 　基板と、
    　前記基板の上に形成された電極パッドと、
    　前記基板及び電極パッドの周縁部の上に形成され、前記電極パッドの中央部を露出する第１の開口部を有する第１の保護膜と、
    　前記電極パッドの中央部、及び第１の保護膜における前記第１の開口部の周縁に位置する部分の上に形成されたアンダーバリアメタル膜と、
    　前記アンダーバリアメタル膜の上に形成されたバンプとを備え、
    　前記第１の保護膜は、
    　　前記基板の上面に形成された基板部と、
    　　前記電極パッドの側面及び前記電極パッドの上面における周縁部に形成されたパッド部とを有し、
    　前記アンダーバリアメタル膜における前記第１の保護膜と接触する側部、及び前記バンプにおける前記アンダーバリアメタル膜と接触する側部が、前記第１の保護膜における前記パッド部の外側面上に位置していることを特徴とする半導体チップ。     A substrate,
    An electrode pad formed on the substrate;
    A first protective film formed on a peripheral portion of the substrate and the electrode pad and having a first opening that exposes a central portion of the electrode pad;
    An under barrier metal film formed on a central portion of the electrode pad and a portion of the first protective film located on the periphery of the first opening;
    A bump formed on the under barrier metal film,
    The first protective film includes:
    A substrate portion formed on the upper surface of the substrate;
    A pad portion formed on a side surface of the electrode pad and a peripheral edge portion on the upper surface of the electrode pad;
    A side portion in contact with the first protective film in the under barrier metal film and a side portion in contact with the under barrier metal film in the bump are located on the outer surface of the pad portion in the first protective film. A semiconductor chip characterized by that.
  2. 　前記アンダーバリアメタル膜の側面は、上方から下方に広がるテーパー面であり、
    　前記バンプは、前記アンダーバリアメタル膜の側面及び上面を覆うように形成されていることを特徴とする請求項１に記載の半導体チップ。     The side surface of the under-barrier metal film is a tapered surface that extends downward from above,
    The semiconductor chip according to claim 1, wherein the bump is formed so as to cover a side surface and an upper surface of the under barrier metal film.
  3. 　前記第１保護膜の上に形成され、第２の開口部を有する第２の保護膜をさらに備えていることを特徴とする請求項２に記載の半導体チップ。 3. The semiconductor chip according to claim 2, further comprising a second protective film formed on the first protective film and having a second opening.
  4. 　前記第２の保護膜は、ポリイミドからなることを特徴とする請求項３に記載の半導体チップ。 4. The semiconductor chip according to claim 3, wherein the second protective film is made of polyimide.
  5. 　前記第１の保護膜は、窒化ケイ素からなることを特徴とする請求項４に記載の半導体チップ。 The semiconductor chip according to claim 4, wherein the first protective film is made of silicon nitride.
  6. 　前記電極パッドは、格子状に配列されていることを特徴とする請求項５に記載の半導体チップ。 The semiconductor chip according to claim 5, wherein the electrode pads are arranged in a lattice pattern.
  7. 　請求項６に記載の半導体チップと、
    　前記半導体チップが実装された実装基板とを備え、
    　前記実装基板と前記半導体チップとの間には、封止樹脂が充填されていることを特徴とする半導体装置。     A semiconductor chip according to claim 6;
    A mounting substrate on which the semiconductor chip is mounted;
    A semiconductor device, wherein a sealing resin is filled between the mounting substrate and the semiconductor chip.
PCT/JP2010/005392 2009-12-17 2010-09-01 Semiconductor chip and semiconductor device provided with said semiconductor chip WO2011074158A1 (en)

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JP2013229491A (en) * 2012-04-26 2013-11-07 Kyocera Corp Electrode structure, semiconductor element, semiconductor device, thermal head, and thermal printer
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