CN1319129C - Soldering tin lug forming method - Google Patents
Soldering tin lug forming method Download PDFInfo
- Publication number
- CN1319129C CN1319129C CNB2003101157685A CN200310115768A CN1319129C CN 1319129 C CN1319129 C CN 1319129C CN B2003101157685 A CNB2003101157685 A CN B2003101157685A CN 200310115768 A CN200310115768 A CN 200310115768A CN 1319129 C CN1319129 C CN 1319129C
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- Prior art keywords
- solder bump
- current value
- metal level
- current
- formation method
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
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- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Electric Connection Of Electric Components To Printed Circuits (AREA)
Abstract
The present invention discloses a forming method for soldering tin lugs, which comprises the following steps of providing a base whose surface is provided with a metallic layer; forming a graphic covering curtain layer on the metallic layer for exposing parts of the metallic layer; forming a soldering tin lug with the silver content of 1.6 wt% to 3.0 wt% on the exposed metallic layer by an electroplating method.
Description
Technical field
The invention relates to a kind of manufacture of semiconductor, particularly relevant a kind of method that on the semiconductor-based end, forms solder bump.
Background technology
On semiconductor chip, form the processing procedure of solder bump, be widely used in winding and engage (tape automated bonding automatically; TAB) with cover crystalline substance (flip chip; FC) encapsulation technology such as joint.
In No. 502424 patent of Taiwan patent announcement (' 424 patent to call in the following text), be to have disclosed a Pb-free solder projection, it contains the silver that percentage by weight (is preferably 3.5) below 5.Yet, silver content is during greater than 3 percentage by weights (wt%), solder bump is in more harsh environment such as follow-up hot processing procedure, high temperature, high temperature difference or high humility etc., solder bump generates silver whiskers (silver whisker) easily, thereby be easy to generate projection distortion (deformed bump), projection bridge joint (bridge bump), bump size inequality defectives such as (large or low volume bump), and cause the short circuit of assembly circuit or open circuit and reduce process rate and production reliability.In addition, when silver content is following less than 1.6%, in the density current processing procedure of projection balling-up, the outward appearance of meeting discovery projection balling-up can present the ball surface (as shown in Figure 9) of the fold as the orange peel, even sphere subside can't globulate (as shown in figure 10, wherein the scope table of solid line is spherical normally, the sphere of the projection that the scope table of dotted line has subsided), and the projection uniformity of the projection globulate in the full wafer chip not good (shown in the zone 201 of Figure 11), thereby reduced the hot processing procedure of process rate and follow-up reliability test, high temperature, high temperature difference, or the yield of testing in the more harsh environment such as high humility, and can present in the outward appearance of projection balling-up under the situation on ball surface of the fold as the orange peel, also be unfavorable for doing the position of projection with optical instrument, detections such as size.
Summary of the invention
In view of this, main purpose of the present invention provides a kind of formation method of solder bump, form high temperature resistant, high temperature difference, with the solder bump of more harsh environment such as high humility, to promote process rate and production reliability.
Another object of the present invention provides a kind of formation method of solder bump, with the level and smooth relatively solder bump of formation outward appearance, and the uniformity of the projection in the lifting full wafer chip, with the detectability of lifting projection, and promote process rate and production reliability more.
For reaching above-mentioned purpose of the present invention, the present invention provides a kind of formation method of solder bump, comprises: a substrate is provided, has a metal level on a surface; Form a patterned cover curtain layer on above-mentioned metal level, the above-mentioned metal level of expose portion; And form the scolding tin that a silver content is 1.6-3.0 percentage by weight (wt%) (solder) projection on the above-mentioned metal level that exposes with galvanoplastic.
Description of drawings
Fig. 1 is a profile, is the step 1 that shows preferred embodiment of the present invention.
Fig. 2 is a profile, is the step 2 that shows preferred embodiment of the present invention, forms the cover curtain layer 120 of patterning.
Fig. 3 is a profile, is the plating step that shows the step 3 of preferred embodiment of the present invention.
Fig. 4 is a profile, is the plating step that shows the step 4 of preferred embodiment of the present invention.
Fig. 5 is a profile, is the plating step that shows the step 5 of preferred embodiment of the present invention.
Fig. 6 is a profile, is the step 6 that shows preferred embodiment of the present invention, removes the cover curtain layer 120 of patterning.
Fig. 7 is a profile, is the step 7 that shows preferred embodiment of the present invention, and metal level 110 is patterned as projection lower metal layer 112.
Fig. 8 is a profile, is the step 8 that shows preferred embodiment of the present invention, solder bump 140 is imposed the step of a density current.
Fig. 9 is an optical microscope photograph, is to show that known solder bump outward appearance presents the surface on the ball surface of the fold as the orange peel.
Figure 10 is an optical microscope photograph, be show that known solder bump outward appearance presents that sphere subsides can't globulate.
Figure 11 is an optical microscope photograph, is with the outward appearance of the formed solder bump of formation method of solder bump of the present invention and known solder bump outward appearance in order to comparison.
Symbol description:
The electrical contact assembly 100-of 60-substrate
110-metal level 112-projection lower metal layer
The cover curtain layer 122 of 120-patterning, 124-opening
140,140-solder bump 201-zone
The 202-zone
Embodiment
Please refer to Fig. 1-Fig. 8, be a series of profile, is the flow process of formation method that shows the solder bump of preferred embodiment of the present invention.
Step 1:
Please refer to Fig. 1, at first, provide a substrate 100, be generally the substrate of monocrystalline silicon, and substrate 100 finishes the processing procedure of metal interconnect, had the structure (not illustrating) of one first weld pad and sheath (passivation); As be the substrate of chip size packages, then substrate 100 more comprise a conductor layer, one second weld pad, with structure (not illustrating) such as encapsulated layer.One metal level 110 is covered on the active surface of substrate 100 comprehensively, and forms electrically connect, metal level 110 with above-mentioned first or second weld pad.The metal level that metal level 110 is generally single or multilayer for example is Al (Ti)/NiV/Cu, Ti (or TiW)/Cu/Ni, Ti/Cr/Cr-Cu/Cu, TiW/Au or other structure (material on the solder bump of follow-up formation is decided) in regular turn, normally as ball substrate layer, can increase the bond strength of the solder bump and the above-mentioned weld pad of follow-up formation, and prevent the mutual diffusion between above-mentioned solder bump and the weld pad.The electrical performance of the above-mentioned follow-up electronic product of mutual diffusion reaction meeting deterioration.
Step 2:
Next, please refer to Fig. 2, on metal level 110, form the cover curtain layer 120 of a patterning, have projection fate on an opening 122 exposing metal layers 110, with opening 124 exposing metal layers 110 on edge part.The generation type of the cover curtain layer 120 of patterning is generally and forms photoresist layer covering metal level 110 earlier, again through steps such as overexposure, developments, forms the cover curtain layer 120 of patterning at last.
Following step 3-5 discloses a preferable plating step, to form solder bump 140 of the present invention, can make formed solder bump 140, can obtain to form solder bump uniformly.
Step 3:
Please refer to Fig. 3, substrate 100 is immersed in the electroplate liquid (not illustrating) fully, use an electrical contact assembly 60 to electrically connect then, metal level 110 is electrically connected at the negative electrode of electroplating reaction with the metal level 110 that is exposed to opening 124.At this moment, begin to carry out first section plating, make electric current by metal level 110, on the metal level 110 that is exposed to opening 122 with one first current value, form solder bump 140, up to the rough thickness that equals the cover curtain layer 120 of patterning of the thickness of solder bump 140.The composition of solder bump 140 wherein of the present invention be tin, silver, with other composition, wherein Yin content is 1.0wt%-3.0wt%, is preferably 1.6wt%-3.0wt%.At this moment, to be preferably the current density that makes by solder bump 140 be 2-7ASD (every square centimeter amperage) for above-mentioned first current value; First current value for example is about 1 ampere.
Step 4:
Please refer to Fig. 4, carry out second section plating, make electric current, up to 1.2 times of the thickness of the rough cover curtain layer 120 that equals patterning of the thickness of solder bump 140 by metal level 110 with one second current value.At this moment, better make current density maintain 2-7ASD by solder bump 140; Be not subjected to the restriction of opening 122 and can enlarge because exceed the width sectional area of paper direction (or perpendicular to) of solder bump 140 of the thickness part of cover curtain layer 120 again, therefore be preferably second current value that makes by solder bump 140 greater than above-mentioned first current value, more preferably make second current value by solder bump 140 be first current value 2.0-3.0 doubly.
Step 5:
Please refer to Fig. 5, carry out the 3rd section plating, make electric current, reach desired one set thickness up to the thickness of solder bump 140 by metal level 110 with one the 3rd current value.At this moment, better make current density maintain 2-7ASD by solder bump 140; Still might continue to enlarge because exceed the width sectional area of paper direction (or perpendicular to) of solder bump 140 of the thickness part of cover curtain layer 120 again, therefore be preferably the 3rd current value that makes by solder bump 140 and be not less than above-mentioned second current value, more preferably make the 3rd current value by solder bump 140 be first current value 3.0-4.0 doubly.
Step 6:
Please refer to Fig. 6, finish above-mentioned plating step after, remove electrical contact assembly 60, and substrate 100 removed in above-mentioned electroplate liquid.Can add a step of cleaning, remove the electroplate liquid that residues in the substrate 100.Then, remove the cover curtain layer 120 of patterning.
Step 7:
Please refer to Fig. 7, serves as the cover curtain with solder bump 140, with for example reactive ion etching method or wet etch method etch metal layers 110, so that metal level 110 is patterned as projection lower metal layer 112.
Step 8:
Please refer to Fig. 8, can optionally impose the step of a density current (reflow) to solder bump 140, be preferably under inert gas atmosphere such as for example nitrogen, with substrate 100 be heated above solder bump 140 fusing points with its liquefaction after, surface tension between the scolding tin of metal level 110 and liquid state can make the scolding tin of above-mentioned liquid state assemble becomes almost spherical, and with after substrate 100 cooling, the scolding tin of above-mentioned liquid state can solidify and become and be roughly spherical solder bump 140.
Compare with known techniques, solder bump 140 of the present invention or 140, its silver content is for being 1.0wt%-3.0wt%, be preferably 1.6wt%-3.0wt%, can avoid solder bump 140 or 140 at follow-up hot processing procedure effectively, high temperature, high temperature difference, or in the more harsh environment such as high humility, generate silver whiskers (silver whisker), thereby avoid solder bump 140 or 140 that projection distortion (deformed bump) takes place, projection bridge joint (bridge bump), bump size inequality defectives such as (large or low volume bump), thereby promote process rate and production reliability, be the main purpose of reaching the invention described above.
In addition, please refer to Figure 11, the solder bump in zone 201 is with the former of prior art method institute, and the solder bump in zone 202 is the formers of formation method institute with solder bump of the present invention.The solder bump in comparison domain 201 and zone 202, the outward appearance of the solder bump in zone 202 is level and smooth far beyond the solder bump in zone 201, and does not have the problem that sphere subsides and take place, and helps doing with optical instrument the detections such as position, size of projection; And the uniformity of the solder bump in zone 202, also the solder bump far beyond zone 201 is good, can promote process rate and production reliability more; It more than is another purpose of the invention described above.
Claims (6)
1. the formation method of a solder bump comprises:
One substrate is provided, has a metal level on the surface of this substrate;
Form a patterned cover curtain layer on this metal level, this metal level of expose portion;
At this metal level by having the electric current of one first current value, carry out first section plating, forming height is the solder bump of 1.6-3.0 percentage by weight (wt%) with this patterned cover curtain layer with a high silver content substantially, and makes the electric current by this solder bump have a set current density;
At this metal level by having the electric current of one second current value, carry out second section plating, up to this silver content is 1.2 times that the height of the solder bump of 1.6-3.0 percentage by weight is roughly this patterned cover curtain layer height, wherein this second current value is greater than this first current value, and makes the electric current by this solder bump have this set current density;
At this metal level by having the electric current of one the 3rd current value, carry out the 3rd section plating, wherein the 3rd current value is not less than this second current value, be that the height of the solder bump of 1.6-3.0 percentage by weight arrives a both take the altitude up to this silver content, and make electric current have this set current density by this solder bump;
Remove this patterned cover curtain layer; And
With this solder bump is the cover curtain, and graphically this metal level is a projection lower metal layer.
2. the formation method of solder bump according to claim 1, wherein this set current density is 2-7ASD.
3. the formation method of solder bump according to claim 1, wherein this second current value is this first current value 2.0-3.0 is doubly big.
4. the formation method of solder bump according to claim 1, wherein the 3rd current value is that the 3.0-4.0 of this first current value is doubly big.
5. the formation method of solder bump according to claim 1 more comprises: to this silver content is the step that the solder bump of 1.6-3.0 percentage by weight is carried out a density current, becomes to be roughly spherical solder bump.
6. the formation method of solder bump according to claim 1, wherein this silver content is that the solder bump of 1.6-3.0 percentage by weight is not leaded.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101157685A CN1319129C (en) | 2003-11-28 | 2003-11-28 | Soldering tin lug forming method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2003101157685A CN1319129C (en) | 2003-11-28 | 2003-11-28 | Soldering tin lug forming method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1622287A CN1622287A (en) | 2005-06-01 |
| CN1319129C true CN1319129C (en) | 2007-05-30 |
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2003101157685A Expired - Fee Related CN1319129C (en) | 2003-11-28 | 2003-11-28 | Soldering tin lug forming method |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1319129C (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5750017A (en) * | 1996-08-21 | 1998-05-12 | Lucent Technologies Inc. | Tin electroplating process |
| US5902472A (en) * | 1996-01-30 | 1999-05-11 | Naganoken And Shinko Electric Industries Co., Ltd. | Aqueous solution for forming metal complexes, tin-silver alloy plating bath, and process for producing plated object using the plating bath |
| US6013572A (en) * | 1997-05-27 | 2000-01-11 | Samsung Electronics Co., Ltd. | Methods of fabricating and testing silver-tin alloy solder bumps |
| US6179935B1 (en) * | 1997-04-16 | 2001-01-30 | Fuji Electric Co., Ltd. | Solder alloys |
| CN1320960A (en) * | 2000-04-19 | 2001-11-07 | 卓联科技有限公司 | Interconnection method without lead bosses |
-
2003
- 2003-11-28 CN CNB2003101157685A patent/CN1319129C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5902472A (en) * | 1996-01-30 | 1999-05-11 | Naganoken And Shinko Electric Industries Co., Ltd. | Aqueous solution for forming metal complexes, tin-silver alloy plating bath, and process for producing plated object using the plating bath |
| US5750017A (en) * | 1996-08-21 | 1998-05-12 | Lucent Technologies Inc. | Tin electroplating process |
| US6179935B1 (en) * | 1997-04-16 | 2001-01-30 | Fuji Electric Co., Ltd. | Solder alloys |
| US6013572A (en) * | 1997-05-27 | 2000-01-11 | Samsung Electronics Co., Ltd. | Methods of fabricating and testing silver-tin alloy solder bumps |
| CN1320960A (en) * | 2000-04-19 | 2001-11-07 | 卓联科技有限公司 | Interconnection method without lead bosses |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1622287A (en) | 2005-06-01 |
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| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C56 | Change in the name or address of the patentee |
Owner name: ECKEL ADVANCED TECHNOLOGY CO., LTD. Free format text: FORMER NAME: UNITIVE SEMICONDUCTOR TAIWAN CORP. |
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| CP03 | Change of name, title or address |
Address after: Hsinchu County of Taiwan Province Patentee after: Ecker advanced Polytron Technologies Inc. Address before: Hsinchu County, Taiwan, China Patentee before: UNITIVE SEMICONDUCTOR TAIWAN CORPORATION |
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| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20070530 Termination date: 20211128 |