JPH10224672A - Picture processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To correspond to the exchange of a CCD camera head different in the number of picture elements by providing plural burst separation means separating burst clocks in accordance with plural frequencies, namely, plural pairs of band-pass filters making the prescribed frequency pass through and gate means extracting only the signal for a period where the burst clocks are overlapped. SOLUTION: A clock generation part 100 attenuates the most part of a synchronizing signal and a video signal in a video signal (signal (a)) inputted to the band-pass filters BPF 1:60 and BPF 2:61 and only the frequency component of a pass band is outputted. The outputs (signals (b) and (c)) of BPF 1:60 and BPF 2 are inputted to the burst gates BG 1:62 and BG 2:63. The signals (b) and (c) are inputted to a burst detection part 64 and whether a burst pulse exists or not is discriminated. The result is outputted to an MPU 48 and the MPU 48 outputs a switch signal (f) for switching the BPF and the VCO based on the result.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a so-called head-separated camera in which an image pickup unit and a signal processing unit are separated via a cable or wireless communication.

[0002]

2. Description of the Related Art In recent years, a camera signal processing system using a CCD has been reduced in size and weight with the progress of electronic technology. In particular, high-speed AD due to advances in semiconductor technology
A method of performing signal processing as a digital signal using conversion and DA change is increasing.

In recent years, an image pickup apparatus using a solid-state image pickup device (hereinafter referred to as a CCD) has recently separated a CCD image pickup section (camera head section) and an image processing section for processing a signal from the CCD and outputting it as a video signal. In addition, there have been proposed many image pickup devices called so-called head-separated cameras, which extend the space between them by a cable or the like. The configuration of the head-separated camera will be described below.

FIG. 4 shows a camera head unit 1 of a conventional example.

In FIG. 4, a camera head 1 includes a zoom lens 10, an iris 11, an optical low-pass filter and an infrared cut filter 12, a CCD 13, a CDS circuit 14, an AGC circuit 15, a CCD signal, a composite synchronizing signal, a burst clock, and the like. , For example, 7
Drive circuit 17 for driving 5 ohm coaxial line 2, synchronization signal generator (SSG) 19, MPU micro-processing unit 2 for controlling camera head 1 as a whole
0, a burst gate (BG) circuit 18 for applying a gate for adding a continuous burst clock to the video signal.

The cable 2 is for connecting the camera head unit 1 to the image processing unit 3 shown in FIG.

Reference numeral 30 denotes an output terminal of a video signal to which a clock and a composite synchronizing signal are added, 31 denotes an output terminal of a transmission signal for communication with the image processing unit 3, and 32 denotes an input terminal of a reception signal for communication with the image processing unit 3. Terminal.

Next, the operation will be described with reference to FIGS.
Zoom lens 10, iris 11, optical low-pass filter and infrared cut filter 12, CCD 13, CD
An imaging signal (video signal) from the CCD is captured via the S circuit 14 and the AGC circuit 15. Synchronous signal generator 1
In step 9, various synchronization pulses for CCD imaging, a composite synchronization signal, a burst gate pulse (BGP), and a continuous clock serving as a reference for imaging are output. Burst gate (B
G) The circuit 18 gates the input continuous clock into a burst clock suitable for addition to the video signal by the BGP from the synchronization signal generator 19. The addition circuit 16 adds the video signal output from the AGC control circuit 15, the burst clock from the BG circuit 18, and the composite synchronization signal from the synchronization signal generator 19. The added video signal is driven by the 75Ω drive circuit 17 and output from the output terminal 30 to the image processing unit 3. FIG. 5 shows a part of the video signal obtained by adding the burst clock and the composite synchronization signal. A is a composite synchronization signal, B is a burst clock, and C is a video signal area. The MPU 20
The output terminal 31 and the input terminal 32 allow the M
It communicates with the PU 20 and performs control such as driving of a zoom lens and an autofocus lens, control of an iris, and AGC control.

FIG. 6 shows an image processing section 3 of a conventional example.
Note that the image processing unit 3 has the shape of an expansion board of a computer, and is inserted into an expansion board slot of the computer.

A buffer circuit 39 for the video signal 30, a clamp circuit 40, an AD converter 41, a filter, color separation,
A digital signal processing (DSP) circuit 42 that performs digital signal processing such as gamma, matrix, and clipping, and a DA converter 4 that performs digital-to-analog conversion on the digital signal-processed signal and outputs a video signal (for example, NTSC).
3, an MPU 48 for controlling the entire image processing unit 3,
Sync separation circuit 44, sync signal generator 45, band pass filter (BPF) 46, burst gate (BG)
Circuit 47 and a PLL (Phase Locked Lo).
op) circuit 49.

The cable 2 is for connecting the camera head unit 1 and the image processing unit 3. Of course, it may be wireless instead of wired.

Reference numeral 30 denotes an input terminal of a video signal to which a clock and a composite synchronizing signal are added, 31 denotes an input terminal of a reception signal for communication with the camera head 1, and 32 denotes an output of a transmission signal for communication with the camera head 1. Terminal.

The operation of FIG. 6 will be described. Buffer circuit 3
9. The video signal passed through the clamp circuit 40 is input to the AD converter 41, the sync separation circuit 44, and the BG circuit 47. The sync separation circuit 44 converts the input video signal into HD
(Horizontal synchronization), VD (vertical synchronization) signal, and burst gate pulse (BGP) are generated. The HD and VD signals are respectively supplied to a reset terminal of a horizontal synchronization counter (not shown) and a vertical synchronization counter (not shown) in the synchronization signal generator 45.
, The horizontal synchronization and the vertical synchronization with the camera head unit 1 are obtained. HD and VD signals synchronized with the camera head unit 1 are input to the DSP circuit 42.
Most of the video signal input to the BPF 46 is attenuated by the synchronization signal and the video signal, and passes only the frequency near the burst clock. From the signal input to the BG circuit 47 after passing through the BPF, the noise component remaining in the video signal area is removed by the BGP generated by the synchronization separation circuit 44, and only the burst clock is extracted.
9 is input. In the PLL circuit 49, a phase comparison circuit (P
C) 50, LPF 51, voltage controlled oscillator (VCO) 52
, A continuous clock having the same phase is generated from the burst clock, and the synchronous signal generator 45 and the AD converter 4
1. Input to the DSP circuit 42. The video signal input to the AD converter 41 is converted into a digital signal, and is image-processed by the DSP circuit 42 in synchronization with the clock from the PLL circuit 49 and the synchronization signal from the synchronization signal generator 45.
The analog video signal (for example, NTSC
Signal) and output. The MPU 20 has a bus B
It is electrically connected to the computer PC via the US
The MPU 48 performs bidirectional communication in response to a command from the C side.
Communicates with the MPU 20 of the camera head unit 1 via the output terminal 32 and the input terminal 31, and performs processing for driving a zoom lens and an autofocus lens, controlling an iris, and controlling AGC.

The head-separated camera as described above has the advantage that the camera head is small and lightweight, and that the camera head can be replaced according to the application. For example, using the image processing unit 3 as a common,
The camera head 1 can be replaced according to the intended use, such as a single focus camera or a Zoom camera.

[0015]

However, in the above configuration, there is no problem in exchanging between camera heads having CCDs having the same number of pixels.
When the camera head is replaced with a camera head having the above, it is impossible for the image processing unit 3 to reproduce a continuous clock. This is because the filter frequencies for extracting the burst clock from the video signal do not correspond because the clock frequencies are different. That is, the conventional configuration has a problem that it cannot be replaced with a camera using a CCD having a different number of pixels.

According to the present invention, even if C has different numbers of pixels from each other,
It is an object of the present invention to provide an image processing apparatus that can be replaced even by a plurality of cameras using a CD.

[0017]

According to the present invention, there is provided an image processing apparatus comprising: an input terminal for inputting a multiplexed video signal to which a burst clock and a composite synchronizing signal are added; Synchronizing separating means for separating a signal, a plurality of burst separating means for separating the burst clock from the multiplexed video signal based on the separated synchronizing signal, clock frequency detecting means for detecting a burst clock frequency, and clock frequency detecting Selecting means for selecting an optimal burst separating means from the plurality of burst separating means according to a result of the means.

The burst separating means has a plurality of pairs of band-pass filters for passing a predetermined frequency and gate means for extracting only signals in a period in which a burst clock is superimposed.

The clock generation means includes a phase comparator for comparing the phases of two clocks, a low-pass filter for averaging the output of the phase comparator, and an oscillation frequency controlled by the output of the low-pass filter. A plurality of voltage controlled oscillators, and switching means for selecting one of the plurality of voltage controlled oscillators and inputting the selected one to the phase comparator.

The pass frequency of the band-pass filter and the center oscillation frequency of the voltage-controlled oscillator are associated with each other so as to coincide with each other, and based on the result of the clock frequency detection means, the first switching means and the By switching both of the two switching means, the band-pass filter and the voltage-controlled oscillator corresponding to the clock frequency are selected.

By using the above means, even when burst clocks of a plurality of frequencies are multiplexed,
Since the corresponding band-pass filter and voltage-controlled oscillator are selected, a continuous clock can be generated by separating the burst clock.

[0022]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. The image processing unit 3 of the present invention also performs bidirectional communication with the PC while being inserted into an expansion slot of the PC as an expansion board or an expansion card.

A buffer circuit 39 for the video signal 30, a clamp circuit 40, an AD converter 41, a filter, color separation,
A digital signal processing (DSP) circuit 42 for performing digital signal processing such as gamma, matrix, clipping, etc., and a DA converter 4 for digital-to-analog conversion of the digital signal processed signal and outputting a video signal (for example, NTSC)
3, an MPU 48 for controlling the entire image processing unit 3,
It comprises a synchronization separation circuit 44, a synchronization signal generator 45, and a clock generation unit 100 that generates a continuous clock having the same phase from the burst clock.

The clock generator 100 includes a switch 65,
Two band pass filters (BPF 1:60, BPF
2:61) and two burst gate circuits (BG1: 6)
2, BG2: 63) and a burst detector (Detec)
t) 64 and PLL (PhaseLocked Loop)
p) The circuit 70 and the PLL circuit 70 further include a phase comparator (P
C: Phase comparator (71), low-pass filter 72, and two VCOs (Voltage)
Control Oscillator) (VCO1: 7)
3, VCO2: 74) and a switch 75.

The cable 2 is for connecting the camera head unit 1 and the image processing unit 3.

Reference numeral 30 denotes an input terminal of a video signal to which a clock and a composite synchronizing signal are added, 31 denotes an input terminal of a reception signal for communication with the camera head 1, and 32 denotes an output of a transmission signal for communication with the camera head 1. Terminal. BUS is a bus for performing bidirectional communication with a PC.

In this embodiment, the clock frequency is 9.5M
Hz (equivalent to a 270,000 pixel CCD) and 14.3 MHz (41
B) with two types of corresponding examples.
PF1 (f = 9.5 MHz), BPF2 (f = 14.3)
MHz), VCO1 (f = 9.5 MHz center)
r), VCO2 (f = 14.3 MHz center)
Will be described.

Next, the operation will be described. Buffer circuit 39,
The video signal that has passed through the clamp circuit 40 is output to the AD converter 4
1, the sync separation circuit 44 and the clock generation unit 100. In the sync separation circuit 44, H
D and VD signals and a burst gate pulse (BGP) are generated. The HD and VD signals are input to the reset terminal of the horizontal synchronization counter and the reset terminal of the vertical synchronization counter of the synchronization signal generator 45, respectively, to perform horizontal synchronization and vertical synchronization with the camera head unit 1. Camera head 1
The HD and VD signals synchronized with are input to the DSP circuit 42. The video signal input to the clock generation unit 100 includes a bandpass filter suitable for the burst clock frequency and a P
The LL circuit generates a continuous clock having the same phase. The clock generator 100 will be described later. The continuous clock generated by the clock generation unit 100 is supplied to the synchronization signal generator 45, the AD converter 41, and the DS
It is input to the P circuit 42. The video signal input to the AD converter 41 is converted into a digital signal,
In synchronization with the clock from 00 and the synchronizing signal from the synchronizing signal generator 45, the image processing is performed by the DSP circuit 42,
The analog video signal (for example, NTSC
Signal) and output. The MPU 48 performs bidirectional communication with the PC via the bus, communicates with the MPU 20 of the camera head unit 1 through the output terminal 32 and the input terminal 31,
Processing for driving the zoom lens and the autofocus lens, controlling the iris, and controlling the AGC is performed.

FIG. 2 is a diagram for explaining the waveform of each unit such as the clock generation unit 100. Hereinafter, the operation of the clock generation unit 100 will be described with reference to FIGS. Most of the video signal (signal a) input to the two band-pass filters, BPF1: 60 and BPF2: 61, attenuates most of the synchronization signal and the video signal, and outputs only the frequency components in the passband. For example, when the burst clock frequency is 9.5 MHz as shown in FIG. 2, only the burst clock component from which the synchronization signal and the video signal are deleted is output from the BPF 1 and the BP is output.
Almost nothing is output from F2. Conversely, when the burst clock frequency is 14.3 MHz, only the burst clock component from which the synchronization signal and the video signal have been deleted is output from BPF2, and almost nothing is output from BPF1. The outputs (signal b and signal c) of BPF1 and BPF2 are input to BG1: 62 and BG2: 63, respectively, and the BGP generated by the sync separation circuit 44 removes noise components remaining in the video signal area and outputs. (Signal d,
Signal e). On the other hand, the outputs (signals b and c) of the BPF1 and BPF2 are input to the burst detection unit 64, and it is determined whether or not a burst pulse exists.
48. The MPU 48 outputs a switching signal f for switching between BPF and VCO based on the result.

Next, the PLL circuit 70 will be described. B
For the signals (signals d and e) gated by the GP, a signal in which a burst clock is present is selected by a switch 65 using a switching signal f generated by the MPU 48, and a phase comparator (PC) 71 Is input to P
In C71, the burst clock g and the continuous clock h (=
VCO output) in the area where the burst clock is present, and outputs the difference i. The output is input to a low-pass filter (LPF) 72. LPF7
2 averages the output i of the PC 71 and outputs a signal j. The signal j has two VCOs (VCO1: 73, VCO2: 7).
Input to 4). Here, VCO1: 73 is 9.5.
VCO whose center frequency is MHz, VCO2: 74 is 1
A VCO having a center frequency of 4.3 MHz. Each VC
O changes the oscillation frequency according to the level of the signal j.
As for the output of each VCO, the switch 75 selects the VCO corresponding to the burst clock frequency using the switching signal f and feeds it back to the PC 71. In this way, locking is performed when the phases of the burst clock and the continuous clock match.

FIGS. 3A and 3B are diagrams respectively showing an example of the configuration of the burst detection unit and an example of the detection method. The signals (signal d, signal e) output from BG1: 60 and BG2: 61 are respectively subjected to peak detection (signal 1, signal m) through detection circuit 1:81 and detection circuit 2:82, respectively.
The signals are input to the comparators 83 and 84. Comparator 8
3 and 84, the signal l and the signal m are binarized (signals n and n).
The signal o) is sampled by the timing signal p generated from the BGP. The result is transmitted to the MPU 48, which determines whether or not a burst clock exists, and recognizes the frequency of the burst clock.
Based on this, the MPU 48 generates a switching signal f for selecting a BPF and a VCO corresponding to the frequency of the burst clock.

In FIG. 3, the comparator and sampling functions of the burst detector may be realized not only by a logic circuit but also by an MPU AD port. Further, the switching signal f is issued not only by the MPU as in the present embodiment, but also by a method in which all processes from burst detection to switching signal output are realized by a logic circuit. In this embodiment, a detection circuit for automatically detecting the frequency of the burst signal sent from the camera head is provided. For example, a ROM for storing pixel number data or burst frequency data in the camera head is provided.
And the like, the pixel number data or the burst frequency data may be automatically transmitted when connected to the image processing apparatus, and the switches 65 and 75 may be switched based on the automatically transmitted data.

As described above, since the band-pass filter and the VCO corresponding to a plurality of frequencies can be switched in advance, camera heads using the clock frequency as the main clock can be exchanged with each other, so that no special adjustment work is performed. Automatic optimization is possible.

[0035]

By using the above means,
A plurality of camera heads using CCDs having different numbers of pixels can be exchanged. As a result, it becomes possible to exchange only the camera head according to the application while sharing the image processing unit.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating an image processing unit in an image processing apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram illustrating an example of an operation of a clock generation unit in the image processing device according to the embodiment of the present invention.

FIG. 3A is a diagram illustrating an example of a configuration of a burst detection unit according to an embodiment of the present invention. (B) is FIG.
FIG. 9 is a diagram illustrating an example of a burst clock detection method according to the configuration of FIG.

FIG. 4 is a diagram showing a camera head section of a conventional head-separated camera.

FIG. 5 is a diagram illustrating a part of a video signal obtained by adding a burst clock and a composite synchronization signal.

FIG. 6 is a diagram illustrating an image processing unit of a conventional head-separated camera.

Claims (5)

[Claims] An input terminal for inputting a multiplexed video signal to which a burst clock and a composite sync signal are added; a sync separation unit for separating a sync signal from the multiplex video signal; and the multiplexed video based on the separated sync signal. A plurality of burst separation means for separating the burst clock from a signal; a clock frequency detection means for detecting a burst clock frequency; and an optimal burst separation among the plurality of burst separation means according to a result of the clock frequency detection means. An image processing apparatus comprising: a selection unit for selecting a unit. 2. The burst separating device according to claim 1, wherein the burst separating device has a plurality of pairs of a band-pass filter that passes a predetermined frequency and a gate device that extracts only a signal in a period in which a burst clock is superimposed. The image processing apparatus according to any one of the preceding claims. 3. The clock generating means includes: a phase comparator for comparing phases of two clocks; a low-pass filter for averaging an output of the phase comparator; and an oscillation frequency based on an output of the low-pass filter. 2. The image processing apparatus according to claim 1, further comprising: a plurality of voltage-controlled oscillators for controlling the voltage-controlled oscillator; and switching means for selecting one of the plurality of voltage-controlled oscillators and inputting the selected one to the phase comparator. 4. The band-pass filter and the voltage-controlled oscillator are associated with each other such that a pass frequency of the band-pass filter matches a center oscillation frequency of the voltage-controlled oscillator. The image processing apparatus according to any one of the preceding claims. 5. The image processing apparatus according to claim 1, wherein said clock frequency detecting means detects pixel number data or clock frequency data input from a camera head.