JPH11252438A - Image-pickup device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce a cable signal line number in an image-pickup device for which a camera head part and a camera main part are connected by a cable. SOLUTION: In a camera main section 3, control signals 370 supplied from a CPU 37 are multiplexed with composite synchronizing signals 34 from a synchronizing signal generation circuit 35 in a multiplex circuit 33 and sent out, and a clock is superimposed on a power source line in a clock superimposing circuit 38 and sent out. In a camera head part 2, a clock 27 superimposed on the power source line is separated into a clock detection circuit 26, the composite synchronizing signals and the control signals are separated from the multiplex signals 24 in a solid-state image-pickup element drive signal generation circuit 23, and a lens part 1 and the camera head part 2 are controlled corresponding to the control signals. Also, multiplex signals 25 to which the state signals of the lens part 1 and the camera head part 2 are multiplexed are sent out, and video signals from a solid-state image-pickup element 20 are superimposed on the multiplex signals 25 in the multiplexing circuit 22 and sent out to the camera main part 3.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image pickup apparatus having a structure for connecting a camera head section and a camera main section with a cable or the like.

[0002]

2. Description of the Related Art Conventionally, as an image pickup apparatus having a configuration in which a camera head section and a camera main section are connected by a cable or the like, there is an image pickup apparatus described in JP-A-9-83851. This conventional imaging apparatus will be described with reference to FIG. In FIG. 12, reference numeral 90 denotes a camera head unit, 91 denotes a solid-state imaging device, 92 denotes a sample hold circuit, and 93 denotes an AG.
C (auto gain control) circuit, 94 is a solid-state image sensor drive signal generation circuit, 95 is a synchronization signal generation circuit, 96
Is a selection circuit, and 97 is a CPU. 100 is a camera main unit, 101 is a CPU, 102 is a horizontal synchronization signal detection circuit, 103 is a vertical synchronization signal detection circuit, 104 is a clock detection circuit, 105 is a digital signal processing circuit, and 106 is A
A / D conversion circuit 107 is a D / A conversion circuit. Reference numeral 98 denotes a cable for connecting the camera head unit 90 and the camera main unit 100.

In the imaging apparatus having the above-described configuration,
A synchronization signal generation circuit 95 in the camera head unit 90 generates a horizontal synchronization signal HD, a vertical synchronization signal VD, and a clock CLK. In the solid-state image sensor drive signal generation circuit 94 receiving these three signals, when a solid-state image sensor drive signal is supplied to a solid-state image sensor (CCD solid-state image sensor) 91, the solid-state image sensor 1 generates a solid-state image sensor signal, and Select circuit 9 via hold circuit 92 and AGC circuit 93
6. A horizontal synchronizing signal HD, a vertical synchronizing signal VD, and a clock CLK are also input to the selection circuit 96 in addition to the solid-state imaging device signal. Each signal is selected under the control of the CPU 97 and transmitted to the camera main unit 100 through the cable 98. I do.

In the camera main unit 100, a selection circuit 96 is provided.
Solid-state image sensor signal, horizontal synchronizing signal H
D, the vertical synchronization signal VD, and the clock CLK,
Detect by the control of 1. Specifically, the horizontal synchronization signal HD is detected by the horizontal synchronization signal detection circuit 102, the vertical synchronization signal VD is detected by the vertical synchronization detection circuit 103, the clock CLK is detected by the clock detection circuit 104, and the respective phases are synchronized. A signal is generated and the digital signal processing circuit 105
Supply to The digital signal processing circuit 105 performs digital signal processing on the solid-state imaging device signal from the selection circuit 96 and performs N signal processing.
Outputs TSC signal.

[0005]

However, in the above conventional imaging apparatus, the control signals Tx and Rx
(In this case, Tx means a transmission signal and Rx means a reception signal), and there is a problem that the number of signals is large. In addition, since the clock CLK, the horizontal synchronizing signal HD, and the vertical synchronizing signal VD are selected and transmitted on the same signal line (cable) as the solid-state imaging device signal, a high bandwidth is required for the signal line. There is a problem that high-frequency noise is mixed in the solid-state imaging device signal after the quantization in the above.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide an image pickup apparatus in which a camera head section and a camera main section are connected by a cable, wherein the number of signal lines of the cable can be reduced. Another object of the present invention is to provide an imaging device capable of preventing high-frequency noise from being mixed and obtaining a high-quality image.

[0007]

According to the imaging apparatus of the present invention, the synchronizing signal generation circuit is shifted to the camera main side, the CPU is arranged only on the camera main side, and the composite synchronizing signal and the camera are transferred from the camera main section to the camera head section. By multiplexing and sending the control signal of the head unit and multiplexing and transmitting the composite synchronization signal, the status signal of the camera head unit, and the video signal from the camera head unit to the camera head unit, the camera head unit and the camera main unit are transmitted. This is to reduce the number of cables between them.

According to a first aspect of the present invention, there is provided an image pickup apparatus comprising a solid state image pickup device, a sample hold circuit, a camera head side multiplexing circuit, a solid state image pickup device drive signal generation circuit, and a clock detection circuit, and an A / D converter. A camera main unit including a circuit, a signal processing circuit, a D / A conversion circuit, a synchronization signal generation circuit, a camera main side multiplexing circuit, a state signal detection circuit, a clock superimposing circuit, and a CPU. Section is connected with a cable.

In this case, the camera main side multiplexing circuit multiplexes the composite synchronizing signal from the synchronizing signal generation circuit and the control signal of the camera head section supplied from the CPU, and as a camera main side multiplexing signal through the cable, the camera head section. Sent to Further, a clock superimposing circuit superimposes a clock on a power supply line and sends the clock to a camera head through a cable. Further, a clock detection circuit separates a clock superimposed on the power supply line. Also, the solid-state image sensor drive signal generation circuit separates the composite synchronization signal and the control signal from the multiplexed signal on the camera main side based on the clock, controls the camera head unit according to the control signal, and combines the composite synchronization signal with the camera head. The camera head side multiplexed signal is generated by multiplexing the status signal of the unit. Further, the multiplexing circuit on the camera head side superimposes the video signal from the solid-state imaging device on the multiplexed signal on the camera head side, and sends out the multiplexed output signal to the camera main unit through a cable. Further, a state signal detection circuit detects a state signal of the camera head section from the multiplexed output signal from the camera head section and sends the signal to the CPU.

According to the first aspect of the present invention, the camera main-side multiplexing circuit inserts a control signal for the camera head from the CPU during a specific period of the composite synchronizing signal from the synchronizing signal generating circuit in the camera main-side multiplexing circuit. A signal and a signal in which a clock is superimposed on a power supply line by a clock superimposing circuit are simultaneously supplied to a camera head unit. In the camera head unit, a clock and a power supply superimposed on a power supply line are separated by a clock detection circuit, and the clock is separated. It is supplied to the solid-state image sensor drive signal generation circuit. The solid-state imaging device drive signal generation circuit includes:
Upon receiving the multiplexed signal on the camera main side, it separates the composite synchronization signal and the control signal, controls the camera head based on the control signal, and inserts a status signal indicating the status of the camera head in a specific period to insert the camera into the camera. Output as a head-side multiplexed signal. The multiplexing circuit on the camera head side mixes the video signal from the solid-state imaging device with the multiplexed signal on the camera head side and sends out the multiplexed output signal to the camera main unit. Therefore, the connection between the camera main unit and the camera head unit can be realized with at least three lines.

According to a second aspect of the present invention, there is provided an image pickup apparatus, comprising: a camera head unit including a solid-state image pickup device, a sample-and-hold circuit, a camera-head-side multiplexing circuit, a solid-state image pickup device drive signal generation circuit, and a clock detection circuit; A camera main unit including a circuit, a signal processing circuit, a D / A conversion circuit, a synchronization signal generation circuit, a camera main side multiplexing circuit, a state signal detection circuit, and a CPU, and a cable connecting the camera head unit and the camera main unit. Connected with.

In this case, the camera main side multiplexing circuit multiplexes the composite synchronizing signal from the synchronizing signal generation circuit and the control signal of the camera head section supplied from the CPU, and as a camera main side multiplexing signal, passes through the cable to the camera head section. Sent to Further, the clock detection circuit generates a clock from the multiplexed signal on the camera main side.
Also, the solid-state image sensor drive signal generation circuit separates the composite synchronization signal and the control signal from the multiplexed signal on the camera main side based on the clock, controls the camera head unit according to the control signal, and combines the composite synchronization signal with the camera head. The camera head side multiplexed signal is generated by multiplexing the status signal of the unit. Further, the multiplexing circuit on the camera head side superimposes the video signal from the solid-state imaging device on the multiplexed signal on the camera head side, and sends out the multiplexed output signal to the camera main unit through a cable. Further, a state signal detection circuit detects a state signal of the camera head section from the multiplexed output signal from the camera head section and sends the signal to the CPU.

According to the second aspect of the present invention, the camera main-side multiplexing circuit inserts a control signal for the camera head from the CPU during a specific period of the composite synchronizing signal from the synchronizing signal generating circuit in the camera main-side multiplexing circuit. The signal is supplied to the camera head unit, and the camera head unit reproduces the clock from the multiplexed signal on the camera main side by the clock detection circuit, and receives the clock and the multiplexed signal on the camera main side by the solid-state image sensor drive signal generation circuit. A signal and a control signal are separated, the camera head is controlled based on the control signal, and a state signal indicating the state of the camera head is inserted in a specific period and output as a camera head side multiplexed signal. The multiplexing circuit on the camera head side mixes the video signal from the solid-state imaging device with the multiplexed signal on the camera head side and sends out the multiplexed output signal to the camera main unit. Therefore, the connection between the camera main unit and the camera head unit can be realized with at least two lines excluding the power supply line. Further, since the clock is generated from the synchronization signal without directly transmitting the clock, the influence of high frequency noise can be reduced.

According to a third aspect of the present invention, in the image pickup apparatus according to the first or second aspect, a CPU is provided in advance.
Has a plurality of selection signals defined by the cable length, and sets the cable length in the CPU to select the sampling clock phase of the A / D conversion circuit. Supply to the circuit.

According to the third aspect of the present invention, an optimum sampling clock can be obtained even if the length of the cable is changed. According to a fourth aspect of the present invention, there is provided an image pickup apparatus comprising: a solid state image pickup device; a sample hold circuit; a camera head side multiplexing circuit; a solid state image pickup device driving signal generation circuit; and a clock detection circuit; A camera main unit including a processing circuit, a D / A conversion circuit, a synchronization signal generation circuit, a camera main-side multiplexing circuit, a state signal detection circuit for detecting a state signal of the camera head unit, and a CPU; The camera main unit is connected with a cable.

In this case, the camera main-side multiplexing circuit multiplexes the composite synchronizing signal from the synchronizing signal generation circuit, the camera head control signal supplied from the CPU, and a specific pattern signal to generate a camera main-side multiplexed signal. It is sent to the camera head through a cable. Also,
A clock detection circuit generates a clock from the multiplexed signal on the camera main side. Also, the solid-state image sensor drive signal generation circuit separates the composite synchronization signal and the control signal from the multiplexed signal on the camera main side based on the clock, controls the camera head unit according to the control signal, and combines the composite synchronization signal with the camera head. The camera head side multiplexed signal is generated by multiplexing the status signal of the unit and a specific pattern signal. Further, the camera head side multiplexing circuit superimposes the video signal from the solid-state imaging device on the camera head side multiplexed signal,
The multiplexed output signal is transmitted to the camera main unit through a cable. Further, the state signal detection circuit detects the state signal of the camera head from the multiplexed output signal from the camera head and sends it to the CPU, and detects a specific pattern signal. A delay signal indicating a detection time width from transmission to the conversion circuit to detection of a specific pattern signal by the state signal detection circuit is sent to the CPU. Further, the CPU performs a process of selecting the sampling clock phase of the A / D conversion circuit based on the delay signal indicating the detection time width, and outputs a selection signal for selecting the sampling clock phase of the A / D conversion circuit to A / D.
It is supplied to the D conversion circuit. Further, the A / D conversion circuit selects a sampling clock according to the selection signal.

According to the fourth aspect of the present invention, the camera main unit in which the control signal and the specific pattern for the camera head unit are inserted by the CPU in the specific period of the composite synchronizing signal from the synchronizing signal generating circuit in the camera main side multiplexing circuit. The multiplexed signal is supplied to the camera head unit. The camera head unit reproduces a clock from the multiplexed signal on the camera main side by a clock detection circuit, and the clock and the multiplexed signal on the camera main side are generated by a solid-state imaging device drive signal generation circuit. The control signal is separated from the received composite synchronizing signal and the control signal, the camera head is controlled based on the control signal, and a status signal indicating the status of the camera head is inserted in a specific period and output as a camera head side multiplexed signal. I do. The multiplexing circuit on the camera head side mixes the video signal from the solid-state imaging device with the multiplexed signal on the camera head side and sends out the multiplexed output signal to the camera main unit. In the camera main part,
A state signal detection circuit detects a state signal and a specific pattern from the multiplexed output signal, and supplies a delay signal indicating a detection time difference from the transmission of the specific pattern from the CPU to the multiplexing circuit on the camera main side to the detection of the specific pattern to the CPU. . CP
In U, the A / D converter selects a sampling clock having an optimal phase based on the delay signal. Therefore,
The signal lines between the cables can be connected with the camera main unit and the camera head unit in at least two lines, excluding the power supply line, and the A / D conversion circuit can be used for the cable delay and the change in the cable length. An optimal sampling clock can be obtained. Further, since the clock is generated from the synchronization signal without directly transmitting the clock, the influence of high frequency noise can be reduced.

According to a fifth aspect of the present invention, in the imaging device of the fourth aspect, the CPU performs a process of selecting a sampling clock phase according to the delay signal to the A / D conversion circuit only for a specific time and performs processing other than the specific time. During the time, the selection signal is held. According to the imaging apparatus of the fifth aspect, by setting the specific pattern detection and the transmission / extraction of the control signal to the specific time, the CPU load can be reduced and the influence of noise on the video signal in the cable can be reduced.

An image pickup apparatus according to a sixth aspect of the present invention provides a camera head section including a solid-state image pickup device, a sample-and-hold circuit, a camera head-side selective multiplexing circuit, a solid-state image pickup device drive signal generation circuit, and a clock detection circuit; A camera main unit including a conversion circuit, a signal processing circuit, a D / A conversion circuit, a synchronization signal generation circuit, a camera main side multiplexing circuit, a state signal detection circuit for detecting a state signal of a camera head unit, and a CPU; The camera head and the camera main are connected by a cable.

In this case, the camera main-side multiplexing circuit multiplexes the composite synchronizing signal from the synchronizing signal generation circuit, the camera head control signal supplied from the CPU only for a specific time, and a specific pattern signal, and The signal is sent to the camera head unit through a cable as a conversion signal. Further, the clock detection circuit generates a clock from the multiplexed signal on the camera main side. Further, the solid-state imaging device drive signal generation circuit separates the composite synchronization signal and the control signal inserted only for a specific time from the multiplexed signal on the camera main side based on the clock, controls the camera head according to the control signal, and A camera head side multiplexed signal is generated by multiplexing a state signal of the camera head unit and a specific pattern signal for a specific time with respect to the composite synchronization signal.

Further, the camera head side selective multiplexing circuit transmits only the camera head side multiplexed signal as a selective multiplexed output signal to the camera main unit through a cable during a specific time, and from the solid state image pickup device during a normal time other than the specific time. Is superimposed on the multiplexed signal on the camera head side, and is sent out as a selective multiplexed output signal to the camera main unit through a cable. Further, the state signal detection circuit detects the state signal of the camera head section from the selective multiplexed output signal from the camera head section only for a specific time and sends it to the CPU, and also detects a specific pattern signal and outputs the specific pattern signal from the CPU. A delay signal indicating a detection time width from transmission to the multiplexing circuit on the camera main side to detection of a specific pattern signal by the state signal detection circuit is transmitted to the CPU. Further, the CPU performs a process of selecting the sampling clock phase of the A / D conversion circuit based on the delay signal indicating the detection time width, and
A selection signal for selecting the sampling clock phase of the D conversion circuit is supplied to the A / D conversion circuit. Further, the A / D conversion circuit selects a sampling clock according to the selection signal.

According to the sixth aspect of the present invention, a specific pattern is sent from the CPU only for a specific time, and the control signal and the control signal are multiplexed into a composite synchronizing signal by the multiplexing circuit on the camera main side, and the multiplexed signal is output as a multiplexed signal on the camera main side. Inserted into the head part, the camera head part reproduces the clock from the multiplexed signal on the camera main side and separates the control signal, and selectively multiplexes the multiplexed signal on the camera head side from the solid-state image sensor drive signal generation circuit on the camera head side Supply to the circuit. The camera head side selective multiplexing circuit selects whether the video signal from the solid-state imaging device is superimposed on the camera head side multiplexed signal and transmitted or only the camera head side multiplexed signal is transmitted. When a specific pattern is inserted, the multiplexed signal on the camera head side is selected, the time signal from the time of transmission of the specific pattern to the time of detection of the specific pattern is detected by the state signal detection circuit, and passed to the CPU as a delay signal. A selection signal is supplied to the / D conversion circuit. Therefore, the connection between the camera main unit and the camera head unit can be realized with at least two signal lines excluding the power supply line, and the A / D is controlled with respect to the cable delay and the change in the cable length. An optimum sampling clock can be obtained by the conversion circuit. Also, without transmitting the clock directly,
Since the clock is generated from the synchronization signal, the effect of high frequency noise can be reduced.In addition, the video signal from the solid-state image sensor and the status signal and the specific pattern signal of the camera head side multiplexed signal can be completely removed. Is transmitted without being multiplexed, instead of inserting the state signal and the specific pattern signal in the vertical blanking period in one field signal as in the case of claims 2 to 4,
Since the state signal and the specific pattern signal and the video signal are switched in the field, the influence of noise on the video signal can be further reduced as compared with the case of claims 2 to 4, and a high quality video signal can be obtained. it can.

According to a seventh aspect of the present invention, there is provided the imaging apparatus according to the first, second, third, fourth, fifth, or sixth aspects.
In the imaging device according to the above, a lens control signal for controlling a lens unit that captures an image of a subject is included in the control signal,
A lens state signal indicating the state of the lens unit is included in the state signal. According to the imaging device of the seventh aspect, it is possible to control the lens unit and monitor the state of the lens unit without increasing the number of cables.

In the above description, the expression “specific period” refers to a vertical blanking period, and is intended to be distinguished from a period during which a video signal is transmitted in one field period. On the other hand, the expression “specific time” is intended to mean a time when the power is turned on, a mode is changed such as a lens aperture or zoom, or a time for each fixed period for monitoring a camera head and adjusting A / D conversion timing. As the time, for example, a vertical blanking period of one field cycle is defined. The period is not limited to one field period, and may be one field period × n (n: integer).

[0025]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment: Claim 1,
Corresponding to 7] Hereinafter, an imaging device according to a first embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a basic configuration of the imaging device according to the first embodiment of the present invention. The imaging apparatus includes a lens unit 1 for photographing a subject, a camera head unit 2 for receiving and photoelectrically converting light from the lens unit 1, and a camera main unit 3 connected to the camera head unit 2 by a cable 4. You. The camera head unit 2 includes a solid-state imaging device 20 and a sample-and-hold circuit 21.
And a camera head side multiplexing circuit 22, a solid-state image sensor driving signal generating circuit 23, and a clock detecting circuit 26. The camera main unit 3 includes an A / D conversion circuit 30, a digital signal processing circuit 31, a D / A conversion circuit 32, a synchronization signal generation circuit 35, a camera main side multiplexing circuit 33, a state signal detection circuit 36, and a clock superimposition. It comprises a circuit 38 and a CPU 37.

The camera main-side multiplexing circuit 33 transmits the composite synchronizing signal 34 from the synchronizing signal generating circuit 35 to the CPU.
Lens unit 1 and camera head unit 2 supplied from 37
Is multiplexed with the control signal 370 and transmitted to the camera head unit 2 through the cable 4 as the camera main side multiplexed signal 24. Further, the clock superimposing circuit 38 superimposes the clock 382 on the power supply line 381 and transmits the clock 382 to the camera head 2 through the cable 4.

The clock detecting circuit 26 is connected to the power line 26
The clock 27 superimposed on 1 is separated. Further, the solid-state image sensor drive signal generation circuit 23 separates the composite synchronization signal 34 and the control signal 370 from the camera main-side multiplexed signal 24 based on the clock 27, and outputs the control signal 37
0, the lens unit 1 and the camera head unit 2 are controlled, and a camera head side multiplexed signal 25 is generated by multiplexing the composite synchronization signal 34 and the state signals of the lens unit 1 and the camera head unit 2. Further, the camera head side multiplexing circuit 22 superimposes the video signal from the solid-state imaging device 20 on the camera head side multiplexed signal 25 and sends out the multiplexed output signal 220 to the camera main unit 3 through the cable 4.
The state signal detection circuit 36 detects a state signal 371 of the lens unit 1 and the camera head unit 2 from the multiplexed output signal 220 from the camera head unit 2 and sends it to the CPU 37.

Hereinafter, this imaging device will be described in detail. In FIG. 1, a composite synchronizing signal 34 from a synchronizing signal generation circuit 35, control of iris and zoom to the lens unit 1 from the CPU 37, a mode of driving the solid-state image sensor of the camera head unit 2, a gain control signal, and the like. The control signal 370 and the control signal 370 are multiplexed by the camera main-side multiplexing circuit 33 and transmitted to the camera head unit 2 via the cable 4 as the camera main-side multiplexed signal 24. As shown in FIG. 2, the control signal 370 is arranged in a specific period of the composite synchronization signal, for example, in a vertical blanking period in one field.

In the camera main unit 3, the clock 382 is superimposed on the power supply line 381 by the clock superimposing circuit 38 and transmitted to the camera head unit 2 via the cable 4. In the camera head unit 2, the clock detection circuit 26 receives a signal obtained by superimposing a clock on a power supply voltage, extracts a clock 27 by a high-pass filter 262 as shown in FIG. Extract only the ingredients. The clock 27 is supplied to the solid-state imaging device drive signal generation circuit 23, and the control signal 370 is separated from the camera main-side multiplexed signal 24 by the solid-state imaging device drive signal generation circuit 23. Further, the signal is sent to the sample hold circuit 21 as a gain control signal 234, and the timing signal 233 is generated from the camera main-side multiplexed signal 24 to drive the solid-state imaging device 20. In addition,
The power supply line 261 is used to supply power to each block of the camera head unit 2.

The solid-state image sensor 20 has a timing signal 23
3 to output a solid-state imaging device signal 201 obtained by photoelectrically converting the light from the lens unit 1. Solid-state image sensor signal 201
Enters the camera head side multiplexing circuit 22 after the reset noise is removed and the gain is controlled by the sample and hold circuit 21. The camera head side multiplexing circuit 22 is also supplied with a camera head side multiplexed signal 25. The camera head side multiplexed signal 25 is output from the solid-state image sensor drive signal generation circuit 23 to the lens state signal 231 indicating the iris state and zoom state of the lens unit 1 and the state of the camera head unit 2 (for example, whether or not the timing signal 233 can be output). , The signal indicating the solid-state imaging device drive mode) is multiplexed instead of the control signal 370 at the position (specific period) where the control signal 370 is inserted in the camera main-side multiplexed signal 24 shown in FIG. It has been made.

In the camera head-side multiplexing circuit 22 to which the above-described signals are input, the video signal from the sample-and-hold circuit 21 and the camera head-side multiplexed signal 25 are converted into the signals shown in FIG.
Are mixed to form a multiplexed output signal 220 as shown in
The multiplexed output signal 220 is output to the camera main unit 3 via the cable 4. In the camera main unit 3, A / D
After A / D conversion of the multiplexed output signal 220 by the conversion circuit 30, the digital signal processing circuit 31 performs signal processing, and further outputs the image signal by the D / A conversion circuit 32, and multiplexes by the state signal detection circuit 36. By extracting the lens state signal 231 and the signal indicating the state of the camera head unit 2 from the converted output signal 220 and supplying them to the CPU 37 as the state signal 371, the state of the lens unit 1 and the camera head unit 2 can be monitored by the CPU 37. it can.

According to the imaging apparatus of this embodiment, the lens section 1 and the camera are controlled by the CPU 37 during a specific period (vertical blanking period) of the composite synchronizing signal 34 from the synchronizing signal generating circuit 35 in the camera main side multiplexing circuit 33. The camera main-side multiplexed signal 24 into which the control signal 370 of the head unit 2 is inserted, and the power supply line 38
1 and a signal in which a clock 382 is superimposed is simultaneously supplied to the camera head unit 2. In the camera head unit 2, the clock 27 superimposed on the power line 261 is separated from the power supply by the clock detection circuit 26, and the clock 27 is solid-state. It is supplied to the image sensor drive signal generation circuit 23. The solid-state imaging device drive signal generation circuit 23 receives the camera main-side multiplexed signal 24, separates the composite synchronization signal 34 from the control signal 370, and controls the lens unit 1 and the camera head unit 2 based on the control signal 370. Then, a state signal indicating the state of the lens unit 1 and the camera head unit 2 is inserted in a specific period (vertical blanking period) of the composite synchronizing signal and output as a camera head side multiplexed signal 25. The camera-head-side multiplexing circuit 22 mixes the video signal from the solid-state imaging device 20 and the camera-head-side multiplexed signal 25 and sends out the multiplexed output signal 220 to the camera main unit 3. Therefore, the connection between the camera main unit 3 and the camera head unit 2 can be realized with at least three wires.

[Second Embodiment: Corresponding to Claims 2 and 7] Hereinafter, an imaging apparatus according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 5 is a block diagram showing a basic configuration of an imaging device according to the second embodiment of the present invention. This image pickup apparatus uses a clock detection circuit 28 instead of the clock detection circuit 26 of FIG. 1 and omits a clock superimposing circuit. The other configuration is the same as that of FIG. In this imaging device, only the same camera-side multiplexed signal 24 as described in the first embodiment is transmitted from the camera main unit 3 to the camera head unit 2 via the cable 4. In the camera head unit 2, for example, a vertical synchronization signal is extracted from the camera main-side multiplexed signal 24 by the clock detection circuit 28, and then a PLL (Phase Locked Loop).
A clock 27 having a desired frequency is generated using a circuit. The clock 27 is supplied to the solid-state imaging device drive signal generation circuit 23, and the same operation as that of the first embodiment is performed hereinafter. Note that a power line connecting the camera main unit 3 and the camera head unit 2 is not shown.

According to the imaging apparatus of this embodiment, the lens section 1 and the camera are controlled by the CPU 37 in the camera main side multiplexing circuit 33 during the specific period (vertical blanking period) of the composite synchronizing signal 34 from the synchronizing signal generating circuit 35. The camera main-side multiplexed signal 24 into which the control signal 370 of the head unit 2 is inserted is supplied to the camera head unit 2. In the camera head unit 2, the clock detection circuit 28 reproduces the clock 27 from the camera main-side multiplexed signal 24. The solid-state image sensor drive signal generation circuit 23 receives the clock 27 and the camera main-side multiplexed signal 24 and separates the composite synchronization signal 34 from the control signal 370.
Controls the lens unit 1 and the camera head unit 2 on the basis of the control signal, and inserts a state signal indicating the state of the lens unit 1 and the camera head unit 2 into a specific period (vertical blanking period) of the composite synchronization signal, and Output as a multiplexed signal 25. The camera-head-side multiplexing circuit 22 mixes the video signal from the solid-state imaging device 20 and the camera-head-side multiplexed signal 25 and sends out the multiplexed output signal 220 to the camera main unit 3. Therefore, the connection between the camera main unit 3 and the camera head unit 2 can be realized with at least two lines except for the power supply line.

Instead of transmitting the clock directly, the clock detection circuit 28 extracts, for example, a vertical synchronizing signal from the camera main-side multiplexed signal 24 and then outputs the PLL.
Since the clock 27 having a desired frequency is generated by using a (phase locked loop) circuit, high frequency noise can be reduced. [Third Embodiment: Corresponding to Claims 3 and 7] Hereinafter, an imaging apparatus according to a third embodiment of the present invention will be described with reference to the drawings. FIG. 6 is a block diagram showing a basic configuration of an imaging device according to the third embodiment of the present invention. This imaging apparatus includes an A / D conversion circuit 301, a camera main-side multiplexing circuit 330, instead of the A / D conversion circuit 30, the camera main-side multiplexing circuit 33, and the state signal detection circuit 36 of the imaging apparatus in FIG. The state signal detection circuit 36 is used.

In this case, as described in the second embodiment, the camera main side multiplexed signal 24 is supplied to the camera head 2 and the multiplexed output signal 2
20 is output to the camera main unit 3. In the A / D conversion circuit 301 of the camera main unit 3, the phase of the sampling clock is made variable by the selection signal 302 as shown in FIG. Specifically, of the cascade-connected, for example, four-stage delay circuits 41 to 44, the sampling clock is input to the first-stage delay circuit 41, and the sampling clock input to the first-stage delay circuit 41 or the first to last stages are output. The selector 45 selects the delayed sampling clock output from each of the delay circuits 41 to 44 by the selection signal 302, and the sampling clock output from the selector 45 is input to the A / D conversion circuit 301. Will be. In the CPU 37, the multiplexed output signal 220 is output by the A / D conversion circuit 301 depending on the length of the cable 4 between the camera head unit 2 and the camera main unit 3.
A plurality of selection signals 302 for selecting an optimal sampling clock phase for sampling the data are prepared in advance. For example, by continuously supplying a predetermined selection signal 302 to the A / D conversion circuit 301 after turning on the power, The multiplexed output signal 220 operates so as to output a digital signal sampled at an optimum position.

According to the imaging apparatus of this embodiment, an optimum sampling clock can be obtained even if the length of the cable is changed. Other effects are the same as those of the second embodiment. Note that the imaging apparatus according to the first embodiment can also be configured to select the phase of the sampling clock of the A / D conversion circuit using the selection signal 302 in the same manner as described above.

[Fourth Embodiment: Corresponding to Claims 4 and 7] An image pickup apparatus according to a fourth embodiment of the present invention will be described below with reference to the drawings. FIG. 8 is a block diagram illustrating a basic configuration of an imaging device according to the fourth embodiment of the present invention. This imaging apparatus includes a lens unit 1 for photographing a subject.
And a camera head unit 2 that receives light from the lens unit 1 and performs photoelectric conversion, and a camera main unit 3 connected to the camera head unit 2 by a cable 4. Camera head 2
Comprises a solid-state imaging device 20, a sample-and-hold circuit 21, a camera head-side multiplexing circuit 22, a solid-state imaging device drive signal generation circuit 23, and a clock detection circuit 28. Also,
The camera main unit 3 includes an A / D conversion circuit 301, a digital signal processing circuit 31, a D / A conversion circuit 32, a synchronization signal generation circuit 35, a camera main-side multiplexing circuit 330, a state signal detection circuit 360, and a CPU 37. .

Then, the camera main side multiplexing circuit 330
Is the composite synchronizing signal 34 from the synchronizing signal generation circuit 35 and CP
The control signal 370 of the lens unit 1 and the camera head unit 2 supplied from U37 and the specific pattern signal 37
2 are multiplexed and transmitted to the camera head unit 2 through the cable 4 as a camera main-side multiplexed signal 240.
Further, the clock detection circuit 28 generates the clock 27 from the camera main side multiplexed signal 240. Further, the solid-state imaging device drive signal generation circuit 23 separates the composite synchronizing signal 34 and the control signal 370 from the camera main-side multiplexed signal 240 based on the clock 27, and the lens unit 1 and the camera head unit 2 according to the control signal 370. It performs control and generates a camera head side multiplexed signal 250 multiplexing the composite synchronization signal 34, the state signal of the lens unit 1 and the camera head unit 2, and a specific pattern signal. Further, the camera head side multiplexing circuit 22 converts the video signal from the solid-state imaging device 20 into a camera head side multiplexed signal 25.
0, and is sent to the camera main unit 2 through the cable 4 as a multiplexed output signal 221. Further, the state signal detection circuit 360 detects the state signals 371 of the lens unit 1 and the camera head unit 2 from the multiplexed output signal 250 from the camera head unit 2 and sends them to the CPU 37, and detects and specifies a specific pattern signal. The delay signal 373 indicating the detection time width from the transmission of the pattern signal from the CPU 37 to the camera main-side multiplexing circuit 330 to the detection of the specific pattern signal by the state signal detection circuit 360 is transmitted to the CPU.
37. Further, the CPU 37 performs a process of selecting the sampling clock phase of the A / D conversion circuit 301 based on the delay signal 373 indicating the detection time width, and
A selection signal 302 for selecting the sampling clock phase of the D conversion circuit 301 is supplied to the A / D conversion circuit 301. Further, the A / D conversion circuit 301 selects a sampling clock by the selection signal 302.

Hereinafter, this imaging device will be described in detail. In FIG. 8, the image pickup apparatus includes a composite synchronizing signal 34 from a synchronizing signal generating circuit 35, control of iris and zoom to a lens unit 1 from a CPU 37, a mode of driving a solid-state image sensor to a camera head unit 2, and the like. , A control signal 370 such as a gain control signal and a specific pattern signal 372 are multiplexed by a camera main-side multiplexing circuit 330 and transmitted as a camera main-side multiplexed signal 240 to the camera head unit 2 via the cable 4. The control signal 370 and the specific pattern signal 372 are arranged in a specific period within one field, that is, a vertical blanking period, as shown in FIG.

In the camera head unit 2, the clock detection circuit 28 receives the camera main-side multiplexed signal 240, extracts a vertical synchronizing signal, and generates a clock 27 having a desired frequency using a PLL circuit. The clock 27 is supplied to the solid-state imaging device drive signal generation circuit 23. The solid-state imaging device drive signal generation circuit 23 separates the control signal 370 from the camera main-side multiplexed signal 240 and sends it as a lens control signal 232 to the lens unit 1 and a gain control signal 234 to the sample and hold circuit 21. The solid-state imaging device 20 is driven by generating a timing signal 233 from the multiplexed signal 240 on the camera main side.

The solid-state image sensor 20 has a timing signal 23
3 to output a solid-state imaging device signal 201 obtained by photoelectrically converting the light from the lens unit 1. Solid-state image sensor signal 201
Enters the camera head side multiplexing circuit 22 after the reset noise is removed and the gain is controlled by the sample and hold circuit 21. Also, the camera head side multiplexing circuit 2
2, the camera head side multiplexed signal 250 is also supplied. The camera head-side multiplexed signal 250 is output from the solid-state image pickup device drive signal generation circuit 23 to the lens state signal 231 indicating the iris state and zoom state of the lens unit 1 and the state of the camera head unit 2 (for example, whether or not the timing signal 233 can be output). , The solid-state imaging device drive mode confirmation signal, etc.) and the specific pattern itself transmitted from the camera main unit 3 are the camera main-side multiplexed signal 2 shown in FIG.
At 40, the signal is multiplexed at the position where the control signal 370 is inserted instead of the control signal 370.

In the camera head-side multiplexing circuit 22 to which the above-described signals are input, the signal from the sample-and-hold circuit 21 and the camera head-side multiplexed signal 250 are converted into the signals shown in FIG.
0, the signals are mixed to form a multiplexed output signal 221, and the multiplexed output signal 221 is output to the camera main unit 3 via the cable 4. When receiving the multiplexed output signal 221, the state signal detection circuit 360 of the camera main unit 3 extracts the multiplexed lens state signal 231 and the state signal of the camera head unit 2 and sends them to the CPU 37 as the state signal 371. At the same time, a specific pattern is also extracted, and a delay signal 373 indicating a time difference from when the specific pattern 372 is transmitted as the camera main-side multiplexed signal 240 to when the specific pattern is detected is transmitted to the CPU 37.

The CPU 37 calculates the inter-cable delay of the multiplexed output signal 221 from the camera head unit 2 from the delay signal 373, and selects a signal 302 for selecting the optimum sampling clock phase for the A / D conversion circuit 301. Is sent. Then, in the camera main unit 3, the A / D conversion circuit 301 receives the selection signal 302, selects an optimal clock, A / D converts the multiplexed output signal 221, and performs signal processing in the digital signal processing circuit 31. , And output as a video signal by the D / A conversion circuit 32.

The state signal detection circuit 360 extracts the lens state signal 231 and the signal indicating the state of the camera head unit 2 from the multiplexed output signal 221 and supplies them to the CPU 37 as the state signal 371. In addition, the state of the camera head unit 2 can be monitored. According to the imaging apparatus of this embodiment, the camera main-side multiplexing circuit 330 sets C during a specific period (vertical blanking period) of the composite synchronizing signal 34 from the synchronizing signal generating circuit 35.
The control signal 370 for the lens unit 1 and the camera head unit 2 and the camera main-side multiplexed signal 240 into which the specific pattern 372 is inserted are supplied from the PU 37 to the camera head unit 2. Clock 2 from the side multiplexed signal 240
7, the solid-state imaging device drive signal generation circuit 23 receives the clock 27 and the camera main-side multiplexed signal 240, separates the composite synchronization signal 34 and the control signal 370,
The lens unit 1 and the camera head unit 2 are controlled based on the control signal 370, and a state signal indicating the state of the lens unit 1 and the camera head unit 2 is inserted in a specific period (vertical blanking period) of the composite synchronization signal. Then, it is output as a camera head side multiplexed signal 250. The multiplexing circuit 22 on the camera head side mixes the video signal from the solid-state imaging device 20 and the multiplexed signal 250 on the camera head side and sends out the multiplexed output signal 221 to the camera main unit 3. In the camera main unit 3, the state signal and the specific pattern are detected from the multiplexed output signal 221 by the state signal detection circuit 360, and the camera 37 outputs the camera main side multiplexing circuit 330 from the CPU 37.
The CPU 37 supplies the CPU 37 with a delay signal 373 indicating a detection time difference from the transmission of the specific pattern to the detection of the specific pattern. In the CPU 37, based on the delay signal 373, A /
The D conversion circuit 301 selects a sampling clock having an optimum phase. Therefore, the signal lines between the cables 4 can be connected with the camera main unit 3 and the camera head unit 2 in at least two lines except for the power supply line, and the cable delay and the change in the cable length can be reduced. A / D
The conversion circuit 301 can obtain an optimal sampling clock.

Instead of transmitting the clock directly, the clock detection circuit 28 extracts, for example, a vertical synchronizing signal from the camera main-side multiplexed signal 24 and then outputs the PLL.
Since the clock 27 having a desired frequency is generated by using a (phase locked loop) circuit, high frequency noise can be reduced. [Fifth Embodiment: Corresponding to Claim 5] In a fifth embodiment of the present invention, the CPU 37 in FIG. 8 samples the delay signal 373 from the delay signal 373 only at the time of turning on the power or only at a specific time of a certain period. A process for calculating the clock phase is performed, and the selection signal 302 based on the result is set to A /
The operation is performed so as to output the data to the D conversion circuit 301 and hold the data or to hold the data until the next specified time.
Other configurations are the same as those of the fourth embodiment. The specific time of the fixed period is, for example, a vertical blanking period of one field period (1/60 second in NTSC). This cycle is 1 field cycle × n
(N: integer).

According to the imaging apparatus of this embodiment, the CP
U37 performs the process of selecting the sampling clock phase in accordance with the delay signal 373 for the A / D conversion circuit 301 only at the time of turning on the power or only at a specific time of a fixed period. I try to hold. Therefore, by setting the detection of the specific pattern and the transmission / extraction of the control signal to the specific time, the load on the CPU 37 can be reduced and the influence of noise on the video signal in the cable 4 can be reduced. Other effects are similar to those of the fourth embodiment.

[Sixth Embodiment: Corresponding to Claim 6] Hereinafter, an imaging apparatus according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 11 is a block diagram illustrating a basic configuration of an imaging device according to the sixth embodiment of the present invention. The imaging apparatus includes a lens unit 1 for photographing a subject,
It comprises a camera head unit 2 that receives light from the lens unit 1 and performs photoelectric conversion, and a camera main unit 3 connected to the camera head unit 2 by a cable 4. The camera head 2 is
It comprises a solid-state imaging device 20, a sample-and-hold circuit 21, a camera head side selection multiplexing circuit 223, a solid-state imaging device drive signal generation circuit 23, and a clock detection circuit 28. The camera main unit 3 includes an A / D conversion circuit 301, a digital signal processing circuit 31, a D / A conversion circuit 32, a synchronization signal generation circuit 35, a camera main side multiplexing circuit 331, a state signal detection circuit 361, a CPU 37, Consists of

Then, the camera main side multiplexing circuit 331
Is the composite synchronizing signal 34 from the synchronizing signal generation circuit 35 and CP
The control signal 370 and the specific pattern signal 3 of the lens unit 1 and the camera head unit 2 supplied from U37 only for a specific time (for example, when the power is turned on or when a certain mode is changed).
72 are multiplexed and sent to the camera head unit 2 through the cable 4 as a camera main side multiplexed signal 241. Further, the clock detection circuit 28 generates the clock 27 from the camera main side multiplexed signal 241. Also,
The solid-state imaging device drive signal generation circuit 23 converts the composite synchronization signal 3 from the camera main side multiplexed signal 241 based on the clock 27.
4 and the control signal 370 inserted only for a specific time, the lens unit 1 and the camera head unit 2 are controlled according to the control signal 370, and the lens unit 1 and the camera head unit 2 are controlled with respect to the composite synchronization signal 34. A camera head side multiplexed signal 252 is generated by multiplexing the status signal and the specific pattern signal only for the specific time. Note that the control signal 370 of the lens unit 1 and the camera head unit 2 and the specific pattern signal 372 are multiplexed in the vertical blanking period (specific period) of the composite synchronization signal. The above-mentioned mode change is, for example, a time when the aperture and zoom of the lens unit 1 are changed, and is performed periodically. The cycle is a one-field cycle or an integer n-field cycle, and the vertical blanking period in each cycle corresponds to a specific time.

The camera head side selective multiplexing circuit 22
3 transmits only the camera head side multiplexed signal 252 to the camera main unit 2 through the cable 4 as the selective multiplexed output signal 222 for a specific time, and outputs the video signal from the solid-state imaging device 20 to the camera for a normal time other than the specific time. The signal is superimposed on the head-side multiplexed signal 252 and transmitted as a selective multiplexed output signal 222 to the camera main unit 3 through the cable 4. The state signal detection circuit 361 detects the state signals of the lens unit 1 and the camera head unit 2 from the selective multiplexed output signal 222 from the camera head unit 2 only for a specific time, and
The signal is sent to the PU 37 and a specific pattern signal is detected. From the transmission of the specific pattern signal from the CPU 37 to the camera main-side multiplexing circuit 331, the state signal detecting circuit 361 is detected.
A delay signal 373 indicating the detection time width until the detection of the specific pattern signal is sent to the CPU 37. Also, C
The PU 37 performs a process of selecting the sampling clock phase of the A / D conversion circuit 301 based on the delay signal 373 indicating the detection time width, and outputs a selection signal 302 for selecting the sampling clock phase of the A / D conversion circuit 301 to A / D. It is supplied to the conversion circuit 301. The A / D conversion circuit 30
1 selects a sampling clock by the selection signal 302.

Hereinafter, this imaging device will be described in detail. The imaging apparatus includes a composite synchronizing signal 34 from a synchronizing signal generation circuit 35 and a specific time (for example, when power is turned on,
Only when the mode is changed periodically) the CPU 37 controls the iris and zoom to the lens unit 1, the mode of driving the solid-state imaging device to the camera head unit 2, the control signal 370 such as a gain control signal and a specific pattern The signal 372 is multiplexed with the camera main-side multiplexing circuit 331 and transmitted as a camera main-side multiplexed signal 241 to the camera head unit 2 via the cable 4. The control signal 370 and the specific pattern signal 372 are arranged in a vertical blanking period within one field.

In the camera head unit 2, the clock detection circuit 28 receives the camera main-side multiplexed signal 241 and, for example, extracts a vertical synchronizing signal and generates a clock 27 having a desired frequency using a PLL circuit. The clock 27 is supplied to the solid-state imaging device drive signal generation circuit 23. The solid-state image sensor drive signal generation circuit 23 separates the control signal 370 from the camera main-side multiplexed signal 241 and sends it as a lens control signal 232 to the lens unit 1 and a gain control signal 234 to the sample and hold circuit 21. The timing signal 233 is generated from the camera main-side multiplexed signal 241 to drive the solid-state imaging device 20.

The solid-state image sensor 20 has a timing signal 23
3 to output a solid-state imaging device signal 201 obtained by photoelectrically converting the light from the lens unit 1. Solid-state image sensor signal 201
Enters the camera head side selective multiplexing circuit 223 after reset noise removal and gain control by the sample and hold circuit 21. Further, the camera head side selective multiplexing circuit 223 includes a camera head side selective multiplexing signal 2.
52 is also provided. The camera head side selective multiplexing signal 252 is output from the solid-state image sensor drive signal generation circuit 23 to the lens state signal 231 indicating the iris state and zoom state of the lens unit 1 and the state of the camera head unit 2 (for example, the output of the timing signal 233). 9 and the specific pattern itself transmitted from the camera main unit 3 are included in the control signal 3 in the camera main-side multiplexed signal 241 shown in FIG.
The control signal 370 is multiplexed instead of the control signal 370 at the position where 70 is inserted.

In the camera head side selective multiplexing circuit 223 to which the above signals are inputted, the video signal from the sample hold circuit 21 and the camera head side multiplexed signal 252
(A state signal and a specific pattern signal are multiplexed only for a specific time) and a selected multiplexed output signal 22
2, and outputs the selective multiplexed signal 222 to the camera main unit 3 via a cable.

At a specific time, when the selective multiplexed output signal 222 is received by the state signal detecting circuit 361 of the camera main unit 3, the multiplexed lens state signal 231 and the state signal of the camera head unit 2 are extracted, and A specific pattern is extracted as well as a signal 371 to the CPU 37, and a delay signal 373 indicating a time difference from transmission to detection is transmitted to the CPU 37 as a camera main-side multiplexed signal 241.

The CPU 37 calculates the delay between the cables of the selective multiplexed output signal 222 from the camera head unit 2 from the delay signal 373, and selects the optimum sampling clock phase for the A / D conversion circuit 301. The selection signal 302 is transmitted, and the selection signal 302 is held until the next specific time. After receiving the selection signal 302 in the A / D conversion circuit 301 and selecting the optimum clock, the camera head side selection and multiplexing circuit 223 selects the solid-state imaging device signal 201 from the sample and hold circuit 21 and selects and multiplexes the output signal. The signal is sent to the camera main unit 3 as 222, A / D-converted, then subjected to signal processing by the digital signal processing circuit 31, and output as a video signal by the D / A conversion circuit 32.

The state signal detection circuit 360 extracts the lens state signal 231 and the signal indicating the state of the camera head unit 2 from the multiplexed output signal 221 and supplies them to the CPU 37 as a state signal 371. In addition, the state of the camera head unit 2 can be monitored. Note that, in this embodiment, the same reference numerals as those in the previous embodiment have the same configuration.

According to the imaging apparatus of this embodiment, C is used only for a specific time (for example, when power is turned on or when a certain mode is changed).
A specific pattern is transmitted from the PU 37, the control signal 370 is multiplexed with the composite synchronizing signal 34 by the camera main-side multiplexing circuit 331 and inserted into the camera head unit 2 as the camera main-side multiplexed signal 241. The clock reproduction and the control signal are separated from the multiplexed signal 241 on the camera main side, and the multiplexed signal 252 on the camera head side is output from the solid-state image sensor drive signal generation circuit 23.
Is supplied to the camera head side selective multiplexing circuit 223. The camera head side selective multiplexing circuit 223 converts the video signal from the solid-state imaging device 20 into a camera head side multiplexed signal 252.
To the camera head side multiplexed signal 25 or
Select whether to send only 2. When inserting a specific pattern,
The camera-head-side multiplexed signal 222 is selected, the state signal detection circuit 361 detects the time difference from the time of transmission of the specific pattern to the time of detection, and passes it to the CPU 37 as a delay signal 373.
The CPU 37 supplies the selection signal 302 to the A / D conversion circuit 301 based on the delay signal 373. Therefore, the signal lines between the cables 4 must be at least 2 except for the power line.
The connection between the camera main unit 3 and the camera head unit 2 can be realized by the number of the lines, and the A / D conversion circuit 301 obtains an optimal sampling clock with respect to a cable delay and a change in cable length. be able to.

Instead of transmitting the clock directly, the clock detection circuit 28 extracts, for example, a vertical synchronizing signal from the camera main-side multiplexed signal 24,
Since the clock 27 having a desired frequency is generated by using a (phase locked loop) circuit, high frequency noise can be reduced. In addition, by setting the specific pattern detection and the transmission / extraction of the control signal to a specific time, the CPU load can be reduced and the influence of noise on the video signal in the cable can be reduced. Further, by completely switching and transmitting the video signal from the solid-state imaging device 20 and the status signal of the camera head side multiplexed signal 252 and the specific pattern signal without multiplexing, the influence of noise on the video signal can be further reduced. It is possible to reduce the number and obtain a high quality video signal.

[0060]

According to the imaging apparatus of the first or second aspect, there is an effect that the camera head unit and the camera main unit can be connected with a small number of cables. In particular, in the case of the imaging device of claim 2, without directly transmitting a clock,
Since the clock is generated from the synchronization signal, the influence of high frequency noise can be reduced.

According to the image pickup apparatus of the third or fourth aspect, the camera head and the camera main can be connected with a small number of cables, and the clock in the camera head can be changed even if the cable length changes. Realize playback,
Further, it is possible to perform sampling at an optimal position for A / D conversion in the camera main unit, and it is possible to obtain a video signal with less deterioration in resolution. Further, since the clock is generated from the synchronization signal without directly transmitting the clock, the influence of high frequency noise can be reduced.

Further, according to the image pickup apparatus of the fifth aspect, in addition to the effect of the fourth aspect, the detection of the specific pattern and the transmission / extraction of the control signal are set to the specific time, so that the CP can be used.
There is also an effect that the U load can be reduced and the influence of noise on the video signal in the cable can be reduced. Furthermore, according to the imaging apparatus of the sixth aspect, since the clock is generated from the synchronization signal without directly transmitting the clock, the influence of high frequency noise can be reduced, and the specific pattern detection and control can be performed. By setting the signal transmission / extraction to a specific time, C
Reduce the PU load and reduce the influence of noise on the video signal in the cable, and completely multiplex the video signal from the solid-state image sensor with the status signal of the camera head side multiplexed signal and a specific pattern signal By switching and transmitting without switching, the effect of noise on the video signal can be further reduced, and there is also an effect that a high-quality video signal can be obtained.

Further, according to the image pickup apparatus of the present invention, it is possible to control the lens unit and monitor the state of the lens unit without increasing the number of cables.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an imaging device according to a first embodiment of the present invention.

FIG. 2 is a timing chart showing a waveform of a camera main-side multiplexed signal in the imaging device according to the first embodiment of the present invention.

FIG. 3 is a block diagram illustrating a configuration of a clock detection circuit in the imaging device according to the first embodiment of the present invention.

FIG. 4 is a timing chart showing a waveform of a multiplexed output signal in the imaging device according to the first embodiment of the present invention.

FIG. 5 is a block diagram illustrating a configuration of an imaging device according to a second embodiment of the present invention.

FIG. 6 is a block diagram illustrating a configuration of an imaging device according to a third embodiment of the present invention.

FIG. 7 is a block diagram illustrating a configuration of a sampling clock selection unit of an A / D conversion circuit in an imaging device according to a third (or fourth, fifth, or sixth) embodiment of the present invention.

FIG. 8 is a block diagram illustrating a configuration of an imaging device according to fourth and fifth embodiments of the present invention.

FIG. 9 is a timing chart showing a waveform of a camera-main-side multiplexed signal in the imaging apparatus according to the fourth embodiment of the present invention.

FIG. 10 is a timing chart showing a waveform of a multiplexed output signal in an imaging device according to a fourth embodiment of the present invention.

FIG. 11 is a block diagram illustrating a configuration of an imaging device according to a sixth embodiment of the present invention.

FIG. 12 is a block diagram illustrating a configuration of a conventional imaging apparatus.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Lens part 2 Camera head part 3 Camera main part 4 Cable 20 Solid-state image sensor 201 Solid-state image sensor signal 21 Sample hold circuit 22 Camera head side multiplexing circuit 220 Multiplexed output signal 221 Multiplexed output signal 222 Multiplexed output signal 223 Camera Head-side selective multiplexing circuit 23 Solid-state imaging device drive signal generating circuit 231 Lens state signal 232 Lens control signal 233 Timing signal 234 Gain control signal 24 Camera main-side multiplex signal 240 Camera main-side multiplex signal 241 Camera main-side multiplex signal 25 Camera head side multiplexed signal 250 Camera head side multiplexed signal 252 Camera head side multiplexed signal 26 Clock detection circuit 261 Power line 262 High pass filter 263 Low pass filter 27 Clock 8 Clock detection circuit 30 A / D conversion circuit 301 A / D conversion circuit 302 Selection signal 31 Digital signal processing circuit 32 D / A conversion circuit 33 Camera main side multiplexing circuit 330 Camera main side multiplexing circuit 331 Camera main side multiplexing Circuit 34 Composite synchronization signal 35 Synchronization signal generation circuit 36 State signal detection circuit 360 State signal detection circuit 361 State signal detection circuit 37 CPU 370 Control signal 371 State signal 372 Specific pattern signal 373 Delay signal 38 Clock superimposition circuit 381 Power supply line 382 Clock Reference Signs List 90 camera head unit 91 solid-state imaging device 92 sample-hold circuit 93 AGC circuit 94 solid-state imaging device drive signal generation circuit 95 synchronization signal generation circuit 96 selection circuit 97 CPU 98 cable 100 camera main unit 101 CPU 1 02 Horizontal synchronization signal detection circuit 103 Vertical synchronization signal detection circuit 104 Clock detection circuit 105 Digital signal processing circuit 106 A / D conversion circuit 107 D / A conversion circuit

Claims (7)

[Claims] A camera head comprising a solid-state imaging device, a sample-and-hold circuit, a camera head-side multiplexing circuit, a solid-state imaging device drive signal generation circuit, and a clock detection circuit;
A camera main unit including an A / D conversion circuit, a signal processing circuit, a D / A conversion circuit, a synchronization signal generation circuit, a camera main-side multiplexing circuit, a state signal detection circuit, a clock superimposition circuit, and a CPU; An imaging apparatus in which a head unit and the camera main unit are connected by a cable, wherein the camera main side multiplexing circuit controls a composite synchronization signal from the synchronization signal generation circuit and the camera head unit supplied from the CPU. Multiplexing the signal and sending it to the camera head section through the cable as a camera main-side multiplexed signal; the clock superimposing circuit superimposing a clock on a power supply line and sending the signal to the camera head section through the cable; A circuit for separating the clock superimposed on the power supply line; Separating the composite synchronization signal and the control signal from the camera main-side multiplexed signal based on a clock, controlling the camera head unit according to the control signal, and controlling the state of the composite synchronization signal and the camera head unit A camera head-side multiplexed signal is generated by multiplexing the signal and the camera head-side multiplexed circuit superimposes a video signal from the solid-state imaging device on the camera head-side multiplexed signal,
A multiplexed output signal is sent to the camera main unit through the cable, and the state signal detection circuit detects a state signal of the camera head unit from the multiplexed output signal from the camera head unit and sends it to the CPU. An imaging device, comprising: 2. A camera head comprising a solid-state image sensor, a sample-and-hold circuit, a camera-head-side multiplexing circuit, a solid-state image sensor drive signal generation circuit, and a clock detection circuit.
A camera main unit including an A / D conversion circuit, a signal processing circuit, a D / A conversion circuit, a synchronization signal generation circuit, a camera main side multiplexing circuit, a state signal detection circuit, and a CPU; An imaging apparatus in which a camera main unit is connected by a cable, wherein the camera main side multiplexing circuit multiplexes a composite synchronization signal from the synchronization signal generation circuit and a control signal of the camera head unit supplied from the CPU. And sends it to the camera head section through the cable as a camera main-side multiplexed signal, the clock detection circuit generates the clock from the camera main-side multiplexed signal, and the solid-state imaging device drive signal generation circuit generates the clock. The composite synchronizing signal and the control signal are separated from the camera main-side multiplexed signal based on the The camera head unit is controlled in accordance with a roll signal, and a camera head-side multiplexed signal is generated by multiplexing the composite synchronization signal and the status signal of the camera head unit. Superimposing the video signal from the image sensor on the camera head side multiplexed signal,
A multiplexed output signal is sent to the camera main unit through the cable, and the state signal detection circuit detects a state signal of the camera head unit from the multiplexed output signal from the camera head unit and sends it to the CPU. An imaging device, comprising: 3. The plurality of selection signals for providing a CPU with a plurality of selection signals defined in advance by a cable length, and selecting a sampling clock phase of an A / D conversion circuit by setting a cable length in the CPU. The imaging device according to claim 1, wherein any one of the following is supplied to the A / D conversion circuit. 4. A camera head comprising a solid-state imaging device, a sample-and-hold circuit, a camera-head-side multiplexing circuit, a solid-state imaging device drive signal generation circuit, and a clock detection circuit.
An A / D conversion circuit, a signal processing circuit, a D / A conversion circuit, a synchronization signal generation circuit, a camera main-side multiplexing circuit, a status signal detection circuit for detecting a status signal of the camera head, and a CP
And a camera main unit consisting of a U and a camera main unit, wherein the camera head unit and the camera main unit are connected by a cable, wherein the camera main side multiplexing circuit is a composite synchronization signal from the synchronization signal generation circuit. And a control signal of the camera head unit supplied from the CPU and a specific pattern signal are multiplexed and transmitted to the camera head unit through the cable as a camera main side multiplexed signal. The clock is generated from a multiplexed signal, and the solid-state imaging device drive signal generation circuit separates the composite synchronization signal and the control signal from the camera main side multiplexed signal based on the clock, and according to the control signal, Controls the camera head unit, and controls the composite synchronization signal and the camera head unit. Generating a camera head side multiplexed signal obtained by multiplexing a state signal and the specific pattern signal, wherein the camera head side multiplexing circuit superimposes a video signal from the solid-state imaging device on the camera head side multiplexed signal. ,
A multiplexed output signal is sent to the camera main unit through the cable, and the status signal detection circuit detects a status signal of the camera head unit from the multiplexed output signal from the camera head unit and sends it to the CPU. Indicates the detection time width from detection of the specific pattern signal to transmission of the specific pattern signal from the CPU to the camera main-side multiplexing circuit to detection of the specific pattern signal by the state signal detection circuit. Sending a delay signal to the CPU, the CPU performing a process of selecting a sampling clock phase of the A / D conversion circuit based on the delay signal indicating the detection time width; Is supplied to the A / D conversion circuit, and the A / D conversion circuit receives a signal based on the selection signal. Imaging apparatus being characterized in that to choose a ring clock. 5. The CPU according to claim 1, wherein the CPU performs a process of selecting a sampling clock phase according to the delay signal to the A / D conversion circuit only for a specific time, and holds the selection signal for a time other than the specific time. The imaging device according to claim 4, wherein: 6. A camera head unit including a solid-state image sensor, a sample-and-hold circuit, a camera head-side selective multiplexing circuit, a solid-state image sensor drive signal generation circuit, and a clock detection circuit, an A / D conversion circuit, and a signal processing circuit. A camera main unit including a D / A conversion circuit, a synchronization signal generation circuit, a camera main side multiplexing circuit, a state signal detection circuit for detecting a state signal of the camera head unit, and a CPU; An imaging apparatus in which a camera main unit is connected by a cable, wherein the camera main-side multiplexing circuit is supplied with a composite synchronization signal from the synchronization signal generation circuit and a control signal of the camera head unit supplied only for a specific time from the CPU. And a specific pattern signal are multiplexed and transmitted to the camera head section through the cable as a camera main side multiplexed signal. The clock detection circuit generates the clock from the camera main-side multiplexed signal, and the solid-state imaging device drive signal generation circuit generates the composite synchronization signal and the specific time from the camera main-side multiplexed signal based on the clock. Only the control signal inserted is separated, the camera head unit is controlled according to the control signal, and the status signal of the camera head unit and the specific pattern signal are identified with respect to the composite synchronization signal. A camera head side multiplexed signal multiplexed only in time is generated, and the camera head side selective multiplexing circuit transmits only the camera head side multiplexed signal as the selective multiplexed output signal to the camera main unit through the cable during the specific time. Send out,
During a normal time other than the specific time, a video signal from the solid-state imaging device is superimposed on the camera head side multiplexed signal, and sent to the camera main unit through the cable as a selective multiplexed output signal, and the state signal detection circuit Detects the status signal of the camera head unit from the selective multiplexed output signal from the camera head unit only for the specific time and sends it to the CPU, and detects the specific pattern signal to detect the specific pattern signal. A delay signal indicating a detection time width from transmission from the CPU to the camera main-side multiplexing circuit to detection of the specific pattern signal by the state signal detection circuit is sent to the CPU, and the CPU detects the detection time width. Performing a process of selecting a sampling clock phase of the A / D conversion circuit based on a delay signal indicating Imaging apparatus characterized by supplying a selection signal for selecting a sampling clock phase of the circuit to the A / D converter circuit, the A / D conversion circuit is to select the sampling clock by the selection signal. 7. The control signal according to claim 1, wherein a lens control signal for controlling a lens unit for photographing the subject is included in the control signal, and a lens state signal indicating a state of the lens unit is included in the state signal. The imaging apparatus according to claim 2, 3, 4, 5, or 6.