JP2009038764A - Video signal multiplex transmission device, and imaging apparatus employing video signal multiplex transmission device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To transmit asynchronous video signals input to a control section to an adapter section without using a frame synchronizer of the control section. <P>SOLUTION: A digital triax system is disclosed for two-way transmission of serial digital signals between the control section and an adapter section connected to an imaging section via a triax cable, wherein a clock frequency of an asynchronous external input video signal and a horizontal synchronizing frequency are synchronized by a line memory within the control section, and the video signal is then data-compressed and transmitted to the adapter section. The compressed video signal is expanded after synchronizing a vertical synchronizing frequency by a frame memory within the adapter section, and then output as an external video signal. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

The present invention relates to an improvement of a transmission method in a video signal multiplex transmission apparatus used for an imaging apparatus such as a television camera apparatus.

  Conventionally, in a television camera system, a main line video signal, a return video signal, an audio signal, a control serial data signal, between an adapter unit connected to an imaging unit (camera head) and a control unit (Camera Control Unit: CCU), In addition, a method of performing time-division bidirectional transmission for power transmission / reception through a transmission line of one triple coaxial cable is called a digital triax system. As a simple method, a normal coaxial cable may be used for the transmission line.

  Main video signals include NTSC with 485 effective scanning lines as SDTV and PAL with 575 effective scanning lines, 720 effective scanning lines and 1080 effective scanning lines as HDTV, 2160 effective scanning lines as SHDTV, and effective scanning as UHDTV. There are 4320 lines, and NTSC will be described as a representative.

The NTSC 10-bit 4: 2: 2 broadcast video digital signal output from the imaging unit has a data amount of 270 Mbps, and the sent-back video signal has a data amount of about 50 Mbps even after data compression (hereinafter video compression). In the case of time-division bidirectional transmission, the video signal is time-compressed and converted to a signal of about 360 Mbps and transmitted from the adapter unit connected to the imaging unit to the control unit intermittently in a short time. Then, during a period free by time compression, the video signal of the return signal time-compressed to 360 Mbps is intermittently transmitted in a short time from the control unit to the adapter unit connected to the imaging unit. The process is switched by an input / output switch at a rate of several times per second to realize time-division bidirectional transmission (Patent Document 1).
Japanese Patent Laid-Open No. 7-203399

  When a digital triax system is used in a TV station studio, etc., images from other on-air cameras and an announcer script are input to the control unit, and the video signals are transmitted to the adapter unit via a triax cable. Video may be output to the camera viewfinder or script projection device. At that time, there is no problem if the video signal input to the control unit is synchronously coupled with the digital triax system. However, in the case of an asynchronous video signal that is not so, a frame synchronizer is usually used to compress the video signal. It is necessary to buffer video signals for frames in a memory and synchronize clock frequency and horizontal / vertical frequency.

  However, when the frame synchronizer is to be built in the camera control device, an external frame memory such as a Synchronous Dynamic Random Access Memory (SY-DRAM) is required, which increases the cost.

  An object of the present invention is to solve the above problems and to improve a bidirectional transmission method that eliminates the need for a frame synchronizer in a camera control apparatus.

  In order to achieve the above object, the present invention provides a video signal multiplex transmission apparatus that bi-directionally transmits a digital signal including a digitized video signal, audio signal, and control signal via a single transmission line. On the signal input side, an external synchronization unit that generates a clock synchronized with an external video signal input, a timing generator that supplies a clock and horizontal synchronization synchronized with the line memory and the system, and a video compression unit that compresses the data amount of the video signal A frame memory for storing compressed video, a timing generator for supplying a vertical synchronization signal synchronized with the system, and a video decompression unit on the external video signal output side, and a system on the external video signal input side By writing to the line memory with a clock synchronized with the asynchronous external video signal input and reading from the line memory with a clock synchronized with the system The external video signal input asynchronous with the system is synchronized with the clock frequency and the horizontal synchronization frequency using a line memory, the data amount of the external video signal is compressed and transmitted, the received external video signal is expanded, A video signal multiplex transmission device that synchronizes and outputs a vertical synchronization frequency by reading out a compressed frame from a frame memory that stores a compressed video in synchronization with a system.

  Moreover, it is an imaging device provided with said video signal multiplex transmission apparatus.

  As described above, according to the present invention, when an asynchronous video signal is input to the control unit, the clock frequency and the horizontal synchronization frequency, which are the minimum requirements for video compression in the control unit, are synchronized. Since this synchronization may be performed by a line memory for 1H, it can be configured by a memory built in an existing general-purpose digital IC such as an FPGA. Then, the video is compressed with the synchronized signal, transmitted to the adapter unit with the triax cable, and when the video signal is expanded with the adapter unit, by synchronizing the vertical frequency using the frame memory, A frame synchronizer in the control unit is not required.

  FIG. 1 is a block diagram showing an entire triax system according to an embodiment of the present invention, and a schematic diagram showing line memory input / output signals of a control unit according to an embodiment of the present invention. This will be described with reference to FIG.

  In FIG. 1 of the block diagram showing the entire triax system of one embodiment of the present invention, an external input serial digital video signal input to the control unit 48 is waveform-equalized by a cable equalizer (EQ) 1 and then clocked. The data recovery unit (CDR) 2 extracts data and a clock synchronized with the data. Then, the serial-parallel converter 3 converts the clock and data into a 10-bit parallel signal. Next, the TRS (timing reference signal) detection unit 4 detects SAV (start of active video) and EAV (end of active video), and only the horizontal effective video signal from SAV to EAV is stored in the line memory 6. The SAV / EAV and the horizontal blanking signal are discarded by the TRS removal unit 5. Here, the write address counter 7 of the line memory 6 is a 1716 frequency division counter in which the first horizontal effective video signal immediately after SAV is address 0 and the last word of SAV is address 1715. On the other hand, the read address counter 8 is controlled by a horizontal address counter 10 synchronized with a timing generator 11 inside the camera control device. The horizontal effective video data read from the line memory 6 is added with SAV, EAV and horizontal blanking by the TRS adding unit 13. The line memory 6 can synchronize the clock frequency and horizontal synchronization frequency of the input video signal with the timing in the control unit 48. The input / output data of this line memory is shown in FIG. 2 which is a schematic diagram showing the line memory input / output signals of the control unit of one embodiment of the present invention.

  Here, the horizontal address of the TRS addition unit is synchronized with the timing generation unit 11 inside the control unit 48, but the vertical phase is the TRS of the video signal input to the control unit 48 regardless of the timing inside the control unit 48. Can forcibly reset at most once per frame. Here, the maximum of once means that a reset is performed once per frame when the difference between the clock frequency of the input video signal and the clock frequency in the camera control device is accumulated until it cannot be absorbed by the line memory. It is. This prevents the video from synchronizing in the vertical direction. In addition, resetting is performed by TRS in the vertical blanking so that the image is not disturbed by resetting.

  Next, the video signal to which TRS is added is sent to the video compression unit 14 and buffered for one frame screen in the frame memory 15, and then compression is started. The compressed data is adjusted in the amount of transmission data in the buffer memory 16 and then time-division multiplexed in the multiplexing unit 17 together with the synchronization data and the control data output from the CPU 18, and the control unit passes through the switch 19 and the plug 40. 48. Here, the switch 19 is for switching the input and output by a timing unit 11 of the control unit 48 in a predetermined time unit (about 1.6 milliseconds in this embodiment). The signal flow when the switch is on the output side is as described above. However, when the switch is on the input side, the uncompressed video signal of the imaging unit from which blanking has been removed is input from the adapter unit 47 side, and the buffer memory 20 After the blanking time is adjusted, EAV, SAV, and blanking are added by the TRS adding unit 21, and the parallel-serial conversion unit 22 outputs the serial digital video signal from the control unit 48.

  On the other hand, the adapter unit 47 separates the data sent from the control unit 48 via the triax cable 23 and the plug 39 through the switch 24 and the separation unit 25 separates the compressed video data from the synchronization data and the control data. Here, the switch 24 is time-division bi-directional between the control unit 48 and the adapter unit 47 by switching the input and output by the timing generation unit 30 of the adapter unit 47 and synchronizing the switch timing with the switch 19 of the control unit 48. Realizes transmission.

  The compressed video data is sent to the video decompression unit 27 after the data transfer speed is adjusted by the buffer memory 26. Here, by using the frame memory 28 to absorb the deviation of the vertical frequency generated on the control unit 48 side and performing the video expansion process, the frame can be finally synchronized. Note that the frame memory 28 is originally necessary in order to prevent the underflow of the compressed video data during the video expansion process, and is not newly added to carry out the present invention.

  Thereafter, the expanded video signal is converted into an analog composite video signal by the VBS encoder 29 and output from the adapter unit 47.

  In addition, the synchronization data serves as a reference signal source for the timing generator 30, and a black burst signal generator 31 outputs a genlock signal to the camera. Since the imaging unit 46 outputs a video signal synchronized with this genlock signal, first, the rate conversion unit 32 resamples the video data with the clock in the adapter unit 47, removes blanking by the buffer memory 33, and then the same. It is time-division multiplexed by the multiplexing unit 34 together with the control signal coming from the imaging unit 46 and transmitted to the control unit 48 in accordance with the output timing of the switch 24.

  The incident light from the imaging unit 46 passes through the lens 41 and is split into three colors of red (R), green (G), and blue (B) by the color separation optical system (Prism) 42, respectively. It is converted into a digital video signal by the image sensor 43. The image sensor 43 may be a CMOS image sensor, a CCD image sensor, a drive circuit, CDS, AGC, and A / D.

  The digital video signal from the image sensor 43 is subjected to signal processing such as black balance, white balance, and γ correction in the video signal processing unit 45. The output signal from the video signal processing unit 45 is time-compressed by the rate conversion unit 32 and the buffer memory 33 of the adapter unit 47, and the audio signal, CPU data, utility data (cable correction circuit setting data, etc.) and the multiplexing unit 34. The signals are multiplexed and transmitted to the control unit 48 through the switch 24, the plug 39, and the triax cable 23.

The block diagram which shows the whole triax system of one Example of this invention The schematic diagram which showed the line memory input / output signal of the control part of one Example of this invention

Explanation of symbols

1: cable equalizer (EQ), 2: clock data recovery unit (CDR), 3: serial-parallel conversion unit, 4: TRS detection unit, 5: TRS removal unit, 6: line memory, 7: write address counter, 8 : Read address counter, 9: Vertical address counter, 10: Horizontal address counter, 11: Timing generator, 12: TRS generator, 13: TRS adder, 14: Video compressor, 15: Frame memory, 16: Buffer memory 17, 34: Multiplexer, 18, 44: CPU, 19: Switch, 20: Buffer memory, 21: TRS addition unit, 22: Parallel-serial converter, 23: Triax cable, 24: Switch, 25: Separation Circuit: 26: Buffer memory, 27: Video expansion unit, 28: Frame memory, 29: VBS encoder , 30: timing generating unit, 31: black burst generator, 32: rate conversion unit, 33: buffer memory,
39, 40: Plug, 41: Lens unit, 42: Color separation optical system, 43: Imaging element, 45: Video signal processing unit, 46: Imaging unit, 47: Adapter unit, 48: Control unit

Claims (2)

In a video signal multiplex transmission device that bidirectionally transmits a digital signal including a digitized video signal, audio signal, and control signal through one transmission path,
On the external video signal input side, an external synchronization unit that generates a clock synchronized with the external video signal input, a timing generator that supplies a clock synchronized with the line memory and the system, and a horizontal synchronization, and a video compression that compresses the data amount of the video signal A frame memory for storing compressed video, a timing generation unit for supplying a vertical synchronization signal synchronized with the system, and a video decompression unit on the external video signal output side,
On the external video signal input side, writing to the line memory with a clock synchronized with the external video signal input asynchronous with the system, and reading from the line memory with a clock synchronized with the system,
The external video signal input asynchronous with the system is synchronized with the clock frequency and the horizontal synchronization frequency using a line memory, the data amount of the external video signal is compressed and transmitted, the received external video signal is expanded,
By reading from the frame memory that stores the compressed video with the vertical synchronization signal synchronized with the system,
A video signal multiplex transmission apparatus characterized by synchronizing and outputting a vertical synchronization frequency. An image pickup apparatus comprising the video signal multiplex transmission apparatus according to claim 1.

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