JPH09214909A - Digital transmitter and digital camera system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To comparatively easily perform digital transmission even in the case of an analog signal asynchronous with a system without omitting any information when it is desired to perform the digital transmission of such an asynchronous analog signal inside the system. SOLUTION: After analog/digital(A/D) conversion 26B1 of the analog signal asynchronous with the system by the internal clock of the system, during the non-transmission period of a synchronizing code to be used for transmission inside the system, these digital data after the A/D conversion are inserted by performing time base compression 26B2. At such a time, on the system side, the analog signal is converted to digital data by a timing signal on the system side regardlessly of phase relation between the analog signal of a transmitting object and the synchronizing signal of the system, time base compression is performed and these relevant compressed data are inserted within the prescribed period so that circuit configuration can be simplified.

Description

Detailed Description of the Invention

[0001]

[Table of Contents] The present invention will be described in the following order. TECHNICAL FIELD OF THE INVENTION Conventional Technology Problems to be Solved by the Invention Means for Solving the Problems Embodiments of the Invention (1) Configuration of Digital Camera System (1-1) Overall Configuration (FIG. 1) (1-2) ) Configuration of camera head unit (CHU) and camera control unit (CCU) (FIGS. 2 and 3) (1-2-1) Configuration of CCU (FIGS. 4 to 7) (1-2-2) Configuration of CHU (FIGS. 8 and 9) (1-2-3) In the case of composite transmission system (FIG. 10) (1-2-4) Effects of the embodiment (2) Other embodiments Effects of the invention

[0002]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital transmission device and a digital camera system. In particular, it is suitable for application to an apparatus and a system in which it is necessary to multiplex an asynchronous analog video signal with a digital video signal transmitted / received by a serial digital interface (SDI).

[0003]

2. Description of the Related Art As a method of transmitting a component digital video signal, SDI specified by SMTPE259M is generally used. In addition to this, there is a parallel transmission standard defined by SMTPE125M, but in either case, in order to detect the horizontal sync timing and vertical sync timing of a digital video signal, TRS (Timing reference) is provided during a horizontal blanking period. signal) or EAV
(End of Active Video), SAV (Start of Active Video)
A special code called Video) is inserted. An example of this is shown in FIGS. 13 (A) and 13 (B).

Nowadays, in a camera system operated in a broadcasting station, a system capable of time-division multiplexing and transmitting a plurality of digital video signals is required because it is necessary to handle many images at the same time. Even when a plurality of digital video signals are multiplexed in this way, the special code must be inserted during the blanking period. That is, as shown in FIG. 13C, even when two SDI signals SDI1 and SDI2 that are synchronized with each other are time-axis compressed and multiplexed, it is essential to insert a special code during a certain blanking period. It is a condition.

In the SDI signal shown in FIG. 13C,
By extracting only the video signal portion from the SDI signals SDI1 and SDI2 shown in FIGS. 13A and 13B and compressing the video signals so that both video signals are included in the video period having the same length as before compression, EAV and SAV are added to the blanking section. Strictly E
Audio and other information included in the SDI signal are also multiplexed in a narrow section sandwiched between AV and SAV.

The problem here is the synchronization relationship between the signals to be multiplexed. First of all, in the case of serial digital interface, a special code for synchronization recovery is originally inserted, and since the period during which this special code is inserted is not originally used for data transmission, it is also used for multiplexing. Although no problem occurs, in the case of an asynchronous analog VBS signal (a signal including a video signal, a burst signal and a sync signal) or the like, the prohibited period may overlap with the period of the important video signal. Therefore, it is said that it is necessary to satisfy the following two conditions in order to digitize the analog signal and allow the analog signal to be transmitted.

First, the first condition is that the input analog signal is at least horizontally synchronized with the digital signal to be transmitted, or at least the horizontal frequency is synchronized and the line memory is provided so that the phase can be synchronized. To do so. The second condition is that it is necessary to separate the composite signal into the component signals so that the color information can be transmitted even if the burst signal is blanked (since SAV comes in this phase). is there.

Therefore, in the camera system of FIG. 14 which is currently used, the return video signal (the video signal transmitted from the camera control unit (CCU) 2 to the camera head unit (CHU) 1) is the above-mentioned 2 signal.
The block configuration shown in FIGS. 15 and 16 is adopted to satisfy one of the conditions. First, the configuration of the CCU 2 will be described with reference to FIG. Of these, the circuit portion for satisfying the above condition 2 is the YC separation circuit 3. The YC separation circuit 3 converts the input analog VBS signal into a Y (luminance) signal and a C signal.
(Chroma) signal and then the C signal is separated into RY and BY color difference signals for output.

In order to separate the luminance signal and the chroma signal from the input VBS signal, a clock having a frequency of 4fs, which is four times that of the subcarrier signal, is required.
The NC / SC separation circuit 4 and the 4fs PLL circuit 5 generate such a clock. Incidentally, the SYNC / SC separation circuit 4 separates the SC (subcarrier) signal and the SYNC signal from the input analog VBS signal, and of these, the SC signal is given to the 4fs PLL circuit 5.
On the other hand, the SYNC signal is applied to the clock timing generation circuit 6 and is used to generate a line memory driving synchronization signal (write reset signal) provided for phase adjustment.

As described above, the YC separation circuit 3 and the SYNC /
In the SC separation circuit 4, the input VBS signal is separated into a Y signal, a color difference signal (RY signal, BY signal), a SYNC signal and an SC signal, and all the information necessary for the horizontal blanking interval is extracted. Therefore, there is no risk of information loss even if blanking is applied during the burst signal period. As a result, SAV and EAV can be added. This blanking process is also YC
This is performed in the separation circuit 3.

The Y signal, RY, separated in this way
The signal and the BY signal are supplied to the analog digital conversion circuits 7, 8 and 9, respectively. The analog digital conversion circuits 7, 8 and 9 respectively execute analog digital conversion processing based on the clock signal provided from the clock timing generation circuit 6. At this time, since the color difference signals (RY signal and BY signal) have a narrow signal band, sampling is performed at a clock of 6.75 [MHz], which is half the clock frequency of 13.5 [MHz] given to the processing system of the Y signal. To be done. Each analog digital conversion circuit 7, 8 and 9
Contains the prefilter required for sampling. Further, since the sampling rate of the color difference signals (RY signal and BY signal) at this stage is half the rate of the Y signal, it is raised to the same sampling rate as the Y signal when multiplexed in the switch 10.

Next, a circuit portion for satisfying the above condition 1 will be described. The line memories 11 and 12 correspond to this circuit. The line memories 11 and 12 have write timing signals (write reset signals) created based on the SYNC signal separated from the input VBS signal as described above.
The Y signal and the multiple color difference signal are written by, and the Y signal and the multiple color difference signal are read by the read timing signal (read reset signal) created based on the SYNC signal supplied from the system. In this way, the CCU 2 generates the component digital video signal whose horizontal sync phase is adjusted to the system while preserving the color information.

The Y signal and the color difference signal are multiplexed at the final stage switch 13 at a sampling rate of 27 [Mbps] and transmitted to the camera head unit (CHU) 1. CHU1 is configured as shown in FIG. C
HU1 has been transmitted from CCU2 via the transmission line 27
An analog VBS signal is generated by encoding a [Mbps] Y color-difference multiplexed digital signal by a digital encoding circuit 14 and digital-analog converting this with a digital-analog conversion circuit 15.

By the way, the camera system described above can be used when it is premised that the input VBS signal is frequency-synchronized with the horizontal synchronizing signal of the camera system, as shown in the condition 1 above. If this premise does not hold, that is, if it is necessary to assume that an asynchronous VBS signal is inserted, a special function called a frame synchronizer is required.

[0015]

However, in order to incorporate the frame synchronizer in the CCU2, a frame memory, a controller for providing the write / read timing of the frame memory, and a large hardware structure are required.
There was a problem that it was inevitable to increase the size of item 2. As described above, the asynchronous VBS signal is a signal that the camera system does not want to handle so much, but recently, it is highly necessary to positively use such a signal.

For example, a prompter signal is a good example. The prompter signal is a signal that is handled by a device that allows the speaker, such as the announcer or speaker, to read the manuscript while looking at the camera.Usually, the manuscript is taken with a camera other than the camera that shoots the talker. The generated image signal corresponds to this. The prompter signal is transmitted from the CCU to the camera, and is projected on a half mirror or the like located in front of the lens of the camera for photographing the talker.

As a camera which outputs a prompter signal, a camera which is not so high in performance is usually used. Moreover, such a camera often does not have a synchronization function, and even if the camera has a synchronization function, it is necessary to install one coaxial cable, and thus the synchronization function is often not used. Therefore, in many cases, the prompter signal is transmitted without the synchronization function.

Therefore, if it is attempted to transmit the prompter signal in synchronization with the system clock, a frame synchronizer is required.
Since the prompter signal to be transmitted is a video signal captured by a camera with a simple structure that does not have such high performance, it is not possible to incorporate a frame synchronizer that requires a large-scale structure just for this purpose. It is irrational. Further, even if a signal synchronized with the signal transmitted by the system is transmitted, it cannot be transmitted without passing through the complicated circuits shown in FIGS. 15 and 16, so that it is suitable for applications in which a very high image quality is not required. Was wasteful.

The above is the case of transmitting the component digital signal. However, when the transmission system is the composite digital signal, the TRS is arranged in the SYNC period, so that it is sufficient to satisfy the condition 1. However, the case of handling an asynchronous signal is exactly the same, and some improvement is desired.

The present invention has been made in consideration of the above points, and although the prompter signal and the return video signal can be easily handled in the analog transmission system, the synchronization is secured as described above in the digital transmission. Therefore, it is an object of the present invention to propose a digital transmission device and a digital camera system that can relatively easily digitally transmit even an asynchronous signal whose circuit has to be complicated.

[0021]

In order to solve such a problem, in the present invention, an analog signal asynchronous to the system is converted to an analog digital signal by an internal clock in the system, and then a non-synchronization code used for transmission in the system is not converted. During the transmission period, the digital data after the analog digital conversion is time-axis compressed and inserted. At this time, on the system side, regardless of the phase relationship between the analog signal to be transmitted and the synchronization signal on the system side, the timing signal on the system side converts the analog signal into digital data, compresses it on the time axis, and within a predetermined period. Since it is only necessary to insert the compressed data into, a simple circuit configuration is sufficient.

[0022]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

(1) Configuration of Digital Camera System (1-1) Overall Configuration FIG. 1 shows an example of a digital camera system. The digital camera system 21 is a system including a prompter device 22. As described above, the prompter device 22 is a device that enables a speaker such as an announcer or a speaker to always read a manuscript while looking at the camera, and is arranged between the camera head unit (CHU) 23 and the speaker 24. Has been done.

Here, the prompter device 22 includes a CHU 23.
On the optical axis of the optical system at 45 [°] with respect to the optical axis, and the monitor 22 at a position orthogonal to the optical axis of the optical system at the CHU 23.
B. Therefore, the image of the original document projected on the monitor 22B is projected on the half mirror 22A. As a result, the speaker 24 can talk intimately to the viewer while looking at the document displayed on the half mirror 22A.

The video image displayed on the monitor 22B is adapted to be input from the CCU 26 connected to the CHU 23 via the optical fiber cable 25.
Further, generally, a camera 27 for displaying an original on the monitor 22B is generally mounted on the head of a speaker 24 who is an announcer or a speaker, as shown in FIG.

(1-2) Camera head unit (CH
U) and camera control unit (CCU) configuration Next, the internal configurations of the CHU 23 and CCU 26 will be described with reference to FIG. Before proceeding to the description of the CHU 23 and the CCU 26, an example of the phase relationship between the video signal handled by the camera system and the asynchronous analog VBS signal will be described with reference to FIG. As shown in FIG. 3, the positions where the EAV and SAV of the SDI signal transmitted by the camera system are inserted and the phase of the horizontal blanking period (BLK) of the input signal of the asynchronous analog VBS signal are significantly deviated.

Since the input VBS signal is an asynchronous signal, this phase relationship gradually shifts. As can be seen from FIG. 3, there is important video information during the period when EAV and SAV are inserted. Therefore, even if the input VBS signal is simply analog-digital converted and then converted to a serial signal, it must be multiplexed with the SDI signal. I can't. Therefore, in the camera system of the present embodiment described in the following sections, the asynchronous VBS signal is sampled by the system clock as it is without YC separation, and the information is time-compressed to create a period in which EAV and SAV can be inserted. . First, an example of component digital transmission will be described.

(1-2-1) Structure of CCU As shown in FIG. 2, the CCU 26 includes a digital processing circuit 26A, a prompter signal compression circuit 26B, a transmission superposition / separation / TRS addition / detection circuit 26C, and a digital circuit. It is configured by the processing circuit 26D. The digital processing circuit 26A is a circuit for inputting an audio signal S _SA and a return video signal S _SR to be transmitted to the CHU 23 side and processing a digital signal.
Output to the TRS addition / detection circuit 26C.

The prompter signal compression circuit 26B is a circuit portion newly proposed this time, and is constructed as shown in FIG. That is, the prompter signal compression circuit 26B includes an analog digital conversion circuit 26B1, a time axis compression circuit 26B2, and a clock timing generation circuit 26B3. This prompter signal compression circuit 26B is
In the analog digital conversion circuit 26B1, input V
The BS signal is not YC-separated, but is directly converted to analog digital by the 13.5 [MHz] component sampling clock.

The time axis compression circuit 26B2 is 1 at 27 [MHz].
It has a memory for the horizontal period, and the memory has 13.5 [MHz]
While the data is written at, the data is compressed in the time direction by reading at 27 [MHz]. Since the clock timing generation circuit 26B3 gives the read timing so that the data reading is started immediately after the SAV, the information to be transmitted is arranged in the video period as shown in FIG. ing.

However, the clock timing generation circuit 26B
3 outputs at a timing delayed to some extent so that the writing timing does not collide with the reading timing. Incidentally, the clock timing generating circuit 26B3 generates these various clocks and timing signals from the system clock of 27 [MHz] and SYNC. In this way, an asynchronous analog signal having a synchronization phase completely independent of the camera system is converted into a digital video signal synchronized with the system.

Transmission superposition / separation / TRS addition / detection circuit 2
The circuit block configuration of the 6C transmission system is shown in FIG. The transmission superimposition / separation / TRS addition / detection circuit 26C inputs the prompter signal S _SP converted into a digital video signal synchronized with the system clock in the prompter signal compression circuit 26B at 27 [Mbps] during transmission. Transmission superposition /
The separation / TRS addition / detection circuit 26C inputs the digital transmission signal S _SD from the digital processing circuit 26A in the same format. Note that the two signals input at this time, that is, the prompter signal S _SP and the digital transmission signal S _SD are already in phase with each other as shown in FIGS. 7A and 7B.

Transmission superposition / separation / TRS addition / detection circuit 2
The 6C performs parallel-serial conversion on the prompter signal S _SP , the digital transmission signal S _SD, and the high-speed clock, at the same time time-division-multiplexes both signals, and further synchronizes the necessary synchronization signal (T
The RS signal) is added as shown in FIG. 7C and output to the optical fiber cable 25. On the other hand, at the time of reception, the transmission superimposition / separation / TRS addition / detection circuit 26C detects the TRS signal from the signal received via the optical fiber cable 25, separates the multiplexed signal portion, and outputs it to the digital processing circuit 26D. give. The digital processing circuit 26D digitally processes the received signal and outputs the processed result to the video signal S.
Output as _RV and audio signal S _RA . The above is CCU
26 is a device configuration and an operation content of each unit that configures 26.

(1-2-2) Structure of CHU On the other hand, as shown in FIG. 2, the CHU 23 includes a video signal processing circuit 23A, a digital processing circuit 23B, a transmission superposition / separation / TRS addition / detection circuit 23C. , A prompter signal expansion circuit 23D and a digital processing circuit 23E. Here, the video signal processing circuit 23
A is a circuit that performs signal processing on a video signal of a subject image captured by the CHU 23.

The digital processing circuit 23B is a circuit that superimposes the video signal S _SV and the audio signal S _SA input from the video signal processing circuit 23A, and transmits the superposed signal by transmission superposition / separation / TRS addition / detection circuit. 23C. The transmission superposition / separation / TRS addition / detection circuit 23C includes a transmission circuit section and a reception circuit section. Of these, the circuit part of the transmission system outputs the signal imaged by the CHU 23 to the CCU 2 via the optical fiber cable 25.
It is designed to be sent to No. 6. On the other hand, the circuit unit of the receiving system detects the synchronization signal (TRS signal) from the signal received from the CCU 26 via the optical fiber cable 25,
The multiplex signal is separated into the return video signal and the prompter signal based on the synchronization signal.

As shown in FIG. 8, the prompter signal expansion circuit 23D is composed of a time axis expansion circuit 23D1, a digital analog conversion circuit 23D2 and a clock timing generation circuit 23D3. Here, the time axis expansion circuit 2
3D1 is transmission superposition / separation / TRS addition / detection circuit 23C
, The prompter signal separated in, ie compressed VB
Input S signal and expand. This time axis expansion circuit 23D
1 has a built-in memory for one horizontal period, and while writing data to the memory at a bit rate of 27 [MHz], while reading data at a bit rate of 13.5 [MHz], the compressed time axis is the original Returning to the time axis.

FIG. 9 shows this state. By this decoding operation, it can be seen that the prompter signal asynchronous with the camera system could be transmitted without loss of information. At this time, if the timing of the write reset signal that gives the write timing and the timing of the read reset signal that gives the read timing are improper, the received prompter signal cannot be read correctly, so that the clock timing generation circuit 23D3 applies the timing. Is managing.

The digital analog conversion circuit 23D2 is
This is a circuit for converting a 13.5 [MHz] bit rate digital signal with an expanded time axis into an analog signal and outputting it. The converted VBS signal is output to the monitor 22B of the prompter device 22. . On the other hand, the digital processing circuit 23E has a transmission superposition / separation /
The TRS adding / detecting circuit 23C is a circuit for separating the return video signal and audio signal parts separated by another circuit, and the return video signal S _RV is output to the view finder 23F.

(1-2-3) In the case of composite transmission system Next, an example of composite digital transmission will be described. Since the composite digital transmission does not have a wider area than the component digital transmission, the method described below is adopted. This will be described with reference to FIG. In the case of this example, the prompter compression circuit 26B on the CCU 26 side is replaced with the analog digital conversion circuit 26B11 and the line memory 26.
B12, and data compression is realized by changing the bit width for writing and reading in the line memory 26B12.

That is, the prompter compression circuit 26B writes digital data to the line memory 26B12 at 8 bits and reads digital data at 10 bits. However, the clock with the same frequency is used as the write clock and the read clock. A method of reading / writing digital data from / to the line memory 26B12 is shown in FIGS.

In this way, only the bit width is changed between the time of writing and the time of reading in the line memory 26B12, and the 8-bit digital data is rearranged into the 10-bit digital data, thereby making a vacant time of about 20%. be able to. By controlling the write timing and the read timing so that this phase is matched with the digital synchronization signal, it is possible to transmit an asynchronous signal as shown in FIG. This method can also be used when two asynchronous signals are multiplexed on the line of component digital transmission.

(1-2-4) Effects of the Embodiment As described above, in the camera system which digitally transmits a plurality of digital data which are synchronized with each other between the CCU 26 and the CHU 23, the VBS signal which is asynchronous to the system, that is, When the prompter signal is transmitted from the CCU 26 to the CHU 23, the prompter signal is transmitted to the CC
After the analog digital conversion by the internal clock of U26, the time axis is compressed and the compressed digital signal is transmitted while avoiding the transmission period of the code used for system synchronization.

At this time, the CCU 26 can be constituted only by an analog digital conversion circuit necessary for converting an analog signal into a digital signal and a memory for one line necessary for time-axis compression of the digital data after the analog digital conversion. Further, the management of the data write timing signal and the data read timing signal with respect to the memory can also be determined from the horizontal synchronization phase of the camera system, so that the configuration of the camera system can be made inexpensive and compact.

In the conventional case, since the frame synchronizer is used, from the input analog signal to the synchronizing signal, Y
Since it is necessary to incorporate a circuit and a frame memory for separating the signal and the C signal into the device, it is unavoidable that the circuit configuration becomes large. On the other hand, in the case of the present embodiment, these circuits are not necessary or can be replaced with a simpler structure, so that the circuit structure is relatively simple.

That is, it is possible to realize a digital camera system having a simple structure and capable of multiplexing and transmitting an asynchronous VDS signal with digital data in the system. On the other hand, the configuration on the receiving side need only be provided with a circuit that expands the time axis of the compressed digital data to expand the original data and a digital-analog conversion circuit that converts the digital data into an analog signal.
Since it is not necessary to provide a large-scale circuit such as a digital encoder as in the conventional case, the circuit configuration can be downsized.

(2) Other Embodiments In the above embodiment, the prompter signal is sent to the CCU.
However, the present invention is not limited to this, and when the video signal of another station demodulated from the broadcast wave is superimposed on the video signal of the local station and is transmitted from the CCU 26 to the CHU23 side. Can also be applied. Further, in the above-described embodiment, the case where the VBS signal (that is, the signal including the video signal, the burst signal and the sync signal) is transmitted as the input analog signal that is asynchronous to the system has been described, but the present invention is not limited to this, and the analog signal is used. If it is a signal, the signal form is not limited to this.

Further, in the above embodiment, CCU2
Although the case where the signal asynchronous with the system is digitally transmitted from the 6 side to the CHU 23 side has been described, the present invention is not limited to this, and the reproduced signal of the video tape recorder operating independently of the system is the CHU 23 side. To CC
It can also be applied when transmitting to the U26 side. Further, in the above-described embodiment, the case where the digital data is digitally transmitted between the CCU 26 and the CHU 23 in the camera system composed of the CCU 26 and the CHU 23 has been described, but the present invention is not limited to this, and the synchronization state is established. The present invention can also be applied to the case where an asynchronous signal is externally input to an existing system and the asynchronous signal is digitally transmitted within the system.

[0048]

As described above, according to the present invention, an analog signal asynchronous to the system is analog-digital converted by an internal clock in the system, and then the analog code is transmitted during a non-transmission period of a synchronization code used for transmission in the system. By inserting the digital data after digital conversion by compressing it on the time axis, it is possible to realize a digital transmission device and a digital camera system with a small circuit configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing an example of a digital camera system according to the present invention.

FIG. 2 is a block diagram showing a circuit configuration of CCU and CHU.

FIG. 3 is a schematic diagram showing a phase relationship between an SDI signal and an asynchronous VBS signal.

FIG. 4 is a block diagram showing an example of a circuit configuration for time-axis compression of an asynchronous VBS signal.

FIG. 5 is a schematic diagram showing an example of a compression operation of an asynchronous VBS signal.

FIG. 6 is a block diagram showing a data input / output relationship in a transmission superposition / separation / TRS addition / detection circuit.

FIG. 7 is a schematic diagram showing the contents of digital data multiplexing processing executed in a transmission superposition / separation / TRS addition / detection circuit.

FIG. 8: Asynchronous VB separated from received transmission data
FIG. 6 is a block diagram showing an example of a circuit configuration for extending the S signal on the time axis.

FIG. 9 is a schematic diagram showing an example of expansion operation of an asynchronous VBS signal.

FIG. 10 is a schematic diagram showing an example of a time axis pressure operation when the asynchronous VBS signal is composite digital data.

11 is a schematic diagram showing an example of a writing / reading method used in FIG.

12 is a schematic diagram showing an example of a write / read method used in FIG.

FIG. 13 is a schematic diagram showing an example of multiplexing video signals synchronized with each other.

FIG. 14 is a block diagram showing an example of a system in which digital data is transmitted.

FIG. 15 is a block diagram showing a conventional example of a CCU that multiplexes VBS signals synchronized with a system.

FIG. 16: VB synchronized with the system from the received signal
It is a block diagram which shows the conventional example of CHU which demodulates an S signal.

[Explanation of symbols]

21 ... Digital camera system, 22 ... Prompter device, 22A ... Half mirror, 22B ... Monitor,
23 …… Camera Head Unit (CHU), 23A ……
Video signal processing circuit, 23B ... Digital processing circuit,
23C: Transmission superposition / separation / TRS addition / detection circuit, 2
3D ... prompter signal expansion circuit, 23D1 ... time axis expansion circuit, 23D2 ... digital analog conversion circuit,
23D3 ... Clock timing generation circuit, 23E ...
Digital processing circuit, 23F ... viewfinder, 2
4 …… Speaker, 25 …… Optical fiber cable, 26 ……
CCU, 26A ... Digital processing circuit, 26B ... Prompter signal compression circuit, 26B1 ... Analog digital conversion circuit, 26B2 ... Time axis compression circuit, 26B3 ...
... Clock timing generation circuit, 26B11 ... Analog digital conversion circuit, 26B12 ... Line memory,
26C: Transmission superposition / separation / TRS addition / detection circuit, 2
6C1 ... SAV, EAV addition circuit, 26D ... Digital processing circuit, 27 ... Camera.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location // H03M 7/30

Claims (8)

[Claims] 1. A digital transmission device for digitally transmitting information to another point connected via a transmission line, wherein an input analog signal having no synchronization relationship with a synchronization signal transmitted via the transmission line is used. An analog digital conversion means for performing analog digital conversion with an internal clock synchronized with the synchronization signal, and a digital signal output from the analog digital conversion means are time-axis compressed so as to be within the non-transmission period of the synchronization signal, and And a time axis compression means for inserting and outputting within the transmission period, and an output means for time-division multiplexing the synchronization signal with the compressed digital signal output from the time axis compression means and outputting the time-division multiplexed signal to the transmission path. Digital transmission device characterized by. 2. The digital transmission apparatus according to claim 1, wherein the time-axis compression means compresses the digital signal by reading the digital signal at a faster speed than when writing to the memory. 3. The time axis compression means compresses the digital signal by setting a bit width for reading larger than a bit width for writing to the memory. Digital transmission equipment. 4. A digital transmission device in which information is digitally transmitted from another point connected via a transmission line, a sync signal is detected from a reception signal received via the transmission line, and the reception signal is detected. Data separating means for separating the digital signal transmitted by time-axis compression from the digital signal separated by the data separating means on the time axis, and the expanded digital signal having no synchronous relationship with the synchronizing signal. And time-axis expansion means for expanding the digital signal to digital analog conversion of the expanded digital signal,
A digital transmission device comprising: a digital-to-analog conversion means for converting an analog signal having no synchronous relationship with the above-mentioned synchronization signal. 5. The digital transmission apparatus according to claim 4, wherein the time axis expansion means expands the digital signal by reading the digital signal at a slower speed than when writing it in the memory. 6. The time axis expansion means expands the digital signal by setting the bit width for reading to be smaller than the bit width for writing to the memory. Digital transmission equipment. 7. An analog digital converting means for analog-digital converting an input analog signal having no synchronous relationship with a synchronizing signal transmitted through a transmission line with an internal clock synchronized with the synchronizing signal, and the analog digital converting means. The output digital signal is time-axis-compressed so as to fit within the non-transmission period of the synchronizing signal, and is output from the time-axis compression unit that inserts and outputs the synchronization signal in the non-transmission period. A sending device having an output means for time-division-multiplexing a compressed digital signal with the synchronizing signal and outputting the multiplexed signal to the transmission path, and detecting a synchronizing signal from a reception signal received through the transmission path, Data separation means for separating the digital signal transmitted in time-axis compression and the digital separation means separated by the data separation means. Time-axis expanding means for expanding the digital signal on the time axis and expanding it to an expanded digital signal having no synchronous relationship with the synchronizing signal, and an analog signal having a digital analog conversion on the expanded digital signal and having no synchronous relationship with the synchronous signal. And a receiving device having a digital-to-analog converting means for converting into a digital transmitting device. 8. A digital camera system in which information is digitally transmitted on a transmission line connecting a digital video camera and a digital camera control unit, wherein the digital video camera and the digital camera control unit are respectively transmitted via the transmission line. The analog digital conversion means for analog-digital converting an analog video signal having no synchronization relationship with the sync signal transmitted by the internal clock synchronized with the sync signal, and the digital video signal output from the analog digital conversion means are synchronized with each other. The time axis compression is performed so that the signal is accommodated within the non-transmission period of the signal, and the time axis compression means for inserting and outputting within the non-transmission period, and the synchronization signal is added to the compression digital signal output from the time axis compression means. Time division multiplexed A sending device having an output means for outputting to the transmission line, and a sync signal is detected from a reception signal received through the transmission line, and a digital video signal transmitted from the reception signal after time-axis compression is transmitted. A data separating means for separating, a time axis expanding means for expanding the digital video signal separated by the data separating means on a time axis to an expanded digital signal having no synchronous relationship with the synchronizing signal, and the expanding digital signal. A digital camera system comprising: a receiver having digital-analog conversion means for converting a signal into a digital-analog and converting into an analog video signal having no synchronous relationship with the synchronization signal.