JPH1093986A - Television reception device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain stable output without a damage in a picture element even if color burst is not overlapped by setting the clock signal of a specified frequency, which is frequency-synchronized with a horizontal synchronizing signal contained in an NTSC signal, to be an operation clock when a color burst detection circuit cannot detect a color burst signal. SOLUTION: A burst detection device 119 is connected to the burst phase error detection circuit 104 of a first PLL circuit 117, detects whether color burst is overlapped with the inputted NTSC signal or not and transmits a detection signal to a clock switch circuit 120. When the color burst is overlapped the 4fSC(14.3MHz) clock synchronized with the color burst signal is supplied to a 14.3MHz clock supply node by the clock switch circuit 120. When they are not overlapped, a 910fH(14.3MHz) clock synchronized with the horizontal synchronizing signal (HD) is supplied.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

TECHNICAL FIELD The present invention relates to NTSC, PAL
The present invention relates to a television receiver that performs digital processing of signals and the like.

[0002]

2. Description of the Related Art In recent years, in television receivers for receiving NTSC, PAL signals, etc., NTSC, PAL
A receiving device in which a signal decoding unit and the like are processed by digital signals has been developed. In the future, it is expected that many television receivers that have performed digital signal processing will be developed because of their good compatibility with computer systems.

A conventional NTS will now be described with reference to the drawings.
A configuration of a television receiver that digitally processes a C signal will be described. A conventional digital television receiver is constituted by a circuit as shown in FIG.

[0004] First, an NTS to which an NTSC signal is input is provided.
An A / D conversion circuit 402 which is connected to the C input terminal 401, the NTSC input terminal, takes in a clock from a 4fSC (14.3 MHz) clock node, and outputs a digital signal sampled using the clock as a sampling frequency; Y / which outputs a frequency-multiplexed luminance signal (Y) and color signal (C) having a signal as an input
A C separation circuit 403, a color demodulation circuit 408 which receives the color signal (C) as an input and outputs a color difference signal (RY) and a color difference signal (BY), and is connected to the Y / C separation circuit 403; Luminance signal (Y ') obtained by delaying the luminance signal (Y).
And a digital signal processing unit 416 comprising a delay circuit 407 for outputting a signal.

[0005] Second, the digital signal processing unit 416
, A burst phase error detection circuit 404 having a color signal (C) output from the Y / C separation circuit 403 as an input, a low-pass filter 405 having an output signal of the burst phase error detection circuit 404 as an input, and the low-pass filter 4.
And an output signal 4fSC of the voltage-controlled oscillator 406 sent to a 4fSC (14.3 MHz) clock node.
Further, a first PLL circuit 417 fed back to the burst phase error detection circuit 404 and the low-pass filter 405.

Third, N is connected to the input terminal 401 and N
A synchronization circuit unit 411 that separates a vertical synchronization signal (VD) and a horizontal synchronization signal (HD) included in the TSC signal. 4th
A phase comparison circuit 412 having the horizontal synchronization signal (HD) as an input, a low-pass filter 413 having an output signal of the phase comparison circuit 412 as an input, and a voltage-controlled oscillator 414 having an output of the low-pass filter 413 as an input. And an output signal 910f of the voltage controlled oscillator 414.
H is sent to a 910fH (14.3 MHz) clock node, and 910fH is further divided by 910 and fed back to the phase comparison circuit 412.
L circuit section 418.

Fifth, two 14.3 MHz clock signals (4 fSC and 910 fH) are fetched, and the luminance signal (Y ') and the color difference signals (RY), (B- Y), and a clock transfer circuit 409 that outputs a signal synchronized with the 4fSC clock in synchronization with the 910fH clock.

[0008] Sixth, it is connected to the clock transfer circuit 409, and converts the luminance signal (Y ') and the color difference signals (RY) and (BY) from the RGB signals synchronized with the 910fH clock into RGB.
A matrix circuit 410 for generating a signal; The 4fSC (14.3 MHz) clock node is connected to the digital signal processing unit 416, and the 910fH (14.3MHz) clock node is connected to the matrix circuit 410.

The operation of the above-described television receiver will be described below. An input terminal 401 is an NTSC input terminal.
4fSC clock (14.3) in the / D conversion circuit 402
MHz), and is Y / C separated circuit 403
Is input to

The Y / C separation circuit 403 separates the frequency-multiplexed luminance signal (Y) and color signal (C). The separated luminance signal (Y) is input to the delay circuit 407, and the color signal (C) is input to the color demodulation circuit 408 and the first PLL circuit 417. The color demodulation circuit 408 demodulates and outputs a color difference signal (RY) and a color difference signal (BY) of the NTSC input signal. The delay circuit 407 outputs a luminance signal (Y ′) obtained by delaying the luminance signal (Y) by the same amount as that of the color demodulation circuit 408, and functions to adjust the input timing of the clock change circuit 409 at the subsequent stage.

In the first PLL circuit section 417, the burst phase error detection circuit 404 uses the color burst signal included in the color signal (C) and the 4 fSC clock (14.3 MHz).
To the 4fSC (14.3 MHz) clock node. This 4fSC clock is fed back to the burst phase error detection circuit 404 to form a PLL loop. Therefore, the 4fSC clock output from the voltage controlled oscillator 406 is PLL-locked to the color burst signal.

The 4f SC clock generated by the voltage controlled oscillator 406 is supplied to the A / D conversion circuit 402 and the Y / C separation circuit 40.
3, input to the delay circuit 407, the color demodulation circuit 408, and the clock transfer circuit 409. Therefore, the sampling frequency of the A / D conversion is the timing of the 4 fSC clock, and the luminance signal (Y ′), the color difference signals (RY), and (BY) output from the delay circuit 407 and the color demodulation circuit 408, respectively. Is PL for the color burst signal of the NTSC signal.
It is output in synchronization with the L-locked 4fSC clock.

On the other hand, a sync separation circuit 41 converts a horizontal sync signal (HD) and a vertical sync signal (VD) from an NTSC input signal.
Is output. In the second PLL circuit section 418, the phase comparison circuit 412 uses the horizontal synchronizing signal (HD) and 910fH
The phase difference from the 910 frequency division of the clock is detected. This phase difference signal is input to the voltage controlled oscillator 414 via the low pass filter 413, and the voltage controlled oscillator 410 using this as a control signal outputs a 910 fH clock (14.3 MHz) to a 910 fH (14.3 MHz) clock node. This 910fH is frequency-divided by 910 in a frequency divider 415 and fed back to the phase comparator 412, where
An L loop is formed. Therefore, 910fH output from the voltage controlled oscillator 414 is equal to the horizontal synchronizing signal (H
D) is PLL locked.

910f generated by voltage controlled oscillator 418
The H clock is input to the clock transfer circuit 409 and the matrix circuit 410. Clock transfer circuit 409
Converts the luminance signal (Y ') of the delay circuit 407 synchronized with the 4 fSC clock (14.3 MHz) and the color difference signals (RY) and (BY) of the color demodulation circuit 408 into a 910 fH clock (14.3 MHz). The synchronized luminance signal (Y ″), the color difference signals (RY) ′ of the color demodulation circuit 408 and (B−
Y) Change to the 'signal and output.

The luminance signal (Y ″), the color difference signals (RY) ′ and (BY) ′ of the clock transfer circuit 409
Are input to the matrix circuit 410 and converted into RGB signals. Since the 910 fH clock is also input to the matrix circuit 410 as an operation clock, the RGB signals output from the matrix circuit 410 are 910 fH PLL-locked to the NTSC horizontal synchronization signal (HD) signal.
It will be output in synchronization with the clock.

FIG. 5 shows an NTSC signal for one scanning line of a television screen. FIG. 5A illustrates a color television signal, and FIG. 5B illustrates a luminance signal component of FIG. As shown in FIG. 5A, a color television signal is obtained by adding a color signal component 50 to a luminance signal.
2 is frequency superimposed. The phase of the NTSC signal is
It is represented by the phase difference of the color signal 502 with respect to the 3.58 MHz color burst signal 501, and the saturation is represented by its amplitude. Therefore, when performing digital processing by A / D conversion of an NTSC signal, it is necessary to use a clock synchronized with a color burst signal included in the NTSC signal in order to accurately demodulate a color signal. When an image is reproduced from an RGB signal, it is necessary to use a clock synchronized with the horizontal synchronization signal 503 superimposed on the NTSC signal. For this reason, in the conventional television receiver shown in FIG. 4, in the process from A / D conversion to generation of a luminance signal and a color difference signal, a 4 fSC clock (14.3 MHz) PLL-locked to a color burst signal is used. The operating clock is used to calculate RGB from the luminance signal and the color difference signal.
In the process of generating a signal and reproducing an image, the 910 fH clock (1) PLL-locked to the horizontal synchronizing signal is used.
4.3 MHz) as the operating clock, 9
An RGB signal synchronized with the 10fH clock was obtained.

However, in the above configuration, the input NTS
If the color burst signal is not superimposed on the C signal, the color burst demodulation output becomes unstable and the 4fSC clock oscillation becomes unstable, and the 4fSC clock and 9
There is a problem that the 10fH clock becomes asynchronous.

FIG. 6 shows NT on which a burst signal is superimposed.
This is the A / D conversion output of the SC signal. Since the A / D conversion clock, that is, the 4fSC clock is locked to the color burst signal, the video signal for each scanning line has a stable horizontal phase for each line. Therefore, in the clock transfer circuit of FIG. 4, even if the luminance signal (Y ') and the color difference signals (RY) and (BY) synchronized with the input 4fSC clock are switched to the 910fH clock. , The image data is transmitted correctly.

FIG. 7 shows an A / D conversion output of an NTSC input signal on which no color burst signal is superimposed.
Since the color burst signal is not superimposed, the A / D conversion clock is free-running (self-running), and the video signal for one scanning line has an unstable horizontal phase for each line. Accordingly, in the clock transfer circuit of FIG. 4, when the luminance signal (Y ′) and the color difference signals (RY) and (BY) synchronized with the input 4 fSC clock are changed to the 910 fSC clock, If the image data is shifted with respect to the horizontal synchronizing signal HD and the sampling phase A / D is shifted by 4 fSC clock and the phase of 910 fH clock are shifted beyond the clock cycle, the pixel will be broken. There was a problem.

Also, when demodulating a PAL signal, the PAL signal modulates a color difference signal with a color burst signal. Therefore, in the absence of a color burst signal, there is a problem that a pixel is similarly broken. there were.

[0021]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a problem that a pixel is broken even when a color burst is not superimposed on an input NTSC signal (or PAL signal). It is an object of the present invention to provide a television receiving apparatus capable of obtaining a stable and stable output.

[0022]

According to the present invention, there is provided a color burst detection circuit for detecting a color burst signal, and when the color burst detection circuit cannot detect a color burst signal, a horizontal synchronization signal included in an NTSC signal is provided. An object of the present invention is to provide a television receiver characterized by using a 14.3 MHz clock signal (910 fH) frequency-synchronized with the signal HD as an operation clock. If the color burst signal is not superimposed on the NTSC signal (or PAL signal) input by the above configuration,
It operates only with a clock that is PLL-locked to the horizontal synchronizing signal (HD) and does not switch clocks, so that it is possible to obtain a stable output without causing any pixel breakdown.

[0023]

Embodiments of the present invention will be described below with reference to the drawings. The digital television receiver according to the present invention is constituted by a circuit as shown in FIG.

First, the NTS to which the NTSC signal is input
14.3M which is connected to a C input terminal 101 and the NTSC input terminal and is supplied from a first clock supply node (hereinafter referred to as a 14.3 MHz clock supply node).
A / D conversion circuit 102 for outputting a digital signal sampled at a sampling frequency of Hz, and Y / C separation for receiving the digital signal and outputting a frequency-multiplexed luminance signal (Y) and color signal (C) Circuit 103
And a color difference signal (RY) having the color signal (C) as an input.
And a color demodulation circuit 108 that outputs a color difference signal (BY).
A digital signal processor 11 connected to the Y / C separation circuit 103 and configured to output a luminance signal (Y ′) obtained by delaying the luminance signal (Y).
6.

Second, the digital signal processing unit 116
A burst phase error detection circuit 104 having a color signal (C) output from the Y / C separation circuit 103 as an input, a low-pass filter 105 having an output signal of the burst phase error detection circuit 104 as an input, and the low-pass filter 105
And a voltage-controlled oscillator 106 having an output signal of the voltage-controlled oscillator 106 as an input.
Clock supply node (hereinafter 4fSC (14.3MHz)
A first PLL circuit 117 for sending the clock signal to a clock node.

Third, connected to the input terminal 101,
A synchronization circuit section 111 for separating a vertical synchronization signal (VD) and a horizontal synchronization signal (HD) included in the NTSC signal; 4th
A phase comparison circuit 112 having the horizontal synchronization signal (HD) as an input, a low-pass filter 113 having an output signal of the phase comparison circuit 112 as an input, and a voltage-controlled oscillator 114 having an output of the low-pass filter 113 as an input. The output signal 910f of the voltage controlled oscillator 114
H is the third clock supply node (hereinafter 910fH (1
4.3 MHz) clock node).
Further, 910fH is frequency-divided by 910 and fed back to the phase comparison circuit 112 in the second PLL circuit section 118.

Fifth, a burst detection circuit 119 connected to the burst phase error detection circuit 104 of the first PLL circuit 117. Sixth, a clock switching circuit 120 connected to the burst detection circuit 119 and having the 4 fSC (14.3 MHz) clock node and the 910 fH (14.3 MHz) clock node as inputs and the 14.3 MHz clock supply node as output. .

Seventh, a clock signal supplied to the 14.3 MHz clock supply node and a 910 fH (14.3 MHz) clock node is taken in, and a luminance signal (Y ') output from the digital signal processing section 116 is obtained.
And chrominance signals (RY) and (BY) as inputs, and a signal synchronized with the clock supplied to the 14.3 MHz clock supply node is 910fH (14.3M).
Hz) A clock transfer circuit 109 which outputs in synchronization with a clock 910fH supplied to the node.

Eighth, a matrix circuit 110 which is connected to the clock transfer circuit 109 and generates an RGB signal from a luminance signal (Y ') and color difference signals (RY) and (BY) synchronized with 910fH.

The digital signal processing section 116 is connected to the 14.3 MHz clock supply node, and the matrix circuit 110 is connected to the 910 fH (14.3 MHz).
z) The clock node is connected.

The operation of the above television receiver will be described below. As is clear from FIG. 1, the present embodiment is different from the conventional digital television receiver shown in FIG. 4 in that the burst detection circuit 119 and the clock switching circuit 12
0 is added. Therefore, the description of the operation of the common circuit is omitted, and the circuit operation of the additional portion will be mainly described.

First, the burst detecting device 119 operates in the first
Phase error detection circuit 104 of PLL circuit 117 of FIG.
And detects whether a color burst is superimposed on the input NTSC signal, and sends a detection signal to the clock switching circuit 120. The clock switching circuit has an input / output terminal connected to a 4 fSC (14.3 MHz) clock node and a 910 fH (14.3 MHz) clock node, and connects one of the nodes to a 14.3 MHz clock supply node based on the detection signal. That is, the input NTS is applied to the 14.3 MHz clock supply node.
When a color burst signal is superimposed on the C signal, 4fSC (14.3 MHz) synchronized with the color burst signal
When a clock is supplied and not superimposed, 910 fH (14.3 MHz) synchronized with the horizontal synchronization signal (HD)
A clock will be supplied.

Since the digital signal processing section 116, the clock transfer circuit 109, and the first PLL circuit 117 are connected to the 14.3 MHz clock supply node, respectively, when the color burst signal is not superimposed on the input NTSC signal, Means that all the television receivers shown in FIG. 4 are synchronized with the horizontal synchronizing signal (HD) at 910fH (1
4.3 MHz) is used as the operation clock.

FIG. 3 shows an A / D conversion output of an NTSC input signal on which no color burst is superimposed, which is obtained by the television receiving circuit of the present invention. Since the operation clock of the A / D conversion is a clock synchronized with the horizontal synchronizing signal (HD), even if the color burst is not superimposed, the video signal for each scanning line has a stable horizontal phase for each line. In this case, in the clock transfer circuit 109,
Since the clock is not changed, the image data is transmitted correctly.

The same effect can be obtained even when the burst detection signal is directly input to the clock switching circuit 117 as an external input signal. further,
A similar effect can be obtained even when the color burst detection signal is directly input to the clock switching circuit 117 as an external input signal.

Further, in the present embodiment, the operation clock has been described as 14.3 MHz, but the same effects as those of the present invention can be obtained by using a clock which is a multiple of the color burst signal.

[0037]

As described above, according to the present invention, NTS
When a color signal is not superimposed on an input signal when digitally decoding a television signal such as a C or PAL signal, a video output in which all processing is stable can be obtained.

Also, when demodulating a PAL signal, since the PAL signal modulates a color difference signal with a color burst, if there is no color burst, all pixels do not break down as in the NTSC signal processing. A stable video output can be obtained.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a television receiver according to the present invention.

FIG. 2 is a diagram showing an A / D conversion output of an NTSC signal for one scanning line in the television receiver of the present invention.

FIG. 3 is a diagram illustrating a circuit configuration of a television receiver according to the present invention.

FIG. 4 is a diagram showing a circuit configuration of a conventional television receiver.

FIG. 5 is a diagram showing NTSC signals for one scanning line.

FIG. 6 shows A of an NTSC signal (color burst superimposed) for one scanning line in a conventional television receiver.
FIG. 6 is a diagram showing a / D conversion output.

FIG. 7 is a diagram illustrating an A / D conversion output of an NTSC signal for one scanning line (no color burst is superimposed) in a conventional television receiver.

[Explanation of symbols]

 116 Digital signal processing unit 117 First PLL circuit 118 Second PLL circuit 120 Clock switching circuit 316 Digital signal processing unit 317 First PLL circuit 318 Second PLL circuit Y Luminance signal C Color signal Y 'Delayed Luminance signal (RY) Color difference signal (BY) Color difference signal Y "Luminance signal after clock change (RY) 'Color difference signal after clock change (BY)' Color difference signal R after clock change G, B RGB signal

Claims (8)

[Claims] 1. A television receiver for performing digital processing of NTSC and PAL signals, comprising a color burst detection circuit for detecting a color burst signal, wherein the color burst detection circuit cannot detect a color burst signal. And a clock signal frequency-synchronized with a horizontal synchronization signal included in the NTSC signal as a clock signal for digital processing. 2. When the color burst detection circuit can detect a color burst signal, a clock signal synchronized in frequency with the color burst signal is used as a clock signal for digital processing, and a clock synchronized in frequency with the horizontal synchronization signal is used. 2. The television receiver according to claim 1, wherein the signal is used as an operation clock signal for generating an RGB signal from a luminance signal and a color difference signal. 3. An input terminal to which an NTSC signal is applied, first to third clock supply nodes for supplying a clock signal to an arbitrary circuit, and an input terminal connected to the input terminal and connected to the first clock supply node. A / A that converts an input NTSC signal into a digital signal using the applied clock signal as an operation clock
A D / C conversion circuit, a Y / C separation circuit connected to the A / D conversion circuit and generating a luminance signal (Y) and a chrominance signal (C) from the NTSC signal converted into a digital signal; A color demodulation circuit connected to a C separation circuit for generating a color difference signal (RY) and a color difference signal (BY) from the color signal (C); and a color demodulation circuit connected to the Y / C separation circuit and A delay circuit for transmitting a luminance signal (Y ′) in which a signal (Y) is delayed by a processing time of the color demodulation circuit; a first circuit connected to the color demodulation circuit and the delay circuit;
The chrominance signals (RY), (RB) and the luminance signal (Y ') synchronized with the clock signal supplied by the third clock supply node to the clock signal supplied by the third clock supply node. Synchronous color difference signals (R-
Y) ′, (R−B) ′ and a luminance signal (Y ″) which are converted and outputted as a clock signal; and a clock signal which is connected to the clock transition circuit and is applied to the third clock supply node. As an operation clock, the input luminance signal (Y ″) and color difference signal (R−
Y) ′, a matrix circuit for generating R, G, B signals from (BY) ′, and a frequency lock to a color burst signal included in the color signal (C), which is connected to the Y / C separation circuit. A first PLL circuit for supplying the clock signal to the second clock supply node, and a synchronization separator connected to the input terminal for separating a vertical synchronization signal (VD) and a horizontal synchronization signal (HD) from the NTSC signal. A horizontal synchronizing signal (H
D) a second PLL circuit for supplying a clock signal frequency-locked to D) to the third clock supply node; and supplying the first clock supply node with either the second clock supply node or the third clock supply. A switching circuit for switching between nodes to connect the first clock supply node and the second clock supply node when a color burst signal is superimposed on an input NTSC signal. And connect
A television receiving circuit that connects the first clock supply node and the third clock supply node when they are not superimposed; 4. A burst detection circuit for detecting a color burst signal superimposed on an NTSC signal, wherein the switching circuit controls connection based on an output signal of the burst detection circuit. The television receiver according to claim 3. 5. The television receiver according to claim 4, wherein said burst detection circuit is connected to an input terminal and detects a color burst signal from an NTSC signal. 6. The burst detection circuit is connected to an output of an A / D conversion circuit, and converts the digital signal into a NTS signal.
The television receiver according to claim 4, wherein a color burst signal is detected from the C signal. 7. The first PLL circuit has the color signal (C) output from the Y / C separation circuit as an input, and
A burst phase error detection circuit for detecting a phase difference between a color burst signal included in the color signal (C) and a clock signal applied to the first clock supply node; A voltage-controlled oscillator that controls the oscillation frequency based on the phase difference signal, and always sends a clock signal PLL-locked to a frequency that is a multiple of the color burst signal to the second clock supply node. 5. The television receiver according to claim 4, wherein the detection circuit receives an output signal of the burst phase error detection circuit as an input. 8. The television receiver according to claim 1, wherein a PAL signal is used instead of the NTSC signal.