JPH10224041A - Multilayer wiring board and its manufacturing method - Google Patents

Multilayer wiring board and its manufacturing method

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Publication number
JPH10224041A
JPH10224041A JP3138297A JP3138297A JPH10224041A JP H10224041 A JPH10224041 A JP H10224041A JP 3138297 A JP3138297 A JP 3138297A JP 3138297 A JP3138297 A JP 3138297A JP H10224041 A JPH10224041 A JP H10224041A
Authority
JP
Japan
Prior art keywords
layer
hole
wiring board
multilayer wiring
manufacturing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3138297A
Other languages
Japanese (ja)
Inventor
Masaki Uemae
昌己 上前
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Nippon Carbide Industries Co Inc
Original Assignee
Nippon Carbide Industries Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Carbide Industries Co Inc filed Critical Nippon Carbide Industries Co Inc
Priority to JP3138297A priority Critical patent/JPH10224041A/en
Publication of JPH10224041A publication Critical patent/JPH10224041A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

PROBLEM TO BE SOLVED: To eliminate the need for separately forming a via hole on an inner- layer circuit board and to reduce the number of manufacturing processes and cost by electrically connecting an inner-layer conductor layer and an outer-layer conductor layer and then breaking the electrical connection with the outer-layer conductor layer, and forming 11 via hole for electrically connecting the inner- layer conductor layers. SOLUTION: For manufacturing a multilayer wiring board, a plurality of inner-layer conductor layers and outer-layer conductor layers are electrically connected via a hole, then the electrical connection with the outer-layer conductor layers is broken, and a via hole 10 for electrically connecting the inner-layer conductor layers is formed. More specifically, the conductor layer 1 and the insulator layer 2 are laminated, laser beams are applied to a desired position of a hole, and a hole is formed on the insulation layer 2. Then, a hole is electrically connected to the formed hole by a connection treatment and the electrical connection of a desired position with the outer-layer conductor layer being electrically connected via the hole is eliminated, thus forming the via hole 10 between the inner-layer conductor layers and hence reducing the number of manufacturing processes and hence cost.

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【産業上の利用分野】本発明は、多層配線板およびその
製造方法に関するものである。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multilayer wiring board and a method for manufacturing the same.

【0002】[0002]

【従来の技術】近年、電子機器の小型化に伴い、銅張り
の多層配線板の小型化、高密度化、軽量化などのために
多層配線板の導体幅、導体間隔、スルホール、ビアホー
ルなどの微細化、小径化などが求められている。これら
の要求のうちスルホール、ビアホールの小径化のため
に、従来のドリルによる孔加工にたいしてレーザーによ
る孔あけ方法が提案されている。例えば、特開昭58−
64097号公報である。
2. Description of the Related Art In recent years, with the miniaturization of electronic devices, the conductor width, conductor spacing, through holes, via holes, etc. of a multilayer wiring board have been developed in order to reduce the size, density, and weight of a copper-clad multilayer wiring board. Miniaturization and small diameter are required. In order to reduce the diameters of through holes and via holes, a method of drilling by laser has been proposed as compared with the conventional drilling. For example, JP-A-58-
64097.

【0003】該公報には、多層印刷回路板の電気的に接
続すべき導体層のうちの最下層より上の導体層に予め孔
を明けておき、上側から前記孔を孔あけのマスクとして
レーザを照射し、最上層から前記最下層までの導体層間
の樹脂層を除去することにより孔を明け、その後多層印
刷回路板の一般的技術によりスミア処理、銅メッキ、エ
ッチングなどによる製造方法が提案開示されている。
This publication discloses that a hole is previously formed in a conductive layer above a lowermost layer among conductive layers to be electrically connected on a multilayer printed circuit board, and a laser is used as a mask for forming the hole from above. Irradiation is performed to remove holes in the resin layer between the conductor layers from the uppermost layer to the lowermost layer, and then a manufacturing method is proposed by a general technique of a multilayer printed circuit board, such as smearing, copper plating, and etching. Have been.

【0004】[0004]

【発明が解決しようとする課題】上記のような従来の多
層配線板(多層印刷回路板、多層プリント板、多層印刷
配線板、PWB、PCBなどと呼ばれることがある。)
の孔あけ加工の方法では、予め導体層に孔あけを施す製
造工程が必要である。この導体層の孔あけ製造工程は、
ドリル、エッチングなどの方法によるが、ドリルによる
方法においては、孔あけ所望の導体層に孔あけが必要で
ある。エッチングによる方法においては、フォトレジス
トの塗布、露光、除去、導体層の除去などが孔あけ所望
の導体層毎に必要である。これらの様な導体層への孔あ
け製造工程は、多層配線板の層毎に行う必要がある。ま
たは、孔あけ所望の内層導体層の孔あけを配線パターン
と同時にエッチング方法により行うとしても外層導体層
への孔あけは別途行う必要がある。また、内層導体層間
の電気的接続(ブラインドビアホール)を行うためには
内層回路基板に孔をあける工程、該孔を介して電気的接
続する工程、回路パターン形成工程などにより製作され
た回路基板を積層してビアホールを形成することが必要
である。これらは製造工程の増加、製造コストの増加と
なるなどの問題点がある。
The conventional multilayer wiring board as described above (sometimes called a multilayer printed circuit board, a multilayer printed board, a multilayer printed wiring board, PWB, PCB, etc.).
The method of drilling requires a manufacturing step of drilling holes in the conductor layer in advance. The hole making process of this conductor layer
Depending on a method such as drilling and etching, a method using a drill requires a hole to be formed in a desired conductor layer. In the method by etching, application, exposure, removal of a photoresist, removal of a conductor layer, and the like are required for each of the desired conductor layers to be perforated. It is necessary to perform such a process of making a hole in the conductor layer for each layer of the multilayer wiring board. Alternatively, even if the desired inner conductor layer is formed by the etching method simultaneously with the wiring pattern, the outer conductor layer needs to be separately formed. Further, in order to make an electrical connection (blind via hole) between the inner conductor layers, a circuit board manufactured by a step of making a hole in the inner layer circuit board, a step of making an electrical connection through the hole, a circuit pattern forming step, and the like. It is necessary to form a via hole by stacking. These have problems such as an increase in manufacturing steps and an increase in manufacturing cost.

【0005】[0005]

【課題を解決するための手段】本発明は、複数の内層導
体層および外層導体層を孔を介して電気的接続して後
に、該外層導体層との電気的接続を絶ち、内層導体層間
を電気的接続するビアホールを形成することであり、内
層回路基板にビアホールを別途形成することがなく製造
工程が減少しコストダウンとなる多層配線板およびその
製造方法を提供することである。
SUMMARY OF THE INVENTION According to the present invention, a plurality of inner conductor layers and an outer conductor layer are electrically connected to each other through a hole, and thereafter, the electric connection with the outer conductor layer is cut off. It is an object of the present invention to provide a multilayer wiring board which forms a via hole for electrical connection, does not separately form a via hole in an inner circuit board, reduces the number of manufacturing steps, and reduces the cost, and a method for manufacturing the same.

【0006】以下、本発明に係る多層配線板の製造方法
について詳細を記述する。図1、図2(a)、(b)、
(c)、(d)は、本発明に係る多層配線板およびその
製造方法を示す一態様断面概略図である。
Hereinafter, a method for manufacturing a multilayer wiring board according to the present invention will be described in detail. 1 and 2 (a), (b),
1C and 1D are schematic cross-sectional views of one embodiment showing a multilayer wiring board according to the present invention and a method for manufacturing the multilayer wiring board.

【0007】本発明に係る多層配線板およびその製造方
法は、一般的に図1に示すごとく複数の内層導体層およ
び外層導体層を孔を介して電気的接続して後に、該外層
導体層との電気的接続を絶ち、内層導体層間を電気的接
続するビアホールを形成して成る。また、図1、図2に
示すごとく導体層1および絶縁体層2を積層する工程、
ホール(スルホール、ビアホールなど)の所望の位置に
レーザ3を照射して導体層、絶縁層に孔4を形成する工
程、形成された該孔4に接続処理により該導体層間を該
孔を介して電気的接続する工程、および該孔を介して電
気接続された外層導体層との所望位置の電気的接続を除
去して内層導体層間のビアホール10を形成する工程よ
り成る製造方法などである。
A multilayer wiring board and a method of manufacturing the same according to the present invention generally provide a method for electrically connecting a plurality of inner conductor layers and outer conductor layers through holes as shown in FIG. And via holes are formed to electrically connect the inner conductor layers. A step of laminating the conductor layer 1 and the insulator layer 2 as shown in FIGS.
A step of irradiating a desired position of a hole (a through hole, a via hole, etc.) with a laser 3 to form a hole 4 in the conductor layer and the insulating layer, and connecting the formed hole 4 to the conductor layer through the hole by a connection process. A manufacturing method including a step of electrically connecting and a step of forming a via hole 10 between the inner conductor layers by removing an electric connection at a desired position with the outer conductor layer electrically connected through the hole.

【0008】多層配線板の積層方法は一般的に行われて
いる多層配線板の積層方法で行えばよい。例えばサブト
ラクティブ方法、アディティブ方法などで所望回路パタ
ーンを形成した回路基板9および樹脂付金属箔7を位置
決め、積み重ね(図2(a))、真空中で加熱加圧によ
り密着積層する(図2(b))。
[0008] The method of laminating the multilayer wiring board may be performed by a generally performed method of laminating the multilayer wiring board. For example, the circuit board 9 on which the desired circuit pattern is formed by the subtractive method, the additive method, and the like, and the resin-attached metal foil 7 are positioned and stacked (FIG. 2A), and closely adhered and laminated by heating and pressing in a vacuum (FIG. b)).

【0009】導体層としての金属箔1としては特に限定
するものではないが銅、ステンレス、ニクロム、タング
ステン、アルミニウムなどが好ましい。さらに好ましく
は銅、ステンレスである。特に好ましくは銅であり圧延
銅箔、電解銅箔の方法で製造されたものが好ましく特に
電解銅箔は絶縁層樹脂との接着、密着性に優れている。
このような金属は電気伝導がよく、箔の形成が安易であ
りまた入手しやすい。該金属箔の厚みは特に限定するも
のではないが0.5〜50μmであることが好ましい。
さらに好ましくは1〜40μmである。特に好ましくは
3〜20μmである。このような厚みの金属は柔軟でレ
ーザ加工、食刻が安易である。
The metal foil 1 as the conductor layer is not particularly limited, but copper, stainless steel, nichrome, tungsten, aluminum and the like are preferable. More preferred are copper and stainless steel. Particularly preferred is copper, which is produced by a method of a rolled copper foil or an electrolytic copper foil, and the electrolytic copper foil is particularly excellent in adhesion and adhesion to an insulating layer resin.
Such a metal has good electric conductivity, is easy to form a foil, and is easily available. The thickness of the metal foil is not particularly limited, but is preferably 0.5 to 50 μm.
More preferably, it is 1 to 40 μm. Particularly preferably, it is 3 to 20 μm. A metal having such a thickness is flexible, and laser processing and etching are easy.

【0010】絶縁体層2としては特に限定するものでは
ないが好ましくはエポキシ、ポリイミド、ポリエステ
ル、フェノール、ポリフェニレンエーテル、ポリフェニ
レンオキシド、ビスマレイミド・トリアジン、シアネー
ト、フッ素、シリコン、ポリブタジエン、ポリサルホ
ン、ポリエーテルイミド、ポリエーテルスルホン、ユリ
ア、ポリカーボネート、ポリアリレートおよび/または
ポリエチレンを主成分とする樹脂である。さらに好まし
くは、エポキシ、ポリイミド、ポリエステル、フェノー
ル、ポリフェニレンエーテル、ポリフェニレンオキシド
および/またはビスマレイミド・トリアジンを主成分と
する樹脂である。
The insulating layer 2 is not particularly limited but is preferably epoxy, polyimide, polyester, phenol, polyphenylene ether, polyphenylene oxide, bismaleimide / triazine, cyanate, fluorine, silicon, polybutadiene, polysulfone, polyetherimide. , Polyethersulfone, urea, polycarbonate, polyarylate and / or polyethylene. More preferably, a resin containing epoxy, polyimide, polyester, phenol, polyphenylene ether, polyphenylene oxide and / or bismaleimide-triazine as a main component is used.

【0011】該絶縁体層2はガラス、アラミド、紙、多
孔質ポリテトラフルオロエチレンおよび/またはクォー
ツの織布および/または不織布に前記樹脂群を含侵させ
たものでもよい。好ましくは、ガラスおよび/またはア
ラミドの織布および/または不織布に前記樹脂群を含侵
させたものでもよい。
The insulating layer 2 may be made of glass, aramid, paper, porous polytetrafluoroethylene and / or quartz woven and / or non-woven fabric impregnated with the resin group. Preferably, a glass and / or aramid woven and / or nonwoven fabric impregnated with the resin group may be used.

【0012】該絶縁体層2は有機、無機の充填材が充填
されていてもよい。例えば樹脂ビーズ、アルミナ粉、酸
化チタン粉、炭酸カルシウム粉などである。
The insulator layer 2 may be filled with an organic or inorganic filler. For example, resin beads, alumina powder, titanium oxide powder, calcium carbonate powder, and the like.

【0013】また、レーザ加工所望の導体層のレーザ照
射側の少なくともレーザの照射点にレーザ吸収率を高め
る処理6を施すことが好ましい。さらに好ましくは、該
レーザ吸収率を高める処理の6サイズは孔あけ所望のサ
イズ以下である。このような処理を施すことによりより
低いエネルギーで該導体層を溶融し孔あけができるから
である(図2(c))。レーザ吸収率の高い処理として
は、レーザ感度の高い材料層の形成、レーザの波長域を
よく吸収する色に着色するなどがあげられる。感度の高
い材料としてはNiOX、CuOXまたは酸化銅、酸化
鉄、酸化コバルト、酸化モリブデン、酸化イリジウム、
酸化錫、酸化鉛、酸化アンチモンなどを主成分とする金
属酸化物などが好ましく、さらに好ましくはNiOX
CuOXであり、特に好ましくはCuOXの酸化膜を形成
することである。また着色としては、コンゴーレッド、
メチルバイオレットなどの染料またはカーボンなどの顔
料で被覆することである。好ましくは、カーボンなどの
顔料で茶色〜黒色に着色された材料で被覆することであ
る。
It is preferable to perform a process 6 for increasing the laser absorptivity at least at the laser irradiation point on the laser irradiation side of the conductor layer desired for laser processing. More preferably, the six sizes of the process for increasing the laser absorptance are not more than the desired size for drilling. This is because by performing such a treatment, the conductor layer can be melted and drilled with lower energy (FIG. 2C). Examples of the treatment having a high laser absorptivity include formation of a material layer having a high laser sensitivity and coloring to a color that absorbs the laser wavelength range well. NiO X is as sensitive materials, CuO X or copper oxide, iron oxide, cobalt oxide, molybdenum oxide, iridium oxide,
Metal oxides containing tin oxide, lead oxide, antimony oxide and the like as main components are preferable, and NiO x ,
CuO x , and particularly preferably, an oxide film of CuO x is formed. The coloring is Congo Red,
Coating with a dye such as methyl violet or a pigment such as carbon. Preferably, it is coated with a material colored brown to black with a pigment such as carbon.

【0014】孔4の形成においてはホール(スルホー
ル、ビアホールなど)の所望位置にレーザ3を照射する
ことにより導体層である金属箔および絶縁体層である絶
縁体を溶融、昇華させて孔を形成する。レーザの種類と
しては炭酸ガスレーザ、Xeレーザ、エキシマレーザ、
YAGレーザ、Arレーザなどが好ましい。さらに好ま
しくは炭酸ガスレーザ、YAGレーザである。特に好ま
しくは加工条件(パルス幅、パルス数、ピーク出力な
ど)を加工中に変更可能で高エネルギーである炭酸ガス
レーザで導体層、絶縁層を加工することである。
In forming the hole 4, a desired position of a hole (a through hole, a via hole, etc.) is irradiated with a laser 3 to melt and sublimate the metal foil as the conductor layer and the insulator as the insulator layer to form the hole. I do. Laser types include carbon dioxide laser, Xe laser, excimer laser,
YAG laser, Ar laser and the like are preferable. More preferred are a carbon dioxide gas laser and a YAG laser. It is particularly preferable to process the conductor layer and the insulating layer with a high energy carbon dioxide gas laser which can change the processing conditions (pulse width, pulse number, peak output, etc.) during the processing and has high energy.

【0015】孔4に接続処理による導体間の電気的接続
方法は一般的な方法で行えばよい。例えばエッチドバッ
ク処理を施してホール内のスミアリングを除去し無電解
メッキ、電解メッキ、導電性ペーストなどで該導体層間
を電気的接続する(図2(d))。
The electrical connection between the conductors in the hole 4 by the connection process may be made by a general method. For example, an etching back process is performed to remove smearing in the holes, and the conductive layers are electrically connected by electroless plating, electrolytic plating, conductive paste, or the like (FIG. 2D).

【0016】こののち外層の該導体層1を所望回路にな
るように、および所望位置のホールとの電気的接続除去
(ビアホール10の形成)するように導体層を取り省き
多層配線板を形成する(図1)。
Thereafter, the conductor layer is omitted so that the outer conductor layer 1 has a desired circuit and electrical connection with a hole at a desired position is removed (formation of a via hole 10) to form a multilayer wiring board. (FIG. 1).

【0017】このような多層配線板およびその製造方法
による多層配線板は製造工程が減少してコストダウンと
なりまた小径ホールの形成が可能であり小型化できる。
Such a multilayer wiring board and a multilayer wiring board manufactured by the method for manufacturing the same can reduce the number of manufacturing steps and reduce the cost, and can form a small-diameter hole and can be downsized.

【0018】[0018]

【実施例】以下、本発明に係る多層配線板およびその製
造方法の実施例を説明する。尚、本発明に係る多層配線
板およびその製造方法は以下の実施例に限られるもので
はない。
DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of a multilayer wiring board and a method of manufacturing the same according to the present invention will be described below. The multilayer wiring board and the method of manufacturing the same according to the present invention are not limited to the following embodiments.

【0019】(実施例1)先ず、ガラス繊維の不織布に
エポキシ樹脂を含浸した絶縁体層の両面に厚さ18μm
の銅箔をラミネートした銅張り両面板に、フォトエッチ
ング方法により回路パターンを形成した内層板(回路基
板9)に黒化処理を施し酸化銅を形成後、該酸化銅を金
属銅に化学的還元する処理を片面に施した。
(Example 1) First, an insulating layer obtained by impregnating a nonwoven fabric of glass fiber with an epoxy resin has a thickness of 18 μm on both surfaces.
An inner layer board (circuit board 9) having a circuit pattern formed by a photo-etching method on a copper-clad double-sided board laminated with a copper foil is blackened to form copper oxide, and the copper oxide is chemically reduced to metallic copper. Was performed on one side.

【0020】次に、樹脂付銅箔7(約50μmの半硬化
エポキシ樹脂含浸ガラス不織布に約12μmの銅箔を付
着)を用いて、該樹脂付銅箔、該内層版、該樹脂付銅箔
を位置合わせおよび重ね合わせを行い(図2(a))、
真空チャンバーの中において積層(圧力25Kg、温度
180度、120分)を行い積層板を作成した(図2
(b))。
Next, using a resin-coated copper foil 7 (approximately 12 μm of copper foil adhered to a glass nonwoven fabric impregnated with a semi-cured epoxy resin of approximately 50 μm), the resin-coated copper foil, the inner layer plate, and the resin-coated copper foil Are aligned and superimposed (FIG. 2A),
Lamination (pressure 25 kg, temperature 180 degrees, 120 minutes) was performed in a vacuum chamber to produce a laminated plate (FIG. 2).
(B)).

【0021】次に、該積層板の表面にレーザ吸収率を高
める処理6として所望ホール径より約20μm小さい円
形状の黒化処理を行った。(図2(b))。
Next, as a process 6 for increasing the laser absorptivity, a circular blackening process smaller than the desired hole diameter by about 20 μm was performed on the surface of the laminate. (FIG. 2 (b)).

【0022】次に、レーザ吸収率を高める処理をした該
積層板を炭酸ガスレーザ装置の加工テーブルに位置決め
セットし、ホールの所望位置にプログラムされたレーザ
を照射して、表面の該銅箔1に孔加工し、続けて硬化し
た該絶縁層2の樹脂およびガラス繊維を溶融、昇華させ
て該内層板9の銅箔に届く孔を形成した。また、別のホ
ール所望位置には表面の該銅箔、該絶縁体層、内層版の
銅箔および内層絶縁体に孔あけを行った。図2
(c))。
Next, the laminated plate subjected to the process of increasing the laser absorptivity is positioned and set on a processing table of a carbon dioxide gas laser apparatus, and a desired position of a hole is irradiated with a programmed laser beam to irradiate the copper foil 1 on the surface. The resin and the glass fiber of the insulating layer 2 which were subjected to the hole processing and subsequently cured were melted and sublimated to form holes reaching the copper foil of the inner layer plate 9. In another desired hole, holes were made in the copper foil, the insulator layer, the copper foil of the inner layer plate, and the inner layer insulator on the surface. FIG.
(C)).

【0023】次に、過マンガン酸カリウム法により孔の
内部のスミア処理を行い、無電解メッキ方法により該孔
の内壁、該内層板の銅箔および銅箔に銅を析出させ、続
いて電解メッキ方法により銅を析出させ、内層の銅箔と
表面の銅箔および内層銅箔間と表面の銅箔を電気接続す
るメッキ層5を形成した(図2(d))。
Next, the inside of the hole is smeared by a potassium permanganate method, and copper is deposited on the inner wall of the hole, the copper foil of the inner layer plate and the copper foil by an electroless plating method. Copper was deposited by the method to form a plating layer 5 for electrically connecting the inner layer copper foil to the surface copper foil and between the inner layer copper foil and the surface copper foil (FIG. 2 (d)).

【0024】次に、ホール内に樹脂を充填して孔埋め
し、フォトレジスト・ドライフィルムを表面に密着張り
付けし、表面の該銅箔をフォトエッチング方法により所
望の回路パターンにエッチングすると共に所望位置のホ
ールと表面の該銅箔の電気接続を無くすため銅をエッチ
ングにより除去してビアホール10を形成し、更にドラ
イフィルムおよび孔埋め樹脂を除去、ソルダレジストの
塗布、ソルダリングなどを行い多層配線板を作成した
(図1)。
Next, the hole is filled with resin to fill the hole, a photoresist dry film is adhered to the surface in close contact, the copper foil on the surface is etched into a desired circuit pattern by a photo-etching method, and a desired position is etched. In order to eliminate the electrical connection between the hole and the copper foil on the surface, the copper is removed by etching to form a via hole 10, and then the dry film and the filling resin are removed, solder resist is applied, soldering, etc., and the multilayer wiring board is formed. (FIG. 1).

【0025】このように作成された該多層配線板は、ホ
ールおよびビアホールの電気接続が確実であるばかりで
なく温度サイクルなどの環境テストにおいても十分な品
質であった。
The multilayer wiring board thus produced not only ensures the electrical connection of the holes and the via holes but also has a sufficient quality in an environmental test such as a temperature cycle.

【0026】[0026]

【発明の効果】本発明に係る多層配線板およびその製造
方法によれば、外層導体層との電気接続除去によるビア
ホールの形成、レーザ照射前に予め導体層に孔をあける
ことなく導体層および絶縁層(樹脂含浸繊維材の絶縁材
においても)に孔をあけることができるなどの製造工程
の省略となり簡略化、コストダウンとなる。
According to the multilayer wiring board and the method of manufacturing the same according to the present invention, a via hole is formed by removing electrical connection with an outer conductor layer, and the conductor layer and the insulating layer can be formed without making a hole in the conductor layer before laser irradiation. Manufacturing steps such as the ability to make holes in the layer (even in the case of resin-impregnated fibrous insulating material) are omitted, resulting in simplification and cost reduction.

【0027】[0027]

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明に係る多層配線基板およびその製造方法
の一実施態様を示す断面図である。
FIG. 1 is a cross-sectional view showing one embodiment of a multilayer wiring board and a method of manufacturing the same according to the present invention.

【図2】(a)、(b)、(c)および(d)は本発明
に係る多層配線板およびその製造方法の一実施態様を示
す断面図である。
FIGS. 2 (a), (b), (c) and (d) are cross-sectional views showing one embodiment of a multilayer wiring board and a method of manufacturing the same according to the present invention.

【0028】[0028]

【符号の説明】[Explanation of symbols]

1 導体層 2 絶縁体層 3 レーザ 4 孔 5 メッキ層 6 レーザ吸収率を高める処理 7 樹脂付銅箔 8 ホール 9 回路基板 10 ビアホール REFERENCE SIGNS LIST 1 conductor layer 2 insulator layer 3 laser 4 hole 5 plating layer 6 treatment to increase laser absorption 7 copper foil with resin 8 hole 9 circuit board 10 via hole

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 複数の内層導体層および外層導体層を孔
を介して電気的接続して後に、該外層導体層との電気的
接続を絶ち、内層導体層間を電気的接続するビアホール
を形成することを特徴とする多層配線板およびその製造
方法。
After a plurality of inner conductor layers and an outer conductor layer are electrically connected via holes, electrical connection with the outer conductor layers is cut off, and a via hole for electrically connecting the inner conductor layers is formed. A multilayer wiring board and a method of manufacturing the same.
【請求項2】 絶縁体層および導体層にホールを形成す
る多層配線板およびその製造方法において、複数の絶縁
体層および導体層を積層する工程と、レーザ照射により
該導体層および該絶縁体層に孔をあける工程と、該導体
層間を該孔を介して電気的接続する工程と、所望位置の
該孔を介して電気的接続された外層導体層との電気的接
続を除去して内層導体層間のビアホールを形成する工程
よりなることを特徴とする多層配線板の製造方法。
2. A multilayer wiring board in which holes are formed in an insulator layer and a conductor layer and a method for manufacturing the same, wherein a step of laminating a plurality of insulator layers and the conductor layer is performed, and the conductor layer and the insulator layer are irradiated by laser irradiation. Forming a hole in the conductor layer, electrically connecting the conductor layer through the hole, and removing the electric connection with the outer conductor layer electrically connected through the hole at a desired position to remove the inner layer conductor. A method for manufacturing a multilayer wiring board, comprising a step of forming a via hole between layers.
JP3138297A 1997-01-31 1997-01-31 Multilayer wiring board and its manufacturing method Pending JPH10224041A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3138297A JPH10224041A (en) 1997-01-31 1997-01-31 Multilayer wiring board and its manufacturing method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3138297A JPH10224041A (en) 1997-01-31 1997-01-31 Multilayer wiring board and its manufacturing method

Publications (1)

Publication Number Publication Date
JPH10224041A true JPH10224041A (en) 1998-08-21

Family

ID=12329713

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3138297A Pending JPH10224041A (en) 1997-01-31 1997-01-31 Multilayer wiring board and its manufacturing method

Country Status (1)

Country Link
JP (1) JPH10224041A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2003101244A (en) * 2001-09-27 2003-04-04 Ibiden Co Ltd Multilayer printed wiring board and method of manufacturing the same
JP2003136268A (en) * 2001-11-06 2003-05-14 Hitachi Via Mechanics Ltd Method for drilling printed board
US7525188B2 (en) 2005-06-07 2009-04-28 Sharp Kabushiki Kaisha Multilayer circuit board and production method for same
US7552531B2 (en) 1997-02-03 2009-06-30 Ibiden Co., Ltd. Method of manufacturing a printed wiring board having a previously formed opening hole in an innerlayer conductor circuit
JP2020508370A (en) * 2017-02-20 2020-03-19 クラリアント・プラスティクス・アンド・コーティングス・リミテッド Antimony-free composition for thermoplastic compounds for laser marking

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7552531B2 (en) 1997-02-03 2009-06-30 Ibiden Co., Ltd. Method of manufacturing a printed wiring board having a previously formed opening hole in an innerlayer conductor circuit
JP2003101244A (en) * 2001-09-27 2003-04-04 Ibiden Co Ltd Multilayer printed wiring board and method of manufacturing the same
JP2003136268A (en) * 2001-11-06 2003-05-14 Hitachi Via Mechanics Ltd Method for drilling printed board
US7525188B2 (en) 2005-06-07 2009-04-28 Sharp Kabushiki Kaisha Multilayer circuit board and production method for same
JP2020508370A (en) * 2017-02-20 2020-03-19 クラリアント・プラスティクス・アンド・コーティングス・リミテッド Antimony-free composition for thermoplastic compounds for laser marking
US11780255B2 (en) 2017-02-20 2023-10-10 Clariant Plastics & Coatings Ltd Antimony free composition for laser marking thermoplastic compounds

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