JPH1021135A - Method of optimizing bus cycle length of memory and control circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To optimize memory bus cycle length of a micro-CPU element and a memory element. SOLUTION: A register 3 previously set a number N, a counter 4 counts time by the number N and a clock cycle, the micro-CPU element 1 adopts the counting time of the counter as a waiting time, data to be written in the same address as that of the memory element 2 is collated with data to be read and one of substrate from the number N of the register 3 when the two kinds of data matched with each out. The counter 4 counts the time by the number (N-1) of the register and the clock cycle, the micro-CPU element 1 adopts the counted time as the waiting time again and data to be written in the same address as that of the memory element 2 is collated with data to be read. The operation is repeated till the two kinds of data are not matched with each other. When they are not matched, the number of the register 3 is adopted as (a). The counter 4 counts the time by the number (a+1) which is obtained by adding one to the number A of the register 3 and the clock cycle, the micro-CPU element 1 adopts the time (clock cycle × (a+1)) as the waiting time and data is read and write in the memory element 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a micro CPU.
The present invention relates to a method of optimizing a bus cycle length of a memory in which an element reads and writes data from and to a memory element, and a control circuit that optimally controls the bus cycle length of the memory.

[0002]

2. Description of the Related Art When a micro CPU device and an asynchronous memory device are connected and data is read from or written to the asynchronous memory device, the bus cycle length of the asynchronous memory device is determined by the access time of the asynchronous memory device and the signal timing of interface control. An acknowledgment signal defined by the bus cycle length is input to the micro CPU element to synchronize data read / write timing with the asynchronous memory element.

[0003]

The access time of the asynchronous memory device has a wide range in its specification, and the operating time of the device used in the circuit that generates this signal is also specified in the interface control timing signal. Depending on the width, a difference is made. Conventionally, in consideration of the above points, the bus cycle length is determined by the access time specification of the asynchronous memory element and the max value of the operation time specification of the element used for the circuit for generating the interface control timing signal.

Therefore, when the access time of the asynchronous memory device and the operation time of the device for generating the interface control timing signal are typ values, the bus cycle length determined by the conventional method causes a dead time. This dead time is a problem particularly in information processing apparatuses that require high-speed data processing.

[0005] Further, the memory access time differs depending on the connection scale of the memory (the load capacity of the bus), and depending on the circuit configuration, the memory access time may exceed the maximum value of the memory access time. The present invention has been made in view of the above points, and an object of the present invention is to propose a method of optimizing a bus cycle length for an asynchronous memory device, and to reduce a waste time and an accurate operation time margin by this method. It is an object of the present invention to provide a control circuit for realizing a bus cycle length.

[0006]

In order to achieve the above object, according to a first aspect of the present invention, a number N is determined,
The waiting time when the element outputs an address to the memory element and reads / writes data to / from the memory element is represented by clock cycle × N
The data to be written to the same address of the memory element and the data to be read are collated, and if these two data match, 1 is subtracted from the number N.

A wait time when the micro CPU element outputs an address to the memory element and the data is again read from and written to the memory element is defined as a clock cycle × (N−1), and data to be written to the same address of the memory element and data to be read are set. And if these two data match, 1 is further subtracted from the number (N-1). The above operation is repeated until these two data do not match, and the numerical value a of the number at which the two data do not match is stored.

[0008] The time when the micro CPU element waits for reading and writing data from and to the memory element is represented by clock cycle × (a
+1). In a second aspect, a control circuit according to the method for optimizing a bus cycle length of a memory according to the first aspect includes a register and a counter. The register sets a number N in advance, and the counter measures time (clock cycle × N) based on the number N and the clock cycle.

The micro CPU element uses the time counted by the counter (clock cycle × N) as a waiting time, compares data to be written to the same address of the memory element with data to be read, and if the two data match, the register 1 is subtracted from the number N set in. The counter measures time (clock cycle × (N−1)) based on the number of registers (N−1) and the clock cycle.

The micro CPU element again sets the time (clock cycle × (N-1)) counted by the counter as a waiting time, and compares data to be written to the same address of the memory element with data to be read. The above operation is repeated until the two data do not match. When the two data do not match, the number of registers is set to a.

The micro CPU element reads and writes data from and to the memory element using a time (clock cycle × (a + 1)) measured by the counter as a number (a + 1) in which 1 is added to the number a of the register and a clock cycle as a waiting time. It shall be.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a time chart illustrating a method for optimizing a bus cycle length of a memory according to the first invention. FIG. 1 is a time chart (FIG. 1) necessary for describing the present invention for a micro CPU element and a memory element.
Here, a case where data is read is illustrated).

In FIGS. 1A, 1B and 1C, the micro CPU element outputs an address signal to the memory element at the timing of the clock signal S1 to allow the memory element to output data. Outputs an enable signal. The memory element outputs data (denoted as DATA in FIG. 1) after the operation speed time (τ).

The number N is set in consideration of the maximum value of the access time of the memory element, and after the waiting time (clock cycle × N) based on the number N is completed, the data acknowledge signal (FIG. Then, * DACK) is input to the micro CPU element. The micro CPU element reads the data of the memory element at the timing of the clock signal S3 in response to the input of the data acknowledge signal.

FIG. 1A is a time chart in the case of the number N. Waiting time by number N (clock cycle x N)
Is completed, the data acknowledge signal is input to the micro CPU element, and at the falling edge point of the clock signal S3, the micro CPU element reads the data output from the memory element.
In the example shown in FIG. 1A, the memory element outputs data after the operation speed time (τ), and the micro CPU element can normally read the data of the memory element.

The number N is decremented by 1, and the waiting time is (clock cycle × (N-1)). At the falling edge point of the clock signal S3, the micro CPU reads data output from the memory. If the data output from the memory element can be read normally, the number (N-1) is further decremented by 1, and the micro CP
The U element repeats the above operation until the data output from the memory element cannot be read normally, and the number at this time is a.

FIG. 1B is a time chart for the case of the number a. Wait time by number a (clock cycle x a)
Is completed, the data acknowledge signal is input to the micro CPU element, and at the falling edge point of the clock signal S3, the micro CPU element reads the data output from the memory element.
As shown in FIG. 1B, the memory element has not yet output data because the operation speed time (τ) has not elapsed.

Therefore, the micro CPU element cannot read the data of the memory element. The number a is incremented by 1, and (a +
1). FIG. 1C shows a time chart in the case of the number (a + 1). The waiting time (clock cycle × (a + 1)) based on the number (a + 1) ends, the data acknowledge signal is input to the micro CPU element, and the clock signal S
At the falling edge point of 3, the micro CPU device reads the data output by the memory device.

As shown in FIG. 1C, at the end of the waiting time (clock cycle × (a + 1)), the memory element outputs data because the operation speed τ has elapsed. Therefore, the micro CPU device can normally read the data output from the memory device. The micro CPU element sets the waiting time to (clock cycle × (a + 1)), and reads and writes data in the memory element.

[0020]

FIG. 2 shows a configuration of an embodiment of a control circuit for optimizing a bus cycle length of a memory according to the second invention. The micro CPU element 1 is connected to the memory element 2 and the register 3 via a data bus.

The counter 4 stores the number N set in the register 3
And a clock cycle, a time (clock cycle × N) is measured, and a data acknowledge signal (* DAC in FIG. 2)
K), and this data acknowledge signal is connected to the micro CPU element 1. FIG. 3 shows a flowchart of the operation of the control circuit shown in FIG.

The operation of the control circuit will be described with reference to FIG. First, a number N (BCREG = N in FIG. 3) that defines the bus cycle length is set in the register 3. An address #A (x) of the memory 3 is designated, and arbitrary data X is written after a waiting time (clock cycle × N).

An address address @A (x) of the memory 3 is designated, and after the waiting time (clock cycle × N), the data X ′
Is read. If X = X ′, 1 is subtracted from the number N, the set value of the register 3 is set to N−1 (BCREG = N−1), and the above operation is repeated again. If X ≠ X ′, 1 is added to the set value a of the register 3 at this time, and the set value of the register 3 is set to a + 1 (BCREG = a + 1).
And write any data X after a waiting time (clock cycle × (a + 1)) time.

The address XA (x) of the memory 3 is designated, and the data X 'is read out after a waiting time (clock cycle × (a + 1)). If X = X ', the process ends.
If X ≠ X ′ (NG), return to the beginning or perform processing related to NG. When the micro CPU element 1 is an element (for example, MC68360 manufactured by Motorola, etc.) for which a waiting time (also called a wait cycle) can be set, the operation shown in FIG. 3 is executed without particularly including the register 3 and the counter 4. .

[0025]

According to the present invention, in a method of connecting a micro CPU element and a memory element and reading and writing data in the memory element, the number N is determined, the micro CPU element outputs an address to the memory element, The waiting time for reading / writing data from / to the element is set to the clock cycle × N, and data to be written to the same address of the memory element and data to be read are collated.

When these two data coincide, the number N is decremented by one, the waiting time for reading and writing data to the memory element is set to the clock cycle × (N-1), and the data to be written to the same address of the memory element again Check the data to be read. The above operation is repeated until the two data do not match. Numerical value a that makes two data inconsistent
Is stored.

The micro CPU element has a waiting time for reading and writing data from / to the memory element is calculated by multiplying a clock cycle × (a + 1).
Accordingly, data can be read from and written to the memory element by satisfying the operation time specification of the memory element and by using the fastest memory bus cycle length. Furthermore,
By adding the above operation to the initial operation processing (also called initial processing) of the control circuit at the time of turning on the power supply, even when replacing the memory element or improving the memory element,
The micro CPU device can always read and write data from and to the memory device by always satisfying the operation time specifications of the memory device and by the fastest memory bus cycle length.

[Brief description of the drawings]

FIG. 1 is a time chart illustrating a method for optimizing a bus cycle length of a memory according to a first invention.

FIG. 2 is a block diagram of an embodiment of a control circuit for optimizing a bus cycle length of a memory according to the second invention;

FIG. 3 is a flowchart showing the operation of a control circuit for optimizing a bus cycle length of a memory according to the second invention;

[Explanation of symbols]

 1 Micro CPU element 2 Memory element 3 Register 4 Counter

Claims (2)

[Claims] In a method of connecting a micro CPU element and a memory element and reading and writing data in the memory element, a number N is determined, the micro CPU element outputs an address to the memory element,
The waiting time for reading / writing data to / from the memory element is assumed to be clock cycle × N, the data to be written to the same address of the memory element and the data to be read are collated, and if these two data match, the number N is decremented by one. The waiting time for reading / writing data from / to the element is defined as clock cycle × (N−1), and the data to be written to the same address of the memory element and the data to be read are compared again. The above operation is repeated until the two data do not match. And a waiting time for the micro CPU element to read / write data from / to the memory element is defined as clock cycle × (a + 1). Cycle length optimization method. 2. A bus cycle length control circuit for a memory of an information processing apparatus which includes at least a micro CPU element and a memory element, reads and writes data in the memory element, and performs information processing, includes a register and a counter. The register sets a number N in advance, and the counter measures time (clock period × N) based on the number N and the clock cycle. The method according to claim 1, further comprising: The CPU element uses the time counted by the counter (clock cycle × N) as a waiting time, compares data to be written to the same address of the memory element with data to be read, and if the two data match, the number of registers N The counter counts the time (clock cycle × (N−1)) based on the number of registers (N−1) and the clock cycle. The micro CPU element sets the time counted by the counter (clock cycle × (N-1)) as a waiting time, compares the data to be written to the same address of the memory element with the data to be read again, and compares the two data. The above operation is repeated until the data does not match, and the number of registers when the two data do not match is a.
A circuit for optimizing the bus cycle length of a memory, wherein a time (clock cycle × (a + 1)) measured by a number (a + 1) to be incremented by 1 and a clock cycle is set as a waiting time, and data is read / written from / to a memory element.