JPH10197608A - Semiconductor circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To shorten the time required for testing I/O blocks included in a semiconductor circuit and to decrease the number of pins for judging output results. SOLUTION: A test select circuit 10 outputs block select signals to all I/O blocks 2-1,..., 2-N upon receiving a test signal 'H' on a test signal line 11. The I/O blocks 2-1,..., 2-N being fed through block select signal lines 4-1,..., 4-N takes in a same input signal from an input bus 6 in synchronism with an operation clock and place the results on output buses 7-1,..., 7-N. Outputs from the output buses 7-1,..., 7-N are fed to a comparing/matching circuit 13 and comparison results of output signals from the I/O blocks 2-1,..., 2-N are obtained from the comparison results output terminal 14. Test results can be judged based on the comparison results and the output signal from one I/O block without confirming the output signals from all I/O blocks 2-1,..., 2-N.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor circuit including a plurality of I / O blocks having the same function.

[0002]

2. Description of the Related Art Normally, tests of I / O blocks included in a semiconductor circuit are performed individually for each I / O block. Conventional I / Os having the same function
The semiconductor circuit including the O block is configured as shown in the circuit diagram of FIG. In FIG. 5, 1 is a block selection circuit, 2-1 to 2-N are N I / O blocks having the same function, 3 is a block designation signal line of a block designation signal input to the block selection circuit 1, -1 to 4-N are block selection signal lines of a block selection signal output from the block selection circuit 1, 5 is a clock signal line of an operation clock input to each I / O block 2-1 to 2-N, 6 Is the input bus, 7-1 ~
7-N is an output bus. The block selection signal is the only I / O block 2-1 to 2-2 corresponding to the block designation signal.
It is supplied as a selection signal only to -N.

The operation of the semiconductor circuit configured as described above will be described. When a block designating signal is input from the block designating signal line 3, the block selecting circuit 1 selects from the corresponding I / O blocks 2-1 to 2-N,
The block selection signal is supplied to the I / O blocks 2-1 to 2-N. The I / O blocks 2-1 to 2-N supplied with the block selection signal take in the input signal input from the input bus 6 in synchronization with the operation clock signal, and output the output result to the output bus 7-1 to 2-N. Output as an output signal from 7-N. Here, the output signal line of one I / O block 2-1 to 2-N is n
Assuming that there are books, all I / O blocks 2-1 to 2
The number of output signal lines that need to be checked to test -N is nx
There are N books.

FIG. 6 is a diagram showing a time chart of each signal in a test of a conventional semiconductor circuit. In FIG. 6, the horizontal axis indicates time, and the vertical axis indicates input and output signals. Here, the description will be given with reference to FIG. 5 on the assumption that the test required time of one I / O block takes T time. First, the I / O block 2-1 is selected by the block selection signal of the block selection signal line 4-1 and an input signal is input from the input bus 6 in synchronization with the operation clock signal.
-1 and the test of the I / O block 2-1 ends after T time. Next, when the test of the I / O block 2-1 is completed, the I / O block 2-2 is selected by the block selection signal of the block selection signal line 4-2, and the I / O block is synchronized with the operation clock signal. The same input signal as that input to 2-1 is input to I / O block 2-1 and the test ends after 2T time.

[0005]

However, since the semiconductor circuit thus configured has N I / O blocks having the same function, the test of each I / O block is performed by selecting the block. The same input signal is input to the I / O block selected by the circuit, and it is confirmed that the output signal from the I / O block is the same for every I / O block. In such a method, the same test needs to be repeated N times, which is the number of N I / O blocks included in the semiconductor circuit, so that the required test time increases to N × T times. .

Since the output signal is output for each I / O block, the I / O block connects the output signal line to n.
In the case where the number of output signal lines is provided, there is a problem that the number of pins for confirming the output result increases to n × N of the number of output signal lines.

SUMMARY OF THE INVENTION The present invention is directed to solving the above-mentioned problems in the prior art, and reduces the time required for testing an I / O block included in a semiconductor circuit and the number of pins for judging an output result. It is an object of the present invention to provide a semiconductor circuit for reducing the number of semiconductor devices.

[0008]

In order to achieve this object, a semiconductor circuit according to the present invention comprises a plurality of I / O blocks having the same function and an I / O block selected by inputting a block designating signal. A semiconductor circuit having a block selection circuit for supplying a block selection signal only to a block, comprising a test selection circuit for supplying a block selection signal to all I / O blocks in response to a test signal input. I do.

Further, the semiconductor circuit is provided with a comparison matching circuit for performing a comparison determination as to whether or not all the output signals from the I / O blocks match, in synchronization with a clock signal.

According to the present invention, when a test signal is input by the semiconductor circuit having the above configuration, the test selection circuit supplies a block selection signal to all the I / O blocks, whereby the output signal from the I / O block is output. At the same time, and a plurality of I / O blocks having the same function can be tested at the same time.

[0011] In addition, with respect to the output signal of the I / O block to which the block selection signal has been supplied, whether or not one I / O block and all the remaining output signals match is determined by a comparison matching circuit. The test can be determined by the output signal of one I / O block and the output of the comparison matching circuit.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a diagram showing a circuit configuration of a semiconductor circuit according to the first embodiment of the present invention. Here, components having substantially the same functions as the components described in FIG. 5 showing the conventional example and having substantially the same functions are denoted by the same reference numerals, and the same applies to the following drawings. In FIG. 1, reference numeral 1 denotes a block selection circuit, and 2-1 to 2-N
Is an I / O block, 3 is a block designation signal line, and 4-1 to 4
-N is a block selection signal line, 5 is a clock signal line, 6 is an input bus, 7-1 to 7-N are output buses, and 10 is a block selection circuit 1 and I / O blocks 2-1 to 2-N. A test selection circuit provided between the block selection signal lines 4-1 to 4-N
Denotes a test signal line for a test signal input to the test selection circuit 10, and 12-1 to 12-N denote OR gates constituting the inside of the test selection circuit 10. The test signal on the test signal line 11 is a signal that is “H” during a test and “L” during a normal operation.

The operation of the circuit configured as described above will be described. When a block specifying signal is input, the corresponding I / O blocks 2-1 to 2-N are selected by the block selecting circuit 1, and the block selecting signal is input to the test selecting circuit 10. Inside the test selection circuit 10, the OR of the block selection signal and the test signal is calculated by OR gates 12-1 to 12-N. Here, when "H" is input as a test signal to the test signal line 11 to perform a test, the test selection circuit 10 causes all the I / O blocks 2-- regardless of the block selection signal from the block selection circuit 1. A block selection signal is output to 1-2-N. In the I / O blocks 2-1 to 2-N to which the block selection signals are supplied via the block selection signal lines 4-1 to 4-N,
The same input signal is received from the input bus 6 in synchronization with the operation clock signal, and the result is output as an output signal from the output buses 7-1 to 7-N.

FIG. 2 is a time chart of each signal in the test of the semiconductor circuit of the first embodiment. In FIG. 2, the horizontal axis indicates time, and the vertical axis indicates input / output signals. Here, assuming that the test time of one I / O block takes T time, description will be given with reference to FIG. When the test signal is input to the test selection circuit 10, all the I / O blocks 2-1 to 2-N are selected, and the same input signal from the input bus 6 is applied to all the I / O blocks 2-1 to 2-N in synchronization with the operation clock signal. It is input to the I / O blocks 2-1 to 2-N. Thereafter, since the outputs of all the I / O blocks 2-1 to 2-N are output as output signals from the output buses 7-1 to 7-N, the test ends after time T.

As described above, according to the configuration of the first embodiment, when a test signal is input, I / Os having the same functions have the same functions.
The test of the O block can be performed simultaneously.

Next, FIG. 3 shows Embodiment 2 of the present invention.
3 is a diagram showing a circuit configuration of the semiconductor circuit of FIG. Here, components corresponding to the components described in FIG. 1 showing the first embodiment are denoted by the same reference numerals, and redundant description will be omitted. In FIG. 3, reference numeral 13 denotes each I / O block 2-1.
A comparison matching circuit 14 for comparing output signals input from .about.2-N is a comparison result output terminal of a result output of the comparison matching circuit 13.

FIG. 4 is a circuit diagram showing the inside of a comparison matching circuit in which the number of output signal lines of the semiconductor circuit according to the second embodiment is connected to n I / O blocks. In FIG. 4, Ex. 15 inverts the exclusive OR of the output buses 7-1 to 7-N of each I / O block. NOR gate, 16 is AN
A D gate, 17 is a final AND gate, and 18 is a flip-flop (hereinafter referred to as FF). Furthermore, 20 is Ex.
Ex. Output from NOR gate 15. NOR output signal,
21 is an AND output signal output from the AND gate 16, 22
Is the final output signal of the final AND gate.

The circuit operation according to the second embodiment will be described. The circuit operation of the second embodiment differs from that of the first embodiment in that the output signals of the output buses 7-1 to 7-N of the I / O blocks 2-1 to 2-N are sent to the comparison matching circuit 13. That is, the output of the comparison judgment is obtained from the comparison result output terminal 14. In the first embodiment, a test signal is input to the test selection circuit 10 and all the I / O blocks 2-1 to 2-N are synchronized with the operation clock signal from the input bus 6 by the output of the block selection signal. Capture the input signal,
The output results of the I / O blocks 2-1 to 2-N are output to the output bus 7-1 to
7-N were output as output signals, and each output was checked to determine the test result. By providing the comparison matching circuit 13 of the second embodiment shown in FIG.
The test results can be determined by comparing the output signals of the / O blocks 2-1 to 2-N.

Further, when the number of output signal lines of the I / O blocks 2-1 to 2-N is n as shown in FIG. The output signal from the output bus 7-1 is used as a reference output signal, and the output signals output from the other I / O blocks 2-2 to 2-N are also input to the comparison matching circuit 13, so that the reference output signal and other output signals are output. A comparison is made to determine whether the output signals match, and the result of the comparison is synchronized with the operation clock and output to the comparison result output terminal.

In the comparison coincidence circuit 13, the exclusive OR of the output signals from the output buses 7-1 and 7-2 to 7-N is inverted. I / O that is taken by NOR gate 15 and becomes a reference
It is checked whether the output is different from the output of block 2-1. A NOR output signal 20 is output. If the outputs of all the output buses 7-1 to 7-N of the I / O blocks 2-1 to 2-N are the same, Ex. The same signal is output as the NOR output signal 20. Further, each Ex. The logical sum of the NOR output signal 20 is obtained by the AND gate 16, and the resulting AND output signal is obtained.
Outputs 21. This is performed for all n output signal lines of the I / O blocks 2-1 to 2-N. Finally, the logical sum of each AND output signal 21 is obtained by the final AND gate 17, and the final output of the result is output. The signal 22 is output. The final output signal 22 is F.
F. At 18, the data is output from the comparison result output terminal 14 in synchronization with the operation clock signal.

As described above, by adding the comparison matching circuit 13 and the comparison result output terminal 14, the I / O block 2
The output signals from the output buses 7-1 to 7-N from -1 to 2-N need not be checked for all n output signal lines, and the output bus 7-1 from the I / O block 2-1 is not required. It is possible to determine the test results of all the I / O blocks 2-1 to 2-N only by checking the output signal and the output of the comparison result output terminal 14 alone.

The I / O in the first and second embodiments
The block may be replaced with a memory block such as a RAM.

[0023]

As is apparent from the above description, according to the present invention, when a test signal is input, a plurality of I / O blocks having the same function can be tested at the same time, thereby reducing the test time. Can be achieved.

Even when the number of pins to be connected for testing the semiconductor circuit is limited, simply adding one comparison result output terminal to the number of output signal lines of one I / O block allows the remaining I / O blocks to be connected. This has the effect that the test of the O block can be performed simultaneously and the number of pins to be connected can be reduced.

[Brief description of the drawings]

FIG. 1 is a diagram showing a circuit configuration of a semiconductor circuit according to a first embodiment of the present invention.

FIG. 2 is a time chart of each signal in a test of the semiconductor circuit of the first embodiment.

FIG. 3 is a diagram illustrating a circuit configuration of a semiconductor circuit according to a second embodiment of the present invention;

FIG. 4 is a circuit diagram showing the inside of a comparison matching circuit in which the number of output signal lines of the semiconductor circuit according to the second embodiment is connected to n I / O blocks;

FIG. 5 is a diagram showing a circuit configuration of a conventional semiconductor circuit.

FIG. 6 is a time chart of each signal in a test of a conventional semiconductor circuit.

[Explanation of symbols]

1: Block selection circuit, 2-1 to 2-N: I / O block, 3: Block designation signal line, 4-1 to 4-N: Block selection signal line, 5: Clock signal line, 6: Input bus, 7-1 to 7-N: output bus, 10: test selection circuit,
11 ... test signal line, 12-1 to 12-N ... OR gate, 13 ...
Comparison match circuit, 14 ... comparison result output terminal, 15 ... Ex. N
OR gate, 16 AND gate, 17 final AND gate, 18 flip-flop (FF), 20 E
x. NOR output signal, 21 ... AND output signal, 22 ... Final output signal.

Claims (2)

[Claims] 1. A plurality of I / O blocks having the same function, and an I / O block selected by inputting a block designating signal.
A semiconductor circuit having a block selection circuit for supplying a block selection signal only to a block, comprising: a test selection circuit for supplying the block selection signal to all the I / O blocks in response to a test signal input; A semiconductor circuit wherein output signals from the I / O block are output simultaneously when a signal is input. 2. The semiconductor circuit according to claim 1, further comprising a comparison matching circuit that performs a comparison determination as to whether or not all output signals from the I / O block match each other in synchronization with a clock signal. .