JPH10191267A - Field double speed conversion circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To display a normal video without the occurrence of screen curve even in a signal with much skews by stabilizing a reading clock. SOLUTION: A video signal digitized by an A/D converter 2 is written into a field memory 12 with the write clock signal 31 of a horizontal frequency which is (n) times based on the timing of a memory write resetting signal 11a. The field memory 12 reads a digital double speed video signal 23a with a read clock signal 41 of 2.n-fold horizontal frequency based on the timing of a read resetting signal 21a. The video signal which is double speed-converted is obtained. At that time, the read clock signal 41 is generated by AFC control executed only by the comparison of the frequencies based on an input horizontal synchronizing signal with a frequency comparison horizontal AFC circuit 40. The stable field memory 12 without the occurrence of the horizontal phase error can be read even if skew exists and therefore the occurrence of screen curve can be prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a field frequency conversion circuit for scanning a field at twice the frequency in order to reduce flicker, and more particularly to a field frequency conversion circuit suitable for preventing image distortion due to skew.

[0002]

2. Description of the Related Art Generally, in a standard television system,
When classified according to the transmission format of color television signals, it is well known that the NTSC system used in Japan, the PA used in Thailand, China, etc., in addition to many European countries.
L method, SEC mainly used in Eastern European countries
There are three methods, the AM method.

[0003] Manufacturers in Japan also produce PAL and SECAM compatible television receivers for export in addition to the normal NTSC system. In some cases, local production is carried out. Therefore, in order to supply high-quality television receivers, PA
Designs of television receivers and the like in the L system or the SECAM system have been designed and many improvements have been made. By the way, the above-mentioned PAL system and SECAM
In the TV signal system such as the system, the scanning frequency of one field is 50 Hz. However, since this scanning frequency is not fast enough to be ignored visually,
A so-called large screen flicker disturbance occurs, which causes flicker on the screen.

In order to solve such flicker interference, conventionally, an image memory has been used and the vertical scanning frequency has been reduced to two.
A field double speed conversion circuit has been developed which performs double conversion. That is, by converting the field frequency to 100 Hz, which is twice as high, the frequency becomes undetectable to human eyes.
I try to improve flicker interference.

FIG. 4 is a block diagram showing an example of a field double speed conversion circuit used in such a conventional television receiver.

As shown in FIG. 4, an input video signal 1 is supplied to an analog-to-digital converter 2 (hereinafter abbreviated as A / D converter 2). The A / D converter 2 converts the analog input video signal 1 into a digital signal and outputs a digital video signal 3
Is output.

A vertical synchronizing signal 4 synchronized with an input video signal
Is supplied to the write reset generation circuit 5 and also to the vertical frequency conversion circuit 6, and the horizontal synchronization signal 7 is supplied to the first horizontal AFC circuit 8.

The first horizontal AFC circuit 8 compares the phase with a reference signal divided by 1 / n (n is a natural number) by an internal counter based on the horizontal synchronizing signal 7 to determine whether the phase is in a predetermined relationship. AFC control is performed so as to generate a write clock signal 9 and a write horizontal timing signal 10 having n times the horizontal frequency (fh) synchronized with the horizontal synchronization signal.

A write reset signal generating circuit 5 generates a field memory write reset signal 11 at a cycle of the vertical synchronizing signal 4 and at a timing synchronized with the write horizontal timing signal 10. That is, the timing of this reset signal indicates the position where the writing of the video signal into the field memory 12 is started.

On the other hand, the second horizontal AFC circuit 13 has a read clock signal 14 having a horizontal frequency of 2.n times (n is a natural number) synchronized with the horizontal synchronizing signal 7 and a frequency twice as high as the input horizontal synchronizing signal. (2 · fh) read horizontal timing signal 15 and horizontal drive signal 16 are generated,
Output.

The vertical frequency conversion circuit 6 inserts a vertical synchronizing signal in the middle of the vertical synchronizing signal from the input vertical synchronizing signal 4, and generates a double-speed vertical synchronizing signal 17 having a double vertical frequency.

The vertical timing signal circuit 18 receives the double-speed vertical synchronization signal 17 and outputs a vertical drive signal 20 and a read vertical timing signal 19, respectively.

The read reset generation circuit 21 receives the read horizontal timing signal 15 and the read vertical timing signal 19, and outputs a field memory read reset signal 22 indicating the read timing of the field memory 12.

The field memory 12 generates a digital double-speed video signal 23 in which the vertical frequency and the horizontal frequency are doubled and the same signal is read out twice vertically.

A digital-to-analog converter 24 (hereinafter, referred to as
The D / A converter 24 converts the digital double-speed video signal 23 into an analog signal, and outputs it as a double-speed video signal 25 to driving means (not shown). Thus, an image based on the double-speed image signal 25 is displayed on the picture tube.

FIGS. 5A and 5B are waveform diagrams for explaining the operation of the conventional field double speed conversion circuit having such a configuration. FIG. 5A shows an input video signal 1 and FIG. 5C shows the write reset signal 11, FIG. 5D shows the read reset signal 22, and FIG. 5E shows the output video signal 25.

Now, the video signal shown in FIG.
It is assumed that it is supplied to the converter 2. Then, the video signal 1 is written by the field memory 12 at the timing of the write clock signal 11 from the write reset signal generation circuit 11 based on the write clock signal from the first horizontal AFC circuit 8.

At this time, the vertical synchronizing signal 4 supplied to the write reset signal generating circuit 5 is synchronized with the input video signal 1 as shown in FIGS. 5A and 5B. , The field memory 12
Is started at the timing of the write reset signal shown in FIG. 5C.

Thereafter, based on the read clock signal 14 from the second horizontal AFC circuit 13, the field memory 12 starts reading the read reset signal 22 from the read reset signal generating circuit 21 shown in FIG. , And outputs it to a D / A converter 24 as a digital double-speed video signal 23.

That is, since the clock signal supplied to the field memory 12 has a frequency twice as high as that of the write operation, the video signal output from the D / A converter 24 is, for example, as shown in FIG. As shown in (1), one field is read twice at double speed.

Therefore, by performing the above-described processing on the input video signal, the field frequency of the video signal can be converted from 50 Hz to 100 Hz, which is doubled.

By the way, in consideration of signals input to the television receiver, various non-standard signals may be supplied. For example, in a reproduced signal from a video cassette tape recorder (hereinafter, referred to as a VTR) for general household use, a phenomenon called skew that causes a phase shift due to switching of a head before a vertical synchronizing signal may occur.

If a reproduced signal having such a skew is displayed on a screen, a phase shifted during a vertical blanking period is usually drawn, so that the skew does not affect the appearance of the screen. However, since the degree of the skew varies depending on the frequency of use of the video tape and the performance depending on the VTR to be reproduced, a video signal having a large skew may be reproduced. When such a large skewed reproduction signal is displayed on the screen, a horizontal screen bend may occur at the top of the screen.

FIG. 6 is a timing chart showing the operation when the video signal having such a large skew is processed by the field double speed conversion circuit shown in FIG. 4, and FIG. 6 (a) shows the input video signal 1. 6B shows a phase error of the first horizontal AFC circuit 8 when a skew occurs, and FIG.
(C) shows the output video signal 25.

In FIG. 6, the input video signal has a phase shift at the timing of T51 shown in FIG.
A phase error occurs as shown in FIG. In this example, it can be seen that the phase shift amount of the skew is large, and at the timing of T52 when the shift of the skew is pulled in and the clock frequency is stabilized, the video portion of the input video signal is slightly bitten. For this reason, as shown in FIG. 6C, the output video signal 25 is greatly compressed into the video signal at the timing of T52 because the time axis is compressed to １ ／. For this reason, if the video signal shown in FIG. 6A is displayed on the screen, the upper part of the screen will appear to be greatly bent. An example of such a screen display is shown in FIG.

FIG. 7 is a screen display diagram when a skewed video signal is displayed on the screen.
FIG. 7B shows a case where the image is displayed on a normal television receiver, and FIG. 7B shows a case where the image is displayed on a receiver using the field double speed conversion circuit shown in FIG.

Now, as an input video signal, a video signal having one vertical line in the middle and having a skew is converted to a normal television receiver and a field double speed conversion circuit which are not provided with a field double speed conversion circuit. It is assumed that they are supplied to the provided television receivers. Then, in a normal television receiver, FIG.
As shown in (1), the display is based on the video signal to the extent that a slight bend is seen at the top of the screen, and does not significantly affect the video quality. However, in a television receiver provided with a field double speed conversion circuit, as shown in FIG. 7B, the screen is considerably distorted to the left, which adversely affects the image quality.

For such a reason, a field double speed conversion circuit has conventionally been used to eliminate flicker disturbance on the screen. However, in the conventional field double speed conversion circuit, the time direction is compressed to 1/2. Therefore, when a skew occurs in the video signal, the skew pull-in period is doubled on the screen, so that there is a problem that the screen curve due to the influence of the skew looks large.

As a solution to the above problem, horizontal A
It is conceivable to increase the time constant of the pull-in of the FC by about twice. However, if the time constant is increased, the jitter is greatly increased due to the influence of noise and the like, and at present, the problem cannot be solved. .

[0030]

As described above, in the conventional field double speed conversion circuit, since the time direction is compressed to １ ／, if a skew occurs in the video signal, the skew pull-in period is reduced to the screen. In the above, since the image is enlarged twice, there is a problem that the screen bend due to the influence of the skew looks large, which adversely affects the image quality.

Accordingly, the present invention has been made in view of the above-mentioned problems, and it is possible to stabilize a read clock so that a normal image can be displayed without causing screen bend even in a signal having a large skew. It is an object of the present invention to provide a field double speed conversion circuit that can perform the conversion.

[0032]

According to the first aspect of the present invention, there is provided a field double speed conversion circuit for converting an input analog video signal into a digital video signal, and a frequency synchronizing with an input horizontal synchronizing signal. Is n of the input synchronization signal.
A first clock signal and a first horizontal timing signal that are automatically controlled so as to be doubled (n is a natural number) and to have a predetermined phase with respect to the input horizontal synchronization signal.
A horizontal AFC circuit, a write timing signal generating circuit for generating a write timing signal based on an input vertical synchronization signal and a first horizontal timing signal from the first horizontal AFC circuit, and a frequency of the input vertical synchronization signal. A vertical frequency conversion circuit for generating a read vertical synchronization signal that has been doubled, and a first read vertical timing signal and a second read vertical timing signal synchronized with the read vertical synchronization signal from the vertical frequency conversion circuit; The second clock is generated by automatically controlling the read vertical timing signal generation circuit and the phase control based on the input horizontal synchronization signal so that only the frequency becomes 2 · m times (m is a natural number) the input synchronization signal. A second horizontal AFC circuit for generating a signal and a second horizontal timing signal; A read timing signal generating circuit for generating a read timing signal having a frequency twice as high as the write timing signal from the first read vertical timing signal; a storage means for storing a digital input video signal from the conversion means; The digital input video signal is written to the storage means with the first clock signal based on the timing signal, and the second video signal is read based on the read timing signal at the time of reading.
And control means for performing control so as to read out from the storage device with the clock signal.

In the present invention, the conversion means converts the input analog video signal into a digital video signal. The first horizontal AFC circuit is automatically controlled so that the frequency becomes n times (n is a natural number) the input synchronization signal and the phase becomes a predetermined phase with respect to the input horizontal synchronization signal in synchronization with the input horizontal synchronization signal. Thus, a first clock signal and a first horizontal timing signal are created. The write timing signal generation circuit generates a write timing signal based on the input vertical synchronizing signal and the first horizontal timing signal from the first horizontal AFC circuit. The vertical frequency conversion circuit creates a read-out vertical synchronizing signal obtained by converting the frequency of the input vertical synchronizing signal to twice. The vertical timing signal generation circuit
A first read vertical timing signal and a second read vertical timing signal synchronized with the read vertical synchronizing signal from the vertical frequency conversion circuit are created. Second horizontal A
The FC circuit does not perform the phase control based on the input horizontal synchronizing signal, but automatically controls the frequency so that only the frequency becomes 2 · m times (m is a natural number) the input synchronizing signal and the second clock signal and the second clock signal. To create a horizontal timing signal. The read timing signal generating circuit generates a read timing signal having a frequency twice as high as the write timing signal from the second horizontal timing signal and the first read vertical timing signal. The storage unit stores the digital input video signal from the conversion unit. In this case, the control means writes the digital input video signal to the storage means with the first clock signal based on the write timing signal, and reads the second input signal based on the read timing signal at the time of reading. It is controlled to read out from the storage device by a clock signal. Thereby, since the read clock of the field memory as the storage means is stabilized within the effective screen of the video signal,
Screen turning due to skew can be prevented.

According to a second aspect of the present invention, there is provided a field double-speed conversion circuit for converting an input analog video signal into a digital input video signal and outputting the digital input video signal, and synchronizing with an input horizontal synchronizing signal. A first clock signal and a first horizontal timing signal are created by automatically controlling the frequency to be n times (n is a natural number) the input synchronization signal and the phase to be a predetermined phase with respect to the input horizontal synchronization signal. A first horizontal AFC circuit, a write reset signal generating circuit for generating a write reset signal based on an input vertical synchronization signal and a first horizontal timing signal from the first horizontal AFC circuit, and the input vertical synchronization signal A vertical frequency conversion circuit for generating a readout vertical signal whose frequency is doubled, and a vertical synchronization signal read out from the vertical frequency conversion circuit. Vertical timing signal generating circuit for generating a vertical timing signal, and automatic control so that only the frequency becomes 2 · n times (n is a natural number) the input synchronization signal without performing phase control based on the input horizontal synchronization signal A second horizontal AFC circuit for generating a second clock signal and a second horizontal timing signal, and the write reset signal based on the second horizontal timing signal and a vertical timing signal from the vertical timing signal generation circuit. A read reset signal generating circuit for generating a read reset signal having a frequency twice as high as the above, and a digital memory for storing the digital video signal, wherein writing is started based on a write reset signal from the write reset signal generating circuit. The first video signal from the first horizontal AFC circuit causes the digital video At the time of reading and writing the data in the storage area, the storage area to be read is reset to the head area by the read reset signal from the read reset signal generation circuit, and stored by the second clock signal from the second horizontal AFC circuit. And a digital / analog converter for converting a digital video signal output from the field memory into an analog video signal and outputting the analog video signal.

According to the second aspect of the present invention, the operation is the same as that of the first aspect, and a read reset signal synchronized with the vertical timing signal can be generated by the read reset signal generating circuit. As a result, the digital video signal read from the field memory has the vertical frequency and the horizontal frequency doubled and the same signal is optimally read twice in the vertical cycle, and a skewed video signal is input. Even if this is done, a normal double-speed output video signal can be obtained, and the phase shift correction by the second horizontal AFC circuit is also performed by the read reset signal.
It does not adversely affect the vertical deflection system. Therefore, it is possible to prevent the occurrence of screen bending.

According to a third aspect of the present invention, there is provided a field double-speed conversion circuit for converting an input analog video signal into a digital input video signal and outputting the digital input video signal, and synchronizing with an input horizontal synchronizing signal. A first clock signal and a first horizontal timing signal are created by automatically controlling the frequency to be n times (n is a natural number) the input synchronization signal and the phase to be a predetermined phase with respect to the input horizontal synchronization signal. A first horizontal AFC circuit, a write reset signal generating circuit for generating a write reset signal based on an input vertical synchronization signal and a first horizontal timing signal from the first horizontal AFC circuit, and the input vertical synchronization signal A vertical frequency conversion circuit for generating a readout vertical signal whose frequency is doubled, and a vertical synchronization signal read out from the vertical frequency conversion circuit. A read vertical timing signal generating circuit for generating the first read vertical timing signal and the second read vertical timing signal, and a phase control based on the input horizontal synchronizing signal is not performed. a second horizontal AFC circuit that automatically generates a second clock signal by automatically controlling it to be n times (n is a natural number), a read horizontal counter that divides the second clock signal by n, Resetting means for resetting the readout horizontal counter by the horizontal synchronization signal at the timing when the readout vertical timing signal is generated,
A read horizontal timing generating circuit for generating a second horizontal timing signal from an output signal of the read horizontal counter; and a second read timing signal which is twice as large as the write reset signal based on the second horizontal timing signal and the first read vertical timing signal. A read reset signal generating circuit for generating a read reset signal of a frequency; and a digital memory for storing the digital video signal, wherein the digital memory is configured to start writing based on a write reset signal from the write reset signal generating circuit. The digital video signal is written to the storage area by a first clock signal from one horizontal AFC circuit, and at the time of reading, a storage area to be read by the read reset signal from the read reset signal generation circuit is reset to a first area, The second horizontal AFC Field memory for sequentially reading and outputting a video signal stored by a second clock signal from a path from a head area, and digital / analog conversion for converting an output digital video signal from the field memory into an analog video signal and outputting the analog video signal And a container.

According to the third aspect of the present invention, the same operation as in the first and second aspects of the present invention is performed. However, in the present invention, the vertical frequency converting circuit is provided by a read vertical timing signal generating circuit. A first read vertical timing signal and a second read vertical timing signal synchronized with the read vertical synchronizing signal from the CPU are generated. After that, the read-out horizontal counter is reset by the horizontal synchronizing signal at a timing when the second read-out vertical timing signal is generated by reset means. Thereby, even if a phase shift occurs due to the second horizontal AFC circuit, it can be reset so as to be synchronized with the timing of the second read vertical synchronization signal (for example, the vertical blanking signal). It is possible to obtain an output video signal that has been double-speed converted. Also,
Since the second horizontal AFC circuit and the readout horizontal counter, reset means and readout horizontal timing generation circuit are configured so as not to interfere with each other, the frequency comparison control operation by the second horizontal AFC control is adversely affected. Therefore, even if the input video signal has a large skew, it is possible to display an optimal video without curving the screen.

According to a fourth aspect of the present invention, in the field double speed conversion circuit according to the third aspect, the second readout vertical timing signal is:
A vertical blanking signal in the input video signal,
The reset means resets using the timing when the vertical blanking signal rises.

According to a fourth aspect of the present invention, the second readout vertical timing signal is a vertical blanking signal in an input video signal, and the reset means uses a timing at which the vertical blanking signal rises. To reset. Thus, as described above, even when a horizontal phase shift occurs due to the frequency comparison control in the second horizontal AFC circuit, the occurrence of the phase shift is suppressed by resetting at the rising timing of the vertical blanking signal. It is possible to obtain the same effect as the above invention.

According to a fifth aspect of the present invention, there is provided a field double-speed conversion circuit according to any one of the first to fourth aspects, wherein the first and second horizontal AFC circuits are provided. , A digital AFC circuit.

According to the fifth aspect of the present invention, the first and second horizontal AFC circuits are provided with a digital AF system.
By adopting the C circuit, it is possible to perform processing without deterioration peculiar to digital, so that it is possible to generate a more stable clock signal, and it is possible to configure a higher quality field double speed conversion circuit. Become.

[0042]

Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a field double speed conversion circuit according to the present invention. In the circuit shown in FIG. 1, the same components as those in the circuit shown in FIG. 4 are denoted by the same reference numerals.

As shown in FIG. 1, the input video signal 1 is A /
It is given to the D converter 2. The A / D converter 2 converts the analog input video signal 1 into a digital signal and outputs a digital video signal 3.

The vertical synchronizing signal 4 synchronized with the input video signal
Is supplied to the write reset generation circuit 5 and also to the vertical frequency conversion circuit 6, and the horizontal synchronizing signal 7 is supplied to the phase comparison horizontal AFC circuit 30.

The phase comparison horizontal AFC circuit 30 uses a 1 / n (n is a natural number) internal counter based on the horizontal synchronization signal 7.
AFC control is performed so that the phases are synchronized with each other, and a write clock signal 31 of n times the horizontal frequency (fh) synchronized with the horizontal synchronization signal and a predetermined timing are generated. The write horizontal timing signal 32 is generated.

The write reset signal generating circuit 5 generates a field memory write reset signal 11a at the cycle of the vertical synchronizing signal 4 and at a timing synchronized with the write horizontal timing signal 32.

The frequency comparison horizontal AFC circuit 40 converts the horizontal synchronizing signal 7 and the clock signal 41 by an internal counter into 2 · n.
A frequency comparison with a frequency-divided (n is a natural number) signal AFC operation is performed. That is, the readout horizontal counter (see FIG. 2) provided in the frequency comparison horizontal AFC circuit 40 is synchronized with the horizontal synchronization signal input by the vertical blanking timing signal 26 generated and supplied by the vertical timing generation circuit 18, A read clock signal 41 having a horizontal frequency (2 · n · fh) twice as high as that of the input horizontal synchronizing signal is generated and output via a read horizontal timing circuit 56 (see FIG. 2). A horizontal timing signal 42 of the horizontal frequency (2 · fh) and a horizontal drive signal 16a are generated and output.

The vertical frequency conversion circuit 6 inserts a vertical synchronization signal in the middle of the vertical synchronization signal from the input vertical synchronization signal 4, and generates a double-speed vertical synchronization signal 17 having a double vertical frequency.

The vertical timing signal circuit 18 receives the double-speed vertical synchronizing signal 17 and outputs a vertical drive signal 20a, a read vertical timing signal 19, and a vertical blanking signal 126, respectively.

The read reset generation circuit 21 receives the read horizontal timing signal 42 and the read vertical timing signal 19, and outputs a field memory read reset signal 21a indicating the read timing of the field memory 12.

The field memory 12 writes the digital video signal 3 with the write clock signal 31 having n times the horizontal frequency (fh) based on the timing of the field memory write reset signal 11a and the timing of the field memory read reset signal 21a. 2
Reading is performed with a read clock signal 41 having n times the horizontal frequency (2 · n · fh). This makes it possible to generate a digital double-speed video signal 23a in which the vertical frequency and the horizontal frequency are doubled and the same signal is read out twice in vertical synchronization, and the digital double-speed video signal 23a is
It is provided to the D / A converter 24.

The D / A converter 24 converts the digital double-speed video signal 23a into an analog signal,
And outputs it to the driving means (not shown). This allows
An image based on the double-speed image signal 25a can be displayed on the picture tube.

FIG. 2 is a block diagram showing a specific example of a circuit configuration of the frequency comparison horizontal AFC circuit 40 used in the field double speed conversion circuit having the above configuration.

As shown in FIG. 2, the frequency comparison horizontal AFC circuit 40 used in the field double speed conversion circuit of the present invention includes a frequency comparator 50, to which the horizontal synchronizing signal 7 is supplied. Is done. Frequency comparator 50
Is that the cycle of the horizontal synchronization signal 7 is the read clock signal 41
It is determined whether it is 2 × n clocks or more or less than 2 × n clocks, and the determination result is given to the loop filter 52 as a frequency error signal 51.

The loop filter 52 determines the pull-in characteristic of the AFC, gives a time constant to the frequency error signal 51, and gives it to the voltage control oscillator 54 as the voltage control oscillator control voltage 53. The voltage controlled oscillator 54 outputs the read clock signal 41 at a frequency controlled by the voltage controlled oscillator control voltage 53. The read clock signal 14
1 is given to the frequency comparator 50.

With the above-mentioned loop constituted by the frequency comparator 50, the loop filter 52 and the voltage controlled oscillator 54, when the frequency of the horizontal synchronizing signal 7 is fh, 2 · n ·
It is possible to feedback control the oscillation frequency of the voltage controlled oscillator 54 as the read clock generation circuit so that the frequency becomes fh. Therefore, unlike the conventional read PLL, in this example, only the frequency comparison is performed by the read PLL using the frequency comparator 50. Therefore, even if skew occurs,
The error signal is generated only once and immediately becomes stable.

On the other hand, the read horizontal counter 55 divides the read clock signal 41 by n and circulates at twice the input horizontal synchronizing frequency. The read horizontal counter output 60 is a read horizontal timing circuit 56.
, And the readout horizontal timing circuit 56 outputs the horizontal timing signal 42 and the horizontal drive signal 16a for giving the timing of the horizontal deflection circuit, respectively.

The horizontal counter reset generation circuit 58 generates a pull-in signal 59 at the edge of the horizontal synchronizing signal 7 at the timing when the vertical blanking signal 26 starts, and resets the read horizontal counter 55. That is, the phase shift caused by not performing the phase adjustment can be adjusted by resetting the readout horizontal counter 55 for each field.

Next, the operation of the frequency comparison AFC circuit which is a main part in the field double speed conversion circuit of the present invention will be described in detail with reference to FIG.

FIG. 3 is a timing chart for explaining the operation of the frequency comparison AFC circuit. FIG. 3A is a waveform chart showing an input video signal, and FIG. 3C is an output waveform diagram of a VCO control voltage serving as a read clock signal, FIG. 3D is a waveform diagram showing a vertical blanking signal, and FIG.
FIG. 3E is a waveform diagram showing a horizontal phase error when reset, and FIG. 3F is a waveform diagram showing a double speed converted output video signal.

The frequency comparison horizontal AFC circuit 40 shown in FIG.
As a read PLL, only the frequency comparison AFC control is performed without performing the phase comparison AFC control on the input horizontal synchronization signal as described above. That is,
In the case of the frequency comparison AFC control, since the error signal does not occur if the frequency is matched even if the phase is shifted, if the reset is not performed by the pull-in signal 59 (see FIG. 2), FIG. As shown in (1), the horizontal phase error does not follow the skew in phase but gradually shifts.

However, the VCO control voltage is
As shown in (c), there is a slight change only when a skew shift occurs, but thereafter, the level returns to a normal level, and the video signal displayed on the screen becomes completely stable during a certain period. Become.

On the other hand, horizontal counter reset generation circuit 58
When the reset is performed by the pull-in signal 59 from FIG. 3, the horizontal phase error is as shown in FIG. That is, in this case, since the reset is performed at the timing of the vertical blanking signal in FIG. 3D, the skew phase error is reset,
It is also possible to prevent the phase shift from gradually spreading. This pull-in operation does not affect the VCO control voltage and does not malfunction because the processing circuit for performing the pull-in exists outside the loop of the frequency comparison AFC control system.

The horizontal drive signal 16 supplied to the deflection system
Since a is generated from the read clock system, there is no problem even if the phase is shifted from the input signal because it is synchronized with the video signal output from the field memory. However, for example, as the horizontal phase gradually shifts, as a result, if the horizontal phase exceeds one horizontal period, the vertical synchronization of readout also shifts by one horizontal period. It is also conceivable that a problem may occur in the processing in. However, in the present embodiment, since the phase error can be reduced by performing the reset by the pull-in signal 59, the normal operation can be performed without adversely affecting the vertical deflection circuit. .

Therefore, according to the present embodiment, in the field double speed conversion circuit for scanning at twice the field frequency in order to reduce flicker, the field frequency can be reliably maintained even when a video signal with a large skew is supplied. Double-speed conversion can be performed, and as a result, it is possible to prevent the occurrence of screen bending at the time of screen display. As a result, the image quality can be improved, and the quality of the television receiver itself can be improved.

In this embodiment, the write clock for the field memory of the field double speed conversion circuit is set to n times the horizontal frequency, and the read clock is set to 2 · n times the horizontal frequency. For example, if the read clock has a horizontal frequency of 2 · m times and the frequency of the write clock is different from m, the same effects as those of the above embodiment can be obtained. There is also an effect that horizontal compression / expansion is possible. Similarly, since a horizontal frequency conversion function can be provided, the present invention can be applied to a case where the horizontal frequency is set to 33.7 kHz and the HDTV and the horizontal frequency are matched, for example. Get.

In this embodiment, the phase comparison horizontal AFC circuit 30 and the frequency comparison horizontal AFC circuit 40 are used.
Although the horizontal AFC circuit such as that described above is described as an analog type, the same effect can be obtained even when a digital type horizontal AFC circuit is adopted, and similar effects can be obtained.

[0069]

As described above, according to the present invention, it is possible to prevent the occurrence of screen bending due to skew in the field double speed conversion circuit, and even if a VTR reproduction signal is supplied, the image quality can be reduced. It is possible to provide a high-quality field double speed conversion circuit that does not cause deterioration. Further, a frequency comparison type AF that does not detect a phase shift
Even in the C control system, by resetting the vertical blanking counter, the AFC operation is not affected, and the phase can be adjusted for each readout field. Also, there is an effect that a period shift of the vertical synchronizing signal which occurs when exceeding the frequency can be prevented. Further, if a horizontal AFC circuit is of a digital type, a more stable field double speed conversion function can be realized by generating a more stable clock unique to digital.

[Brief description of the drawings]

FIG. 1 is a block diagram showing an embodiment of a field double speed conversion circuit according to the present invention.

FIG. 2 is a block diagram showing a specific circuit configuration of a frequency / phase comparison AFC circuit.

FIG. 3 is a characteristic diagram for explaining operation;

FIG. 4 is a block diagram showing an example of a conventional field double speed conversion circuit.

FIG. 5 is a waveform chart for explaining operation.

FIG. 6 is a waveform chart showing characteristics when a skewed video signal is supplied.

FIG. 7 is a screen display diagram when a skewed video signal is displayed on the screen.

[Explanation of symbols]

2 A / D converter, 5 Write reset signal generator, 6 Vertical frequency converter, 12 Field memory, 17 Vertical frequency converter, 18 Vertical timing signal generator, 21 Read reset signal generator ,
24: D / A converter, 30: phase comparison horizontal AFC circuit,
40 ... Frequency comparison AFC circuit.

Claims (5)

[Claims] A conversion means for converting an input analog video signal into a digital video signal; a frequency n times (n is a natural number) of the input synchronization signal in synchronization with the input horizontal synchronization signal; A first horizontal AFC circuit for automatically controlling a horizontal synchronization signal to have a predetermined phase to generate a first clock signal and a first horizontal timing signal; an input vertical synchronization signal and the first horizontal AFC circuit; A write timing signal generation circuit for generating a write timing signal based on a first horizontal timing signal from a circuit; a vertical frequency conversion circuit for generating a read vertical synchronization signal obtained by doubling the frequency of the input vertical synchronization signal; A first read vertical timing signal and a second read vertical timing synchronized with a read vertical synchronization signal from the vertical frequency conversion circuit. A read-out vertical timing signal generating circuit for generating a signal; and performing automatic control so that only the frequency is 2 · m times (m is a natural number) the input synchronization signal without performing phase control based on the input horizontal synchronization signal. A second horizontal AFC circuit for generating a second clock signal and a second horizontal timing signal; and a second write timing signal based on the second horizontal timing signal and the first read vertical timing signal.
A read timing signal generating circuit for generating a read timing signal having a double frequency; a storage means for storing a digital input video signal from the conversion means; and storing the first clock signal based on the write timing signal. Control means for writing the digital input video signal to the means, and controlling to read from the storage device with the second clock signal based on the read timing signal at the time of reading. Field double speed conversion circuit. 2. An analog / digital converter which converts an input analog video signal into a digital input video signal and outputs the digital input video signal, and a frequency n times (n is a natural number) of the input synchronization signal in synchronization with the input horizontal synchronization signal. ), And a first horizontal AFC circuit for automatically controlling the input horizontal synchronizing signal so as to have a predetermined phase with respect to the input horizontal synchronizing signal to generate a first clock signal and a first horizontal timing signal; A write reset signal generating circuit for generating a write reset signal based on a first horizontal timing signal from the first horizontal AFC circuit; and generating a read vertical signal obtained by doubling the frequency of the input vertical synchronization signal. A vertical frequency conversion circuit for generating a vertical timing signal synchronized with a vertical synchronization signal read from the vertical frequency conversion circuit. The second clock signal and the second clock signal are automatically controlled so that only the frequency becomes 2 · n times (n is a natural number) the input synchronization signal without performing the phase control based on the input horizontal synchronization signal. A second horizontal AFC circuit for generating the horizontal timing signal of the above, and a read reset signal having a frequency twice as high as the write reset signal from the second horizontal timing signal and the vertical timing signal from the vertical timing signal generation circuit. A read reset signal generating circuit to be created; and a digital memory for storing the digital video signal, wherein the first horizontal AFC circuit starts writing based on a write reset signal from the write reset signal generating circuit. The digital video signal is written to the storage area by the first clock signal of The storage area to be read by the read reset signal from the output reset signal generation circuit is reset to the first area, and the video signal stored by the second clock signal from the second horizontal AFC circuit is sequentially read from the first area. A field double speed conversion circuit, comprising: a field memory for outputting; and a digital / analog converter for converting an output digital video signal from the field memory into an analog video signal and outputting the analog video signal. 3. An analog / digital converter for converting an input analog video signal into a digital input video signal and outputting the digital input video signal; and synchronizing with an input horizontal synchronizing signal, the frequency is n times the input synchronizing signal (n is a natural number). ), And a first horizontal AFC circuit for automatically controlling the input horizontal synchronizing signal so as to have a predetermined phase with respect to the input horizontal synchronizing signal to generate a first clock signal and a first horizontal timing signal; A write reset signal generating circuit for generating a write reset signal based on a first horizontal timing signal from the first horizontal AFC circuit; and generating a read vertical signal obtained by doubling the frequency of the input vertical synchronization signal. A vertical frequency conversion circuit, and a first read vertical timing signal and a second read signal synchronized with a vertical synchronization signal read from the vertical frequency conversion circuit. A vertical timing signal generating circuit for generating a vertical timing signal, and an automatic control so that only the frequency is 2 · n times (n is a natural number) the input synchronization signal without performing phase control based on the input horizontal synchronization signal. Control to generate a second clock signal;
A horizontal AFC circuit, a readout horizontal counter for dividing the second clock signal by n, and reset means for resetting the readout horizontal counter by the horizontal synchronization signal at a timing when the second readout vertical timing signal is generated. A readout horizontal timing generation circuit for generating a second horizontal timing signal from an output signal of the readout horizontal counter; twice the write reset signal from the second horizontal timing signal and the first readout vertical timing signal A read reset signal generating circuit for generating a read reset signal having a frequency of, and a digital memory for storing the digital video signal, wherein writing is started based on a write reset signal from the write reset signal generating circuit. First horizontal AFC circuit The digital video signal is written to the storage area by the first clock signal, and at the time of reading, the storage area to be read is reset to the head area by the read reset signal from the read reset signal generation circuit, and the second horizontal AFC A field memory for sequentially reading and outputting a video signal stored by a second clock signal from a circuit from a head area, and a digital / analog conversion for converting an output digital video signal from the field memory into an analog video signal and outputting the analog video signal And a field double speed conversion circuit. 4. The apparatus according to claim 1, wherein the second read vertical timing signal is a vertical blanking signal in an input video signal, and the resetting means resets using a timing at which the vertical blanking signal rises. The field double speed conversion circuit according to claim 3. 5. The first and second horizontal AFC circuits,
5. The field double speed conversion circuit according to claim 1, wherein the field double speed conversion circuit is a digital AFC circuit.