JPH10190672A - Cell processing circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To prevent a transmission band from being oppressed by outputting a reliable cell. SOLUTION: A data count circuit 1 outputs a data count signal 14 by counting a write-side clock 12 as may as data of a fixed-length cell in response to a write-side synchronizing signal 11. An AND circuit 2 output a synchronous detection signal 15 when the data count signal 14 synchronizes with the write- side synchronizing signal 11. A write control circuit 3 outputs a write address signal 18 in response to the synchronous detection signal 15 and write side- synchronizing signal 11. A storage circuit 4 receives an input cell and stores it in the address of the write address signal 18. Consequently, when the input is a short cell, a next input cell is overwritten to the cell in the storage circuit 4 and when the input is a long cell, only input data 19 which is equal to the number of the fixed length in the inputted cell are stored in the storage circuit 4 to overwrite the next input cell onto the cell.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a cell processing circuit, and more particularly to a cell processing circuit that discards cells other than cells having a predetermined number of data.

[0002]

2. Description of the Related Art Conventionally, this type of cell processing circuit is a cell other than a cell having an input cell having a predetermined number of data (hereinafter, such a cell is referred to as a fixed-length cell). It is used to monitor whether or not a cell other than a fixed-length cell is processed.

For example, JP-A-6-152700 discloses a frame length monitoring circuit for monitoring a cell or frame length of transmission data transmitted in units of fixed-length cells or frames. There is described a technique of detecting various signals early and outputting various signals for minimizing discarding of data in a frame.

In general, when a cell is shorter than the fixed length, the input data in the cell to be input next is added to the input data in the cell to make the cell longer than the fixed length. A fixed-length cell is created using only the valid input data with the fixed-length input data in the cell as the valid input data. If the cell is longer than the fixed length, the fixed-length input data in this cell is used. Is used as valid input data, a fixed-length cell is created using only this valid input data, and the created fixed-length cell is output as a valid cell.

[0005]

The above-described conventional cell processing circuit discards input data of a fixed-length cell other than the fixed length in its own cell or adds data of another cell. Then, the fixed-length cell is created, and the created fixed-length cell is output as a valid cell. Therefore, there is a problem that the cell regarded as valid is not reliable.

[0006] Further, since this unreliable cell is output, this cell is present on the line for transmitting this cell, so that the transmission band of other effective cells is compressed. There is a problem of fear.

SUMMARY OF THE INVENTION An object of the present invention is to provide a cell processing circuit capable of outputting a reliable cell and eliminating the possibility of pressure on the transmission band in order to eliminate such a conventional disadvantage.

[0008]

A cell processing circuit according to the present invention passes cells having a predetermined number of data and discards cells other than cells having a predetermined number of data.

When the cell processing circuit of the present invention receives a cell having a smaller number of data than a predetermined number of data, the cell processing circuit stores the cell as it is and overwrites the next received cell on the stored cell. By discarding a cell having a data number smaller than the predetermined data number by storing and receiving a cell having a data number larger than the predetermined data number, from the cell, By discarding more data than the number of data and storing it as a cell having the predetermined number of data, and overwriting and storing the next received cell on the stored cell, the number of data is smaller than the predetermined number of data. Cells having a large number of data are discarded.

Further, the cell processing circuit of the present invention responds to a write-side synchronization signal input in synchronization with the first input data in the input cell, and responds to each of the input data in the input cell. Data that resets the count value of the number of write-side clocks that are input in synchronization and outputs a data count signal indicating that the count has been completed after counting the number of write-side clocks by the predetermined number of data. A count circuit, an AND circuit that outputs a synchronization detection signal when the data count signal and the write-side synchronization signal are synchronized, and in response to the synchronization detection signal, the write-side synchronization signal, and the write-side clock. A write control circuit for outputting a write address signal indicating an address for storing the input data in the input cell; A synchronization signal generation circuit that outputs a synchronization signal that defines an interval for outputting cells having the predetermined number of data; a read-side clock that is input in synchronization with each output data in the output cell; A read control circuit for outputting a read address signal indicating an address for reading the output data in the output cell in response to a synchronization signal; and receiving the input data and inputting the input data to an address indicated by the write address signal. A storage circuit that stores data, reads data from an address indicated by the read address signal, and outputs the data as the output data, and receives the synchronization signal, and outputs the synchronization signal to a predetermined number of the read-side clocks. And a read-side synchronization signal in accordance with the output data output from the storage circuit. It is configured to include a buffer circuit for outputting Te.

Further, the write control circuit of the cell processing circuit of the present invention counts up a cell address A indicating an address for storing the input cell in response to the synchronization detection signal and generates a cell address A as a cell address signal A. In response to the output cell address generation circuit A and the write-side synchronization signal, a data address A indicating an address for storing the input data in the input cell is reset, and in synchronization with the input data, The data address A is counted up to the predetermined number of data for each input write clock, and the data address A is output as a data address signal A for each write clock in synchronization with the write clock. A data address generation circuit A, the data address signal A and the cell address signal. It is constructed and a write circuit for outputting a write address signal indicating an address for writing the input data in a cell to enter the A to the input to the storage circuit.

Further, the read control circuit of the cell processing circuit of the present invention counts up a cell address B indicating an address for reading the output cell in response to the synchronizing signal and outputs it as a cell address signal B. A cell address generation circuit B, in response to the synchronization signal, resetting a data address B indicating an address for reading the output data in the cell to be output, and reading the data input in synchronization with the output data A data address generation circuit that counts up the data address B up to the predetermined number of data for each side clock and outputs the data address B as a data address signal B for each read side clock in synchronization with the read side clock B, the data address signal B and the cell address signal B Is configured to include a, a read circuit for outputting a read address signal indicating an address for reading the output data in a cell to the output from the storage circuit Te.

[0013]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the cell processing circuit of the present invention.

The present embodiment shown in FIG. 1 responds to a write-side synchronizing signal 11 inputted in synchronization with the leading input data 19 in the cell 13 to be inputted. The count value of the number of write-side clocks 12 input in synchronization with the data 19 is reset, and after counting the number of write-side clocks 12 by a predetermined number of data, a data count signal 14 indicating that the count is completed. And an AND circuit 2 that outputs a synchronization detection signal 15 when the data count signal 14 and the write-side synchronization signal 11 are synchronized.
A write control circuit 3 that outputs a write address signal 18 indicating an address for storing input data 19 in the cell 13 to be input in response to the synchronization detection signal 15, the write-side synchronization signal 11, and the write-side clock 12; A synchronizing signal generating circuit 5 for outputting a synchronizing signal 21 for defining an interval for outputting cells having a predetermined number of data, and a read-side clock 20 input in synchronization with each output data 27 in the cell 25 for output And a read control circuit 6 for outputting a read address signal 24 indicating an address for reading output data 27 in a cell 25 which is output in response to the synchronization signal 21 and receiving the input data 19 as indicated by a write address signal 18. Input data 19 in address
And a storage circuit 4 for reading data from the address indicated by the read address signal 24 and outputting the data as output data 27; a synchronization signal 21; and inputting the synchronization signal 21 to a predetermined number of read-side clocks. 2
The buffer circuit 7 outputs the read-side synchronization signal 26 in accordance with the output data 27 output from the storage circuit 4 with a delay of 0.

The write control circuit 3 has a cell address A indicating an address for storing the cell 13 to be inputted.
In response to the synchronization detection signal 15 to count up and output the cell address signal A17, and a cell address generation circuit A32 for storing the input data 19 in the cell 13 to be input in response to the write-side synchronization signal 11. The data address A indicating the address is reset and the input data 1
9, the data address A is counted up to a predetermined number of data for each write-side clock 12 input in synchronization with the write-side clock 12, and the data address A is synchronized with the write-side clock 12 for each write-side clock 12. Data address generation circuit A3 output as A16
1, data address signal A16 and cell address signal A
17 and a write circuit 33 that outputs a write address signal 18 indicating an address for writing input data 19 in the cell 13 to be input to the storage circuit 4.

The read control circuit 6 has a cell address B indicating an address for reading the cell 25 to be output.
Cell address generation circuit B6 which counts up in response to a synchronization signal 21 and outputs the same as a cell address signal B23.
2 and in response to the synchronization signal 21, reset the data address B indicating the address for reading the output data 27 in the output cell 25, and for each read-side clock 20 input in synchronization with the output data 27. The data address B is counted up to a predetermined number of data.
A data address generation circuit B61 for outputting a data address B as a data address signal B22 every time; an output data 27 in a cell 25 for receiving the data address signal B22 and the cell address signal B23 and outputting from the storage circuit 4
And a read circuit 63 that outputs a read address signal 24 indicating an address for reading the data.

Next, the operation of the cell processing circuit according to the present embodiment will be described in detail with reference to FIGS.

FIG. 2 is a timing chart showing an example of a write operation when a cell having input data is written in the storage circuit. The write-side synchronization signal 11, the write-side clock 12, the input data 19, the data count signal 14, The synchronization detection signal 15, the data address signal A16,
Cell address signal A17 and write address signal 18
Are written along the time axis, and the respective signals indicate that they are synchronized with the write-side clock 12, respectively. When the input data 19 is written to the storage circuit 4 for each cell, The timing of the signal of FIG. Then, (A) synchronizes input data 19 in a cell having a predetermined number of data of, for example, 53 (hereinafter, such a cell is referred to as a fixed-length cell) with the write-side clock 12. This shows that data is written to the cell address n of the storage circuit 4. (B)
Input data 19 in a cell having a smaller number of data (for example, 52) than the predetermined number of data (for example, 53) (hereinafter, such a cell is referred to as a short cell) is synchronized with the write-side clock 12. And n +
1 shows that writing to the cell address 1 is performed.
(C) shows 53 of the input data 19 in a cell having a data number (for example, 54) larger than a predetermined data number (for example, 53) (hereinafter, such a cell is described as a long cell). In this example, more than 53 data, that is, the 54th data is discarded at the (n + 1) th cell address of the storage circuit 4 in synchronization with the write-side clock 12. Then, since the input data 19 is overwritten on the cell address of (n + 1) in (C), (B)
The short cell written to the cell address of (n + 1) is discarded. (D) shows that the input data 19 in the fixed-length cell is written to the (n + 1) -th cell address of the storage circuit 4 in synchronization with the write-side clock 12. Therefore, in (D), the input data 19 is
Of the long cell written to the (n + 1) cell address in (C), the 53 data are discarded.

FIG. 3 is a timing chart showing an example of an output operation for outputting a cell having the output data 27. The output side clock 20, the synchronization signal 21, the data address signal B22, the cell address signal B23, and the read address signal 24 are shown. , Output data 27 and read-side synchronization signal 26 are respectively described along the time axis, and indicate that each signal is synchronized with the read-side clock 20, respectively. 4 shows the timing of each signal when the output data 27 is output to the. (A) reads data from the cell address of m in the storage circuit 4 indicated by the read address signal 24 and outputs the read data to the output data 2.
7 and is output in synchronization with the read-side clock 20, and the read-side synchronization signal 26 is synchronized with the first output data 27 of the cell address of m which is the head of the fixed-length cell of the output data 27. In this case, a fixed-length cell is output in such a manner as to output a fixed-length cell. (B) reads data from the (m + 1) cell address of the storage circuit 4 indicated by the read address signal 24 and outputs the read data as output data 27 in synchronization with the read clock 20 as in (A). At the same time, a fixed-length cell is output by synchronizing the read-side synchronization signal 26 with the first output data 27 of the (m + 1) -th cell address at the head of the fixed-length cell of the output data 27 and outputting the same. It shows how to do it.

In FIG. 1, as shown in FIG. 2, in order to write the input data 19 in the cell 13 to be input into the storage circuit 4, the data count circuit 1 adds the first input data 19 in the cell 13 to be input. In response to the write-side synchronization signal 11 input in synchronization, the count value of the number of write-side clocks 12 input in synchronization with each input data 19 in the input cell 13 is reset to 1, and The number of side clocks 12 is set to a predetermined data number (for example, 5
After counting three (3), a data count signal 14 indicating that the counting is completed is output.

The AND circuit 2 outputs the data count signal 14
A synchronization detection signal 15 is output when the data and the write-side synchronization signal 11 are synchronized.

The write control circuit 3 outputs a synchronization detection signal 15
Write address signal 18 indicating an address for storing input data 19 in cell 13 to be input in response to write-side synchronization signal 11 and write-side clock 12.
Is output. That is, the cell address generation circuit A32
Counts up a cell address A indicating an address for storing the input cell 13 in response to the synchronization detection signal 15 and outputs it as a cell address signal A17. The data address generation circuit A31 outputs In response, the data address A indicating the address for storing the input data 19 in the cell 13 to be input is reset to 1, and the predetermined data for each write-side clock 12 input in synchronization with the input data 19 is reset. Number (for example, 53
), And the data address A is counted up to the data address signal A1 for each write clock 12 in synchronization with the write clock 12.
Output as 6. Then, the write circuit 33 receives the data address signal A16 and the cell address signal A17, and inputs the data address signal A16 and the cell address signal indicating an address for writing the input data 19 in the cell 13 to be input to the storage circuit 4. A17 is output.

The storage circuit 4 receives an input cell 13 having input data 19 and stores the input data 19 at an address indicated by a write address signal 18.

In this way, when the input cell 13 is a fixed-length cell, as shown in FIG. 2A, 53 pieces of input data 19 have the cell addresses n and n.
Data addresses are written to addresses of the storage circuit 4 indicated by 1 to 53, respectively. Cell 1 to be input
When 3 is a short cell, as shown in FIG. 2B, 52 pieces of input data 19 have a cell address of n +
1, a storage circuit 4 in which data addresses are indicated by 1 to 52
, And the input data 19 of the cell 13 to be input next is overwritten on the written input data 19, so that the short cell is discarded. When the input cell 13 is a long cell, as shown in FIG. 2C, only 53 of the 54 input data 19 have a cell address of n + 1 and a data address of n + 1. The data is written to the addresses of the storage circuit 4 indicated by 1 to 53, and more than 53 data, that is, the 54th data is discarded.
This long cell is discarded by writing on the 53 pieces of input data 19 written at the cell address of +1.

Next, in order to read out the input data 19 written in the storage circuit 4 and output it as output data 27, as shown in FIG. 53) is output.

The read control circuit 6 controls the output cell 25
A read address indicating an address for reading out the output data 27 in the cell 25 to be output from the storage circuit 4 in response to the read-side clock 20 and the synchronization signal 21 input in synchronization with each output data 27 in the The signal 24 is output. That is, the cell address generation circuit B62 counts up the cell address B indicating the address for reading the output cell 25 from the storage circuit 4 in response to the synchronization signal 21, outputs the cell address B as the cell address signal B23, and outputs the cell address signal B23. B61 stores the output data 27 in the cell 25 to be output in the storage circuit 4 in response to the synchronization signal 21.
And resets the data address B indicating the address to be read from to 1 and counts up the data address B to a predetermined number of data (for example, 53) for each read-side clock 20 input in synchronization with the output data 27 The data address B is output as a data address signal B22 in synchronization with the read-side clock 20 for each read-side clock 20. And the read circuit 6
3 is a data address signal B22 and a cell address signal B
23 and output data 2 in the cell 25 to be output.
A read address signal 24 having a data address signal B22 indicating an address for reading 7 from the storage circuit 4 and a cell address signal B23 is output.

The storage circuit 4 has a read address signal 24
The data is read from the address indicated by, and this data is output as output data 27.

The buffer circuit 7 receives the synchronization signal 21, delays the synchronization signal 21 by a predetermined number (for example, three) of read-side clocks 20, and outputs the output data 27 output from the storage circuit 4. The output data 27 is output as a read-side synchronization signal 26 for use as the leading output data 27 of the cell 25 to be output.

By doing so, as shown in FIG. 3, the fixed-length cells stored in the storage circuit 4 are read out and output in the order of the cell addresses.

In the above description, the number of data in the fixed-length cell is set to 53.
4 may be used. The relationship between a write address (cell address A and data address A) and a read address (cell address B and data address B) is generally
The read address is set to follow the write address, but the read address does not overtake the write address. Further, the writing clock 12 and the reading clock 20 are usually set to have the same frequency and to shift the phase.

[0032]

As described above, according to the cell processing circuit of the present invention, when a cell having a smaller number of data than a predetermined number of data is received, the next cell to be received is overwritten on this cell. When discarding this cell and receiving a cell having a larger number of data than the predetermined number of data, discarding more data than the predetermined number of data from this cell and disposing of the cell having the predetermined number of data. , And the next received cell is overwritten on this cell and this cell is discarded, so that only reliable cells can be output. For this reason, since unreliable cells are not transmitted, since there is no unreliable cell on the line, there is no danger that the transmission band will be squeezed for other valid cells.

[Brief description of the drawings]

FIG. 1 is a block diagram showing one embodiment of a cell processing circuit of the present invention.

FIG. 2 is a timing chart illustrating an example of a write operation when writing a cell having input data to a storage circuit.

FIG. 3 is a timing chart showing an example of an output operation for outputting a cell having output data.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 data count circuit 2 AND circuit 3 write control circuit 4 storage circuit 5 synchronization signal generation circuit 6 read control circuit 7 buffer circuit 11 write side synchronization signal 12 write side clock 13 input cell 14 data count signal 15 synchronization detection signal 16 data address Signal A 17 Cell address signal A 18 Write address signal 19 Input data 20 Read clock 21 Synchronous signal 22 Data address signal B 23 Cell address signal B 24 Read address signal 25 Cell to be output 26 Read synchronous signal 27 Output data 31 Data address Generation circuit A 32 Cell address generation circuit A 33 Write circuit 61 Data address generation circuit B 62 Cell address generation circuit B 63 Read circuit

Claims (5)

[Claims] 1. A cell processing circuit wherein cells having a predetermined number of data are passed through and cells other than cells having a predetermined number of data are discarded. 2. When a cell having a smaller number of data than a predetermined number of data is received, the cell is stored as it is, and the next cell to be received is overwritten and stored on the stored cell. When a cell having a smaller number of data than the predetermined number of data is discarded and a cell having a larger number of data than the predetermined number of data is received, data of a larger number than the predetermined number of data is received from this cell. Is discarded and stored as a cell having the predetermined data number, and a cell having a data number larger than the predetermined data number is discarded by overwriting and storing the next received cell on the stored cell. 2. The cell processing circuit according to claim 1, wherein 3. The write-side input in synchronization with each of the input data in the input cell in response to a write-side synchronization signal input in synchronization with the first input data in the input cell. A data count circuit that resets a count value of the number of clocks, outputs a data count signal indicating that counting has been completed after counting the number of the write-side clocks by the predetermined number of data, and the data count signal. And an AND circuit for outputting a synchronization detection signal when the write-side synchronization signal and the write-side synchronization signal are synchronized. The input in the cell to be input in response to the synchronization detection signal, the write-side synchronization signal, and the write-side clock A write control circuit that outputs a write address signal indicating an address for storing data; and A synchronizing signal generation circuit for outputting a synchronizing signal defining an interval for outputting cells having the cell; a read-side clock input in synchronization with each output data in the output cell; and the output in response to the synchronizing signal. A read control circuit for outputting a read address signal indicating an address for reading the output data in a cell to be read; receiving the input data and storing the input data at an address indicated by the write address signal; A storage circuit for reading data from the address indicated by, and outputting the data as the output data; and inputting the synchronization signal, delaying the synchronization signal by a predetermined number of the read-side clocks, and A buffer circuit that outputs a read-side synchronization signal in accordance with output data to be output; The cell processing circuit according to claim 1, further comprising: 4. The cell address generation circuit A which counts up a cell address A indicating an address for storing the input cell in response to the synchronization detection signal and outputs the cell address A as a cell address signal A. And resetting a data address A indicating an address for storing the input data in the input cell in response to the write-side synchronization signal, and writing the write-side clock input in synchronization with the input data. A data address generation circuit A that counts up the data address A to the predetermined number of data every time, and outputs the data address A as a data address signal A for each write clock in synchronization with the write clock. Receiving the data address signal A and the cell address signal A, and Cell processing circuit according to claim 3, characterized by comprising a write circuit, the outputs of the write address signal indicating an address for writing the input data in a cell to the input to. 5. A cell address generation circuit B which counts up a cell address B indicating an address for reading the output cell in response to the synchronization signal and outputs the cell address B as a cell address signal B, In response to the synchronization signal, reset a data address B indicating an address for reading the output data in the cell to be output, and reset the data address B for each of the read-side clocks input in synchronization with the output data. A data address generation circuit B that counts up the data address B up to the number of data, and outputs the data address B as a data address signal B for each read-side clock in synchronization with the read-side clock; B and the cell address signal B, and receives the output from the storage circuit. Cell processing circuit according to claim 3, characterized in that and a reading circuit that outputs a read address signal indicating an address for reading the output data in that cell.